blob: f989a758ee8e67ed5e6406005dc8fdc9263d6d8b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_pkg IS
SUBTYPE test_t IS std_ulogic_vector(7 DOWNTO 0);
TYPE test_array_t IS ARRAY (natural RANGE <>) OF test_t;
END PACKAGE test_pkg;
LIBRARY work;
USE work.test_pkg.ALL;
ENTITY test IS
PORT (
a : IN test_array_t(0 TO 4) := (OTHERS => (OTHERS => '0'));
b : IN test_array_t(0 TO 4) := ((OTHERS => (OTHERS => '0'))));
END ENTITY test;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
|
