blob: 042a64d8f91010eb3c798402227d931656cb59d9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
entity t5 is
end t5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of t5 is
signal s : std_logic := '0';
begin
b: block
port (p : out std_logic := 'Z');
port map (p => s);
begin
end block;
b2: block
port (p : out std_logic := '1');
port map (p => s);
begin
end block;
process
begin
wait for 1 ns;
assert s = 'X' severity failure;
wait;
end process;
end behav;
|
