blob: 3fc5e2e96042d489036d9564bb4bb9e48d92fa94 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
entity repro is
port
(
clk : in bit;
rst : in bit;
data_out : out bit_vector(7 downto 0)
);
end ;
architecture arch1 of repro is
--
-- NOTE: placing port attributes here in the architecture body is illegal in VHDL,
-- but unfortunately Vivado requires them here to parse the X_INTERFACE attributes
--
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_INFO of rst : signal is "xilinx.com:signal:reset:1.0 rst RST";
attribute X_INTERFACE_PARAMETER of rst : signal is "POLARITY ACTIVE_HIGH";
begin
end arch1;
|
