blob: 3181eb3d4aeff70cde74e8b16e9af21435ee84c6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
library ieee;
use ieee.std_logic_1164.all;
package wishbone_pkg is
type t_wishbone_master_out is record
dat : std_logic_vector;
-- Works properly when field we is declared before dat
we : std_logic;
end record;
end wishbone_pkg;
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
entity wb_demux_tb is
end entity;
architecture bench of wb_demux_tb is
signal s : t_wishbone_master_out(
dat(1 downto 0)
);
begin
stimulus : process
begin
wait for 1 ns;
s.dat <= "11";
wait for 1 ns;
s.dat <= "00";
wait for 1 ns;
report "pass";
std.env.finish;
end process;
end architecture;
|
