blob: 8b13577ffd38d7282e4a6a65ef66aa896367c98c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
use work.issue_pkg."=";
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = work.issue_pkg.one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
|
