testsuite/gna/issue912/mwe_entity.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity mwe_entity is
  port (
        input : in std_logic;
        output : out std_logic
  );
end mwe_entity;

architecture behav of mwe_entity is
begin
	process(input)
	begin
		output <= input;
	end process;
end behav;