blob: 0c52aa1b65ee69fdf874abc61b1ec65b9896a46e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb2 is
end;
architecture arch of tb2 is
signal a, b : std_logic := '0';
begin
ainst: alib.apkg.acomp
port map (a, b);
process is
begin
a <= '0';
wait for 1 ns;
assert b = '0' report "component is missing" severity failure;
a <= '1';
wait for 1 ns;
assert b = '1' report "component is missing" severity failure;
wait;
end process;
end architecture;
|
