testsuite/pyunit/libghdl/examples/comments/ent_inside.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity e2 is
  -- comments in design units (python doc-string style) :e2:
    -- might be multi line :e2:
    generic (
      -- comment before a generic :FREQUENCY:
        -- might be multiline :FREQUENCY:
        constant FREQUENCY : positive
    );
    port (
      signal Clock : in std_logic
    );
end entity;