testsuite/synth/issue1044/ent.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity ent is
	generic (
		VAL : real := 1.5
	);
	port (
		lt  : out std_logic
	);
end;

architecture a of ent is
   constant fmul : real := val * 5.0;
   constant fneg : real := -val;
begin
	lt  <= '1' when VAL  < 1.5 else '0';
end;