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library ieee;
use ieee.std_logic_1164.all;
entity simple01 is
port (a, b, c : in std_logic;
z : out std_logic);
end simple01;
architecture behav of simple01 is
begin
process(A, B, C)
variable temp : std_logic;
begin
temp := A and B;
Z <= temp or C;
end process;
end behav;
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