blob: de60ca324d7061c1a040b7c4d68073589e40f2e0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
|
entity tb_subprg01 is
end tb_subprg01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_subprg01 is
signal a, na : std_logic_vector (3 downto 0);
begin
dut: entity work.subprg01
port map (a, na);
process
begin
a <= x"0";
wait for 1 ns;
assert na = x"f" severity failure;
a <= x"5";
wait for 1 ns;
assert na = x"a" severity failure;
wait;
end process;
end behav;
|