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| author | David Shah <davey1576@gmail.com> | 2017-11-17 18:29:14 +0000 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2017-11-17 18:29:14 +0000 |
| commit | 614c60df255751b5b1348aae8e64c4035f22c422 (patch) | |
| tree | 043f03ed192bf4c0531e51961c1ae32e4a0cb1cb | |
| parent | 902e972cc50736f0bcdc5888edbe38e9b9815ec3 (diff) | |
| download | icestorm-614c60df255751b5b1348aae8e64c4035f22c422.tar.gz icestorm-614c60df255751b5b1348aae8e64c4035f22c422.tar.bz2 icestorm-614c60df255751b5b1348aae8e64c4035f22c422.zip | |
Add missing 5k BRAM bits
| -rw-r--r-- | icebox/iceboxdb.py | 345 | ||||
| -rw-r--r-- | icefuzz/cached_dsp3_5k.txt | 5 | ||||
| -rw-r--r-- | icefuzz/cached_ramb_5k.txt | 486 | ||||
| -rw-r--r-- | icefuzz/cached_ramt_5k.txt | 448 |
4 files changed, 1277 insertions, 7 deletions
diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index a8b6990..61c0757 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -6742,6 +6742,7 @@ B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 @@ -6749,27 +6750,53 @@ B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 !B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 +!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 +!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 -!B12[0],B12[1],B13[0] buffer glb_netwk_1 glb2local_3 +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 -B12[0],B12[1],B13[0] buffer glb_netwk_3 glb2local_3 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE -B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 -B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 @@ -6785,6 +6812,7 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 @@ -6797,10 +6825,13 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 @@ -6811,6 +6842,7 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 @@ -6825,25 +6857,34 @@ B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 +B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 @@ -6852,11 +6893,13 @@ B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 @@ -6865,7 +6908,9 @@ B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_ !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 @@ -6877,19 +6922,26 @@ B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDAT !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 @@ -6899,7 +6951,10 @@ B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 @@ -6921,18 +6976,28 @@ B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 @@ -6942,7 +7007,11 @@ B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 @@ -6953,6 +7022,7 @@ B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 @@ -6960,11 +7030,13 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 @@ -6980,6 +7052,7 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 @@ -6990,6 +7063,7 @@ B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 @@ -7004,32 +7078,47 @@ B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 +B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 @@ -7054,7 +7143,9 @@ B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 @@ -7064,12 +7155,15 @@ B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 +!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 @@ -7077,6 +7171,9 @@ B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_ !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -7091,6 +7188,8 @@ B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 @@ -7099,10 +7198,15 @@ B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 @@ -7111,6 +7215,7 @@ B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 @@ -7125,7 +7230,10 @@ B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 @@ -7161,16 +7269,22 @@ B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 B12[19] buffer sp12_h_l_1 sp4_h_r_13 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 B8[2] buffer sp12_h_l_15 sp4_h_l_9 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 B10[2] buffer sp12_h_l_17 sp4_h_r_21 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 @@ -7179,6 +7293,7 @@ B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 B3[1] buffer sp12_h_l_9 sp4_h_r_17 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 @@ -7191,21 +7306,29 @@ B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_r_18 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 B6[2] buffer sp12_h_r_14 sp4_h_l_6 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 B14[2] buffer sp12_h_r_22 sp4_h_r_23 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_r_16 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_b_12 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 @@ -7226,6 +7349,7 @@ B8[19] buffer sp12_v_b_19 sp4_v_t_8 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 B0[19] buffer sp12_v_b_3 sp4_v_b_13 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 @@ -7249,6 +7373,7 @@ B9[19] buffer sp12_v_t_14 sp4_v_b_20 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 B11[19] buffer sp12_v_t_18 sp4_v_t_11 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 B10[19] buffer sp12_v_t_20 sp4_v_b_23 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 @@ -7258,6 +7383,7 @@ B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 B4[19] buffer sp12_v_t_8 sp4_v_t_4 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 @@ -7270,7 +7396,9 @@ B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 @@ -7283,10 +7411,12 @@ B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 @@ -7304,6 +7434,7 @@ B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 @@ -7326,6 +7457,7 @@ B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 @@ -7339,6 +7471,7 @@ B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 @@ -7346,6 +7479,8 @@ B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 @@ -7420,6 +7555,7 @@ B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 @@ -7456,11 +7592,14 @@ B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 @@ -7502,44 +7641,69 @@ B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 +B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 +B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 +B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 +B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 +B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 +B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 +B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 +B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 @@ -7558,14 +7722,18 @@ B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 +B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 +B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 +B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 @@ -7578,11 +7746,14 @@ B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 +B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 +B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 +B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 @@ -7590,6 +7761,7 @@ B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 +B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 @@ -8009,20 +8181,38 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 -B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK -B8[0],B8[1],B9[1] buffer glb_netwk_6 glb2local_1 +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 @@ -8033,10 +8223,12 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 @@ -8048,29 +8240,41 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 @@ -8078,8 +8282,10 @@ B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 @@ -8089,6 +8295,9 @@ B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 @@ -8100,18 +8309,23 @@ B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 +!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 @@ -8123,6 +8337,9 @@ B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 @@ -8132,10 +8349,14 @@ B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 @@ -8143,6 +8364,7 @@ B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 @@ -8150,10 +8372,12 @@ B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 +B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 @@ -8169,17 +8393,24 @@ B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 @@ -8192,25 +8423,35 @@ B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 @@ -8223,6 +8464,7 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 @@ -8236,6 +8478,8 @@ B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 @@ -8246,9 +8490,12 @@ B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 @@ -8259,6 +8506,7 @@ B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 @@ -8283,6 +8531,7 @@ B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 @@ -8294,10 +8543,12 @@ B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 @@ -8322,6 +8573,7 @@ B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 @@ -8351,6 +8603,7 @@ B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 @@ -8363,6 +8616,7 @@ B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 @@ -8375,12 +8629,14 @@ B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 @@ -8395,10 +8651,12 @@ B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 @@ -8410,47 +8668,82 @@ B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 B14[2] buffer sp12_h_l_21 sp4_h_l_10 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_l_2 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_r_12 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 B3[1] buffer sp12_h_r_10 sp4_h_r_17 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_l_7 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 B8[2] buffer sp12_h_r_16 sp4_h_r_20 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 B10[2] buffer sp12_h_r_18 sp4_h_l_8 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 B12[19] buffer sp12_h_r_2 sp4_h_r_13 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_r_22 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_l_5 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_t_1 @@ -8458,6 +8751,7 @@ B1[19] buffer sp12_v_b_1 sp4_v_t_1 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 B4[19] buffer sp12_v_b_11 sp4_v_b_17 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 @@ -8499,9 +8793,11 @@ B8[19] buffer sp12_v_t_16 sp4_v_t_8 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 @@ -8509,6 +8805,7 @@ B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 @@ -8520,7 +8817,11 @@ B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 @@ -8539,6 +8840,7 @@ B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 @@ -8553,33 +8855,43 @@ B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 @@ -8742,9 +9054,11 @@ B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 @@ -8754,6 +9068,8 @@ B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 @@ -8770,11 +9086,16 @@ B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 +B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 @@ -8798,16 +9119,19 @@ B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 +B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 @@ -8842,7 +9166,9 @@ B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 +B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 @@ -8853,6 +9179,9 @@ B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 +B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 +B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 +B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 @@ -15871,6 +16200,7 @@ B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 @@ -15897,6 +16227,7 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 diff --git a/icefuzz/cached_dsp3_5k.txt b/icefuzz/cached_dsp3_5k.txt index f42a3f9..0979d71 100644 --- a/icefuzz/cached_dsp3_5k.txt +++ b/icefuzz/cached_dsp3_5k.txt @@ -22,6 +22,7 @@ (0 15) routing glb_netwk_6 <X> wire_mult/lc_7/s_r (0 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r (0 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 6) routing glb_netwk_2 <X> glb2local_0 (0 6) routing glb_netwk_3 <X> glb2local_0 (0 6) routing glb_netwk_6 <X> glb2local_0 (0 6) routing glb_netwk_7 <X> glb2local_0 @@ -76,6 +77,7 @@ (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 @@ -328,11 +330,13 @@ (13 9) routing sp4_h_l_40 <X> sp4_h_r_8 (13 9) routing sp4_v_b_2 <X> sp4_h_r_8 (13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing bnr_op_0 <X> lc_trk_g0_0 (14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 (14 0) routing sp4_h_l_5 <X> lc_trk_g0_0 (14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 (14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 (14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing bnr_op_0 <X> lc_trk_g0_0 (14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 (14 1) routing sp12_h_r_16 <X> lc_trk_g0_0 (14 1) routing sp4_h_l_5 <X> lc_trk_g0_0 @@ -691,6 +695,7 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt index 65c15e3..85d0e11 100644 --- a/icefuzz/cached_ramb_5k.txt +++ b/icefuzz/cached_ramb_5k.txt @@ -2,17 +2,30 @@ (0 10) routing glb_netwk_2 <X> glb2local_2 (0 10) routing glb_netwk_3 <X> glb2local_2 (0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 (0 11) routing glb_netwk_3 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_2 <X> glb2local_3 (0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 (0 13) routing glb_netwk_1 <X> glb2local_3 (0 13) routing glb_netwk_3 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 (0 14) routing glb_netwk_4 <X> wire_bram/ram/RE +(0 14) routing glb_netwk_6 <X> wire_bram/ram/RE (0 14) routing lc_trk_g2_4 <X> wire_bram/ram/RE (0 14) routing lc_trk_g3_5 <X> wire_bram/ram/RE +(0 15) routing glb_netwk_2 <X> wire_bram/ram/RE +(0 15) routing glb_netwk_6 <X> wire_bram/ram/RE (0 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE (0 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE (0 2) routing glb_netwk_2 <X> wire_bram/ram/RCLK (0 2) routing glb_netwk_3 <X> wire_bram/ram/RCLK +(0 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK (0 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK @@ -26,18 +39,43 @@ (0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 (0 7) routing glb_netwk_1 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 (0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 8) routing glb_netwk_6 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 (0 9) routing glb_netwk_5 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 (1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE @@ -48,6 +86,7 @@ (1 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE (1 2) routing glb_netwk_4 <X> wire_bram/ram/RCLK (1 2) routing glb_netwk_5 <X> wire_bram/ram/RCLK +(1 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK (1 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE @@ -59,10 +98,23 @@ (1 5) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 (1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 (1 9) routing glb_netwk_5 <X> glb2local_1 +(1 9) routing glb_netwk_6 <X> glb2local_1 (10 0) routing sp4_h_l_40 <X> sp4_h_r_1 (10 0) routing sp4_h_l_47 <X> sp4_h_r_1 (10 0) routing sp4_v_b_7 <X> sp4_h_r_1 @@ -396,10 +448,13 @@ (14 4) routing lft_op_0 <X> lc_trk_g1_0 (14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 (14 4) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 (14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 (14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 (14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0 (14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (14 5) routing sp4_h_r_16 <X> lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 (14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 @@ -414,6 +469,7 @@ (14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 (14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (14 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 (14 7) routing sp4_v_b_12 <X> lc_trk_g1_4 (14 8) routing bnl_op_0 <X> lc_trk_g2_0 @@ -426,6 +482,7 @@ (14 9) routing bnl_op_0 <X> lc_trk_g2_0 (14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 (14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0 (14 9) routing sp4_h_r_40 <X> lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 (14 9) routing sp4_v_b_32 <X> lc_trk_g2_0 @@ -434,7 +491,9 @@ (15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (15 0) routing sp4_v_t_4 <X> lc_trk_g0_1 +(15 1) routing bot_op_0 <X> lc_trk_g0_0 (15 1) routing lft_op_0 <X> lc_trk_g0_0 (15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 (15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 @@ -446,7 +505,9 @@ (15 10) routing sp4_h_r_29 <X> lc_trk_g2_5 (15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 (15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 (15 11) routing rgt_op_4 <X> lc_trk_g2_4 (15 11) routing sp12_v_b_4 <X> lc_trk_g2_4 (15 11) routing sp4_h_r_28 <X> lc_trk_g2_4 @@ -461,6 +522,8 @@ (15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 (15 12) routing sp4_h_r_33 <X> lc_trk_g3_1 (15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 12) routing tnr_op_1 <X> lc_trk_g3_1 (15 13) routing rgt_op_0 <X> lc_trk_g3_0 (15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 (15 13) routing sp4_h_r_24 <X> lc_trk_g3_0 @@ -468,6 +531,7 @@ (15 13) routing sp4_h_r_40 <X> lc_trk_g3_0 (15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 (15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 (15 14) routing rgt_op_5 <X> lc_trk_g3_5 (15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 (15 14) routing sp4_h_r_29 <X> lc_trk_g3_5 @@ -483,11 +547,14 @@ (15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (15 15) routing sp4_v_b_44 <X> lc_trk_g3_4 (15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 15) routing tnr_op_4 <X> lc_trk_g3_4 (15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_l_2 <X> lc_trk_g0_5 (15 2) routing sp4_h_r_13 <X> lc_trk_g0_5 (15 2) routing sp4_h_r_21 <X> lc_trk_g0_5 (15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 (15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing bot_op_4 <X> lc_trk_g0_4 (15 3) routing lft_op_4 <X> lc_trk_g0_4 (15 3) routing sp12_h_l_3 <X> lc_trk_g0_4 (15 3) routing sp4_h_l_1 <X> lc_trk_g0_4 @@ -503,32 +570,44 @@ (15 5) routing bot_op_0 <X> lc_trk_g1_0 (15 5) routing lft_op_0 <X> lc_trk_g1_0 (15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (15 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 (15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 (15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_l_2 <X> lc_trk_g1_5 (15 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (15 6) routing sp4_h_r_21 <X> lc_trk_g1_5 (15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 (15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 7) routing bot_op_4 <X> lc_trk_g1_4 (15 7) routing lft_op_4 <X> lc_trk_g1_4 (15 7) routing sp12_h_l_3 <X> lc_trk_g1_4 (15 7) routing sp4_h_l_1 <X> lc_trk_g1_4 (15 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 (15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 (15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 (15 8) routing sp4_h_r_33 <X> lc_trk_g2_1 (15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 (15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 8) routing tnr_op_1 <X> lc_trk_g2_1 (15 9) routing rgt_op_0 <X> lc_trk_g2_0 (15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0 (15 9) routing sp4_h_r_32 <X> lc_trk_g2_0 (15 9) routing sp4_h_r_40 <X> lc_trk_g2_0 (15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 (15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 9) routing tnr_op_0 <X> lc_trk_g2_0 +(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 (16 0) routing sp4_v_t_4 <X> lc_trk_g0_1 @@ -546,6 +625,7 @@ (16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 (16 10) routing sp4_v_t_24 <X> lc_trk_g2_5 (16 11) routing sp12_v_b_20 <X> lc_trk_g2_4 (16 11) routing sp12_v_t_11 <X> lc_trk_g2_4 @@ -587,6 +667,8 @@ (16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 (16 15) routing sp4_v_b_44 <X> lc_trk_g3_4 (16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 +(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_21 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 @@ -602,17 +684,23 @@ (16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 (16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 (16 4) routing sp12_h_l_14 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 (16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 (16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 (16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 (16 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0 (16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (16 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 +(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_21 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 @@ -623,6 +711,7 @@ (16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (16 7) routing sp4_h_l_1 <X> lc_trk_g1_4 (16 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (16 7) routing sp4_v_b_12 <X> lc_trk_g1_4 (16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 (16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 @@ -636,6 +725,7 @@ (16 8) routing sp4_v_t_20 <X> lc_trk_g2_1 (16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 (16 9) routing sp12_v_t_7 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0 (16 9) routing sp4_h_r_32 <X> lc_trk_g2_0 (16 9) routing sp4_h_r_40 <X> lc_trk_g2_0 (16 9) routing sp4_v_b_32 <X> lc_trk_g2_0 @@ -643,15 +733,19 @@ (16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 @@ -675,8 +769,10 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 @@ -705,6 +801,8 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 @@ -719,6 +817,7 @@ (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 @@ -748,9 +847,13 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 @@ -759,6 +862,7 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 @@ -775,6 +879,7 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 @@ -786,9 +891,12 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 @@ -796,6 +904,9 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 @@ -805,12 +916,14 @@ (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 @@ -818,6 +931,7 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 @@ -829,11 +943,13 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 @@ -842,13 +958,16 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 <X> lc_trk_g0_1 (18 0) routing lft_op_1 <X> lc_trk_g0_1 (18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 (18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 (18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 (18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1 (18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 (18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 (18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 @@ -883,6 +1002,7 @@ (18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 (18 13) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 (18 14) routing bnl_op_5 <X> lc_trk_g3_5 (18 14) routing rgt_op_5 <X> lc_trk_g3_5 (18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 @@ -900,11 +1020,14 @@ (18 15) routing tnl_op_5 <X> lc_trk_g3_5 (18 2) routing bnr_op_5 <X> lc_trk_g0_5 (18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_l_2 <X> lc_trk_g0_5 (18 2) routing sp4_h_r_13 <X> lc_trk_g0_5 (18 2) routing sp4_h_r_21 <X> lc_trk_g0_5 (18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 (18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 (18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_l_2 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5 (18 3) routing sp4_h_r_21 <X> lc_trk_g0_5 (18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 @@ -925,22 +1048,27 @@ (18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 (18 6) routing bnr_op_5 <X> lc_trk_g1_5 (18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_l_2 <X> lc_trk_g1_5 (18 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (18 6) routing sp4_h_r_21 <X> lc_trk_g1_5 (18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 (18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_l_2 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5 (18 7) routing sp4_h_r_21 <X> lc_trk_g1_5 (18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 (18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 8) routing bnl_op_1 <X> lc_trk_g2_1 (18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 (18 8) routing sp4_h_r_33 <X> lc_trk_g2_1 (18 8) routing sp4_v_b_25 <X> lc_trk_g2_1 (18 8) routing sp4_v_t_20 <X> lc_trk_g2_1 (18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 (18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 (18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 (18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 @@ -972,6 +1100,7 @@ (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK @@ -988,6 +1117,7 @@ (21 0) routing lft_op_3 <X> lc_trk_g0_3 (21 0) routing sp12_h_r_3 <X> lc_trk_g0_3 (21 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 (21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 (21 1) routing bnr_op_3 <X> lc_trk_g0_3 @@ -1000,15 +1130,18 @@ (21 10) routing bnl_op_7 <X> lc_trk_g2_7 (21 10) routing rgt_op_7 <X> lc_trk_g2_7 (21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 10) routing sp4_v_b_31 <X> lc_trk_g2_7 (21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 (21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_20 <X> lc_trk_g2_7 (21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 (21 11) routing sp4_h_r_31 <X> lc_trk_g2_7 (21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 (21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 (21 12) routing bnl_op_3 <X> lc_trk_g3_3 (21 12) routing rgt_op_3 <X> lc_trk_g3_3 (21 12) routing sp12_v_b_3 <X> lc_trk_g3_3 @@ -1023,49 +1156,58 @@ (21 13) routing sp4_h_r_43 <X> lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 (21 13) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 (21 14) routing bnl_op_7 <X> lc_trk_g3_7 (21 14) routing rgt_op_7 <X> lc_trk_g3_7 (21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 (21 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 14) routing sp4_v_b_31 <X> lc_trk_g3_7 (21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (21 15) routing bnl_op_7 <X> lc_trk_g3_7 (21 15) routing sp12_v_t_20 <X> lc_trk_g3_7 (21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 (21 15) routing sp4_h_r_31 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 (21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 (21 15) routing tnl_op_7 <X> lc_trk_g3_7 (21 2) routing bnr_op_7 <X> lc_trk_g0_7 (21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7 (21 2) routing sp4_h_r_15 <X> lc_trk_g0_7 (21 2) routing sp4_h_r_23 <X> lc_trk_g0_7 (21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 (21 3) routing bnr_op_7 <X> lc_trk_g0_7 (21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 +(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7 (21 3) routing sp4_h_r_23 <X> lc_trk_g0_7 (21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 (21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 (21 4) routing lft_op_3 <X> lc_trk_g1_3 (21 4) routing sp12_h_r_3 <X> lc_trk_g1_3 (21 4) routing sp4_h_l_6 <X> lc_trk_g1_3 (21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 (21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 (21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 (21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 (21 5) routing sp12_h_r_3 <X> lc_trk_g1_3 (21 5) routing sp4_h_l_6 <X> lc_trk_g1_3 (21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 (21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing bnr_op_7 <X> lc_trk_g1_7 (21 6) routing lft_op_7 <X> lc_trk_g1_7 (21 6) routing sp12_h_r_7 <X> lc_trk_g1_7 (21 6) routing sp4_h_r_15 <X> lc_trk_g1_7 (21 6) routing sp4_h_r_23 <X> lc_trk_g1_7 (21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 7) routing bnr_op_7 <X> lc_trk_g1_7 (21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 (21 7) routing sp12_h_r_7 <X> lc_trk_g1_7 (21 7) routing sp4_h_r_23 <X> lc_trk_g1_7 @@ -1074,11 +1216,14 @@ (21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 (21 8) routing bnl_op_3 <X> lc_trk_g2_3 (21 8) routing rgt_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3 (21 8) routing sp4_h_r_43 <X> lc_trk_g2_3 (21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 (21 8) routing sp4_v_b_35 <X> lc_trk_g2_3 (21 9) routing bnl_op_3 <X> lc_trk_g2_3 (21 9) routing sp12_v_b_19 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3 (21 9) routing sp4_h_l_14 <X> lc_trk_g2_3 (21 9) routing sp4_h_r_43 <X> lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 @@ -1090,6 +1235,7 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 @@ -1097,9 +1243,11 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 @@ -1111,7 +1259,9 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 @@ -1119,6 +1269,8 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 @@ -1147,6 +1299,8 @@ (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 @@ -1161,6 +1315,7 @@ (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 @@ -1168,12 +1323,14 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 @@ -1184,6 +1341,7 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 @@ -1193,6 +1351,7 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1201,9 +1360,11 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 @@ -1212,6 +1373,7 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 @@ -1238,6 +1400,7 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 @@ -1251,19 +1414,26 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1286,14 +1456,17 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 (23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 (23 0) routing sp4_v_t_6 <X> lc_trk_g0_3 (23 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_18 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 @@ -1301,6 +1474,8 @@ (23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 (23 1) routing sp4_v_t_7 <X> lc_trk_g0_2 (23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_20 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (23 10) routing sp4_h_r_31 <X> lc_trk_g2_7 (23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (23 10) routing sp4_v_b_31 <X> lc_trk_g2_7 @@ -1334,6 +1509,7 @@ (23 14) routing sp12_v_t_20 <X> lc_trk_g3_7 (23 14) routing sp4_h_l_26 <X> lc_trk_g3_7 (23 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (23 14) routing sp4_v_b_31 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 @@ -1342,6 +1518,7 @@ (23 15) routing sp4_h_l_19 <X> lc_trk_g3_6 (23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 (23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 (23 15) routing sp4_v_t_19 <X> lc_trk_g3_6 (23 15) routing sp4_v_t_27 <X> lc_trk_g3_6 (23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 @@ -1352,6 +1529,7 @@ (23 2) routing sp4_v_b_23 <X> lc_trk_g0_7 (23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6 (23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 (23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 (23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 @@ -1384,12 +1562,17 @@ (23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 (23 7) routing sp12_h_r_14 <X> lc_trk_g1_6 +(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 (23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 (23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 (23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 (23 7) routing sp4_v_t_11 <X> lc_trk_g1_6 (23 8) routing sp12_v_b_19 <X> lc_trk_g2_3 +(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3 (23 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3 (23 8) routing sp4_h_r_43 <X> lc_trk_g2_3 (23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 (23 8) routing sp4_v_b_35 <X> lc_trk_g2_3 @@ -1405,8 +1588,10 @@ (24 0) routing lft_op_3 <X> lc_trk_g0_3 (24 0) routing sp12_h_r_3 <X> lc_trk_g0_3 (24 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (24 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(24 1) routing bot_op_2 <X> lc_trk_g0_2 (24 1) routing lft_op_2 <X> lc_trk_g0_2 (24 1) routing sp12_h_l_1 <X> lc_trk_g0_2 (24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 @@ -1415,9 +1600,12 @@ (24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 (24 10) routing rgt_op_7 <X> lc_trk_g2_7 (24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (24 10) routing sp4_h_r_31 <X> lc_trk_g2_7 (24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (24 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 (24 11) routing rgt_op_6 <X> lc_trk_g2_6 (24 11) routing sp12_v_t_5 <X> lc_trk_g2_6 (24 11) routing sp4_h_l_19 <X> lc_trk_g2_6 @@ -1432,6 +1620,8 @@ (24 12) routing sp4_h_l_22 <X> lc_trk_g3_3 (24 12) routing sp4_h_r_43 <X> lc_trk_g3_3 (24 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 (24 13) routing rgt_op_2 <X> lc_trk_g3_2 (24 13) routing sp12_v_t_1 <X> lc_trk_g3_2 (24 13) routing sp4_h_l_15 <X> lc_trk_g3_2 @@ -1439,24 +1629,30 @@ (24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 (24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 (24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 (24 14) routing rgt_op_7 <X> lc_trk_g3_7 (24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 (24 14) routing sp4_h_l_26 <X> lc_trk_g3_7 (24 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 (24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 (24 15) routing rgt_op_6 <X> lc_trk_g3_6 (24 15) routing sp12_v_t_5 <X> lc_trk_g3_6 (24 15) routing sp4_h_l_19 <X> lc_trk_g3_6 (24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 (24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 (24 15) routing tnl_op_6 <X> lc_trk_g3_6 (24 15) routing tnr_op_6 <X> lc_trk_g3_6 (24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_15 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_23 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 (24 2) routing sp4_v_b_23 <X> lc_trk_g0_7 +(24 3) routing bot_op_6 <X> lc_trk_g0_6 (24 3) routing lft_op_6 <X> lc_trk_g0_6 (24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 (24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 @@ -1482,6 +1678,7 @@ (24 6) routing sp4_h_r_23 <X> lc_trk_g1_7 (24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 (24 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(24 7) routing bot_op_6 <X> lc_trk_g1_6 (24 7) routing lft_op_6 <X> lc_trk_g1_6 (24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 (24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 @@ -1489,7 +1686,9 @@ (24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (24 7) routing sp4_v_t_11 <X> lc_trk_g1_6 (24 8) routing rgt_op_3 <X> lc_trk_g2_3 +(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3 (24 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3 (24 8) routing sp4_h_r_43 <X> lc_trk_g2_3 (24 8) routing sp4_v_b_43 <X> lc_trk_g2_3 (24 8) routing tnl_op_3 <X> lc_trk_g2_3 @@ -1501,6 +1700,7 @@ (24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 (24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 (24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 (25 0) routing bnr_op_2 <X> lc_trk_g0_2 (25 0) routing lft_op_2 <X> lc_trk_g0_2 (25 0) routing sp12_h_l_1 <X> lc_trk_g0_2 @@ -1593,11 +1793,15 @@ (25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 (25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 (25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 (25 7) routing bnr_op_6 <X> lc_trk_g1_6 (25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 (25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 (25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 (25 8) routing bnl_op_2 <X> lc_trk_g2_2 (25 8) routing rgt_op_2 <X> lc_trk_g2_2 (25 8) routing sp12_v_t_1 <X> lc_trk_g2_2 @@ -1742,8 +1946,11 @@ (26 9) routing lc_trk_g3_3 <X> input0_4 (26 9) routing lc_trk_g3_7 <X> input0_4 (27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (27 1) routing lc_trk_g1_1 <X> input0_0 @@ -1754,10 +1961,14 @@ (27 1) routing lc_trk_g3_3 <X> input0_0 (27 1) routing lc_trk_g3_5 <X> input0_0 (27 1) routing lc_trk_g3_7 <X> input0_0 +(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (27 11) routing lc_trk_g1_0 <X> input0_5 (27 11) routing lc_trk_g1_2 <X> input0_5 (27 11) routing lc_trk_g1_4 <X> input0_5 @@ -1784,8 +1995,12 @@ (27 13) routing lc_trk_g3_7 <X> input0_6 (27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 (27 15) routing lc_trk_g1_0 <X> input0_7 (27 15) routing lc_trk_g1_2 <X> input0_7 (27 15) routing lc_trk_g1_4 <X> input0_7 @@ -1796,9 +2011,12 @@ (27 15) routing lc_trk_g3_6 <X> input0_7 (27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 (27 3) routing lc_trk_g1_0 <X> input0_1 (27 3) routing lc_trk_g1_2 <X> input0_1 (27 3) routing lc_trk_g1_4 <X> input0_1 @@ -1823,7 +2041,10 @@ (27 5) routing lc_trk_g3_3 <X> input0_2 (27 5) routing lc_trk_g3_5 <X> input0_2 (27 5) routing lc_trk_g3_7 <X> input0_2 +(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_12 +(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_12 +(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12 @@ -1837,10 +2058,12 @@ (27 7) routing lc_trk_g3_4 <X> input0_3 (27 7) routing lc_trk_g3_6 <X> input0_3 (27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 (27 9) routing lc_trk_g1_1 <X> input0_4 (27 9) routing lc_trk_g1_3 <X> input0_4 @@ -1852,8 +2075,10 @@ (27 9) routing lc_trk_g3_7 <X> input0_4 (28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (28 1) routing lc_trk_g2_0 <X> input0_0 @@ -1864,10 +2089,14 @@ (28 1) routing lc_trk_g3_3 <X> input0_0 (28 1) routing lc_trk_g3_5 <X> input0_0 (28 1) routing lc_trk_g3_7 <X> input0_0 +(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (28 11) routing lc_trk_g2_1 <X> input0_5 (28 11) routing lc_trk_g2_3 <X> input0_5 (28 11) routing lc_trk_g2_5 <X> input0_5 @@ -1895,8 +2124,11 @@ (28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 (28 15) routing lc_trk_g2_1 <X> input0_7 (28 15) routing lc_trk_g2_3 <X> input0_7 (28 15) routing lc_trk_g2_5 <X> input0_7 @@ -1906,10 +2138,13 @@ (28 15) routing lc_trk_g3_4 <X> input0_7 (28 15) routing lc_trk_g3_6 <X> input0_7 (28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 (28 3) routing lc_trk_g2_1 <X> input0_1 (28 3) routing lc_trk_g2_3 <X> input0_1 (28 3) routing lc_trk_g2_5 <X> input0_1 @@ -1936,6 +2171,7 @@ (28 5) routing lc_trk_g3_7 <X> input0_2 (28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12 +(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12 @@ -1949,11 +2185,13 @@ (28 7) routing lc_trk_g3_2 <X> input0_3 (28 7) routing lc_trk_g3_4 <X> input0_3 (28 7) routing lc_trk_g3_6 <X> input0_3 +(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 +(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 (28 9) routing lc_trk_g2_0 <X> input0_4 (28 9) routing lc_trk_g2_2 <X> input0_4 @@ -1965,12 +2203,18 @@ (28 9) routing lc_trk_g3_7 <X> input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 @@ -1993,11 +2237,18 @@ (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 @@ -2047,15 +2298,21 @@ (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 @@ -2073,16 +2330,21 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 @@ -2133,9 +2395,15 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -2158,15 +2426,20 @@ (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 @@ -2216,22 +2489,38 @@ (3 8) routing sp12_v_t_22 <X> sp12_v_b_1 (3 9) routing sp12_h_l_22 <X> sp12_v_b_1 (3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_9 @@ -2250,21 +2539,36 @@ (30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9 (30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 (30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 (30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_13 @@ -2281,22 +2585,33 @@ (30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13 +(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 +(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 +(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 @@ -2305,58 +2620,89 @@ (31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 +(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14 +(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 +(31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_13 @@ -2364,25 +2710,40 @@ (31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 (31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 @@ -2390,39 +2751,60 @@ (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 @@ -2444,10 +2826,16 @@ (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 @@ -2460,34 +2848,44 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 @@ -2495,37 +2893,57 @@ (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 (33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 +(33 11) routing lc_trk_g2_1 <X> input2_5 (33 11) routing lc_trk_g2_3 <X> input2_5 +(33 11) routing lc_trk_g2_5 <X> input2_5 +(33 11) routing lc_trk_g2_7 <X> input2_5 (33 11) routing lc_trk_g3_0 <X> input2_5 +(33 11) routing lc_trk_g3_2 <X> input2_5 (33 11) routing lc_trk_g3_4 <X> input2_5 (33 11) routing lc_trk_g3_6 <X> input2_5 (33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (33 13) routing lc_trk_g2_0 <X> input2_6 (33 13) routing lc_trk_g2_2 <X> input2_6 @@ -2539,10 +2957,14 @@ (33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (33 15) routing lc_trk_g2_1 <X> input2_7 (33 15) routing lc_trk_g2_3 <X> input2_7 (33 15) routing lc_trk_g2_5 <X> input2_7 +(33 15) routing lc_trk_g2_7 <X> input2_7 (33 15) routing lc_trk_g3_0 <X> input2_7 (33 15) routing lc_trk_g3_2 <X> input2_7 (33 15) routing lc_trk_g3_4 <X> input2_7 @@ -2552,10 +2974,13 @@ (33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_14 +(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 (33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 @@ -2563,34 +2988,50 @@ (33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 (34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 (34 11) routing lc_trk_g1_0 <X> input2_5 +(34 11) routing lc_trk_g1_2 <X> input2_5 (34 11) routing lc_trk_g1_4 <X> input2_5 +(34 11) routing lc_trk_g1_6 <X> input2_5 (34 11) routing lc_trk_g3_0 <X> input2_5 +(34 11) routing lc_trk_g3_2 <X> input2_5 (34 11) routing lc_trk_g3_4 <X> input2_5 (34 11) routing lc_trk_g3_6 <X> input2_5 +(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (34 13) routing lc_trk_g1_1 <X> input2_6 (34 13) routing lc_trk_g1_3 <X> input2_6 @@ -2601,6 +3042,12 @@ (34 13) routing lc_trk_g3_5 <X> input2_6 (34 13) routing lc_trk_g3_7 <X> input2_6 (34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (34 15) routing lc_trk_g1_0 <X> input2_7 (34 15) routing lc_trk_g1_2 <X> input2_7 @@ -2610,11 +3057,15 @@ (34 15) routing lc_trk_g3_2 <X> input2_7 (34 15) routing lc_trk_g3_4 <X> input2_7 (34 15) routing lc_trk_g3_6 <X> input2_7 +(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 +(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 @@ -2626,19 +3077,33 @@ (34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 +(35 10) routing lc_trk_g0_5 <X> input2_5 (35 10) routing lc_trk_g0_7 <X> input2_5 (35 10) routing lc_trk_g1_4 <X> input2_5 +(35 10) routing lc_trk_g1_6 <X> input2_5 +(35 10) routing lc_trk_g2_5 <X> input2_5 +(35 10) routing lc_trk_g2_7 <X> input2_5 (35 10) routing lc_trk_g3_4 <X> input2_5 (35 10) routing lc_trk_g3_6 <X> input2_5 (35 11) routing lc_trk_g0_3 <X> input2_5 (35 11) routing lc_trk_g0_7 <X> input2_5 +(35 11) routing lc_trk_g1_2 <X> input2_5 +(35 11) routing lc_trk_g1_6 <X> input2_5 (35 11) routing lc_trk_g2_3 <X> input2_5 +(35 11) routing lc_trk_g2_7 <X> input2_5 +(35 11) routing lc_trk_g3_2 <X> input2_5 (35 11) routing lc_trk_g3_6 <X> input2_5 (35 12) routing lc_trk_g0_4 <X> input2_6 (35 12) routing lc_trk_g0_6 <X> input2_6 @@ -2661,6 +3126,7 @@ (35 14) routing lc_trk_g1_4 <X> input2_7 (35 14) routing lc_trk_g1_6 <X> input2_7 (35 14) routing lc_trk_g2_5 <X> input2_7 +(35 14) routing lc_trk_g2_7 <X> input2_7 (35 14) routing lc_trk_g3_4 <X> input2_7 (35 14) routing lc_trk_g3_6 <X> input2_7 (35 15) routing lc_trk_g0_3 <X> input2_7 @@ -2668,15 +3134,25 @@ (35 15) routing lc_trk_g1_2 <X> input2_7 (35 15) routing lc_trk_g1_6 <X> input2_7 (35 15) routing lc_trk_g2_3 <X> input2_7 +(35 15) routing lc_trk_g2_7 <X> input2_7 (35 15) routing lc_trk_g3_2 <X> input2_7 (35 15) routing lc_trk_g3_6 <X> input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 +(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 +(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 +(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 +(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 +(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 +(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 +(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 +(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 +(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 @@ -2695,15 +3171,20 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 +(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 +(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 +(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 +(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 +(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 @@ -2785,8 +3266,12 @@ (4 9) routing sp4_v_b_0 <X> sp4_h_r_6 (4 9) routing sp4_v_t_36 <X> sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 +(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 +(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 +(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 +(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 @@ -2805,6 +3290,7 @@ (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 +(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt index 768ae76..8f2669c 100644 --- a/icefuzz/cached_ramt_5k.txt +++ b/icefuzz/cached_ramt_5k.txt @@ -1,21 +1,34 @@ (0 0) Negative Clock bit (0 10) routing glb_netwk_3 <X> glb2local_2 (0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 (0 11) routing glb_netwk_3 <X> glb2local_2 (0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 +(0 13) routing glb_netwk_1 <X> glb2local_3 +(0 13) routing glb_netwk_3 <X> glb2local_3 (0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 (0 14) routing glb_netwk_4 <X> wire_bram/ram/WE (0 14) routing glb_netwk_6 <X> wire_bram/ram/WE (0 14) routing lc_trk_g2_4 <X> wire_bram/ram/WE (0 14) routing lc_trk_g3_5 <X> wire_bram/ram/WE +(0 15) routing glb_netwk_2 <X> wire_bram/ram/WE (0 15) routing glb_netwk_6 <X> wire_bram/ram/WE (0 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE (0 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE (0 2) routing glb_netwk_2 <X> wire_bram/ram/WCLK +(0 2) routing glb_netwk_3 <X> wire_bram/ram/WCLK +(0 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK (0 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK (0 3) routing glb_netwk_1 <X> wire_bram/ram/WCLK +(0 3) routing glb_netwk_3 <X> wire_bram/ram/WCLK (0 3) routing glb_netwk_5 <X> wire_bram/ram/WCLK (0 3) routing glb_netwk_7 <X> wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK @@ -25,18 +38,38 @@ (0 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE (0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 +(0 7) routing glb_netwk_1 <X> glb2local_0 (0 7) routing glb_netwk_3 <X> glb2local_0 (0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_3 <X> glb2local_1 (0 8) routing glb_netwk_6 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 <X> glb2local_2 (1 11) routing glb_netwk_5 <X> glb2local_2 (1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 (1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE @@ -49,6 +82,7 @@ (1 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE (1 2) routing glb_netwk_4 <X> wire_bram/ram/WCLK (1 2) routing glb_netwk_5 <X> wire_bram/ram/WCLK +(1 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK (1 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE @@ -59,10 +93,23 @@ (1 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 (1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 (1 9) routing glb_netwk_6 <X> glb2local_1 (10 0) routing sp4_h_l_40 <X> sp4_h_r_1 (10 0) routing sp4_h_l_47 <X> sp4_h_r_1 @@ -322,16 +369,20 @@ (13 9) routing sp4_v_t_38 <X> sp4_h_r_8 (14 0) routing bnr_op_0 <X> lc_trk_g0_0 (14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 (14 0) routing sp4_h_l_5 <X> lc_trk_g0_0 (14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 (14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 (14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 (14 1) routing bnr_op_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0 (14 1) routing sp4_h_l_5 <X> lc_trk_g0_0 (14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 (14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 (14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 (14 10) routing sp12_v_t_3 <X> lc_trk_g2_4 (14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 (14 10) routing sp4_h_r_44 <X> lc_trk_g2_4 @@ -347,21 +398,31 @@ (14 11) routing tnl_op_4 <X> lc_trk_g2_4 (14 12) routing bnl_op_0 <X> lc_trk_g3_0 (14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0 (14 12) routing sp4_h_l_29 <X> lc_trk_g3_0 (14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 (14 12) routing sp4_v_t_21 <X> lc_trk_g3_0 (14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 (14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0 (14 13) routing sp4_h_l_29 <X> lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 (14 13) routing sp4_v_t_21 <X> lc_trk_g3_0 (14 13) routing tnl_op_0 <X> lc_trk_g3_0 (14 14) routing bnl_op_4 <X> lc_trk_g3_4 (14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4 (14 14) routing sp4_v_b_28 <X> lc_trk_g3_4 (14 14) routing sp4_v_t_25 <X> lc_trk_g3_4 (14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4 (14 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 (14 15) routing sp4_v_t_25 <X> lc_trk_g3_4 (14 15) routing tnl_op_4 <X> lc_trk_g3_4 @@ -374,11 +435,13 @@ (14 2) routing sp4_v_t_1 <X> lc_trk_g0_4 (14 3) routing bnr_op_4 <X> lc_trk_g0_4 (14 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4 (14 3) routing sp4_h_r_20 <X> lc_trk_g0_4 (14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 (14 3) routing sp4_v_t_1 <X> lc_trk_g0_4 (14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 (14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 (14 4) routing sp4_h_l_5 <X> lc_trk_g1_0 (14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 @@ -386,6 +449,7 @@ (14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 (14 5) routing bnr_op_0 <X> lc_trk_g1_0 (14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0 (14 5) routing sp4_h_l_5 <X> lc_trk_g1_0 (14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 @@ -399,28 +463,34 @@ (14 6) routing sp4_v_t_1 <X> lc_trk_g1_4 (14 7) routing bnr_op_4 <X> lc_trk_g1_4 (14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (14 7) routing sp4_h_r_20 <X> lc_trk_g1_4 (14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 (14 7) routing sp4_v_t_1 <X> lc_trk_g1_4 (14 8) routing bnl_op_0 <X> lc_trk_g2_0 (14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 (14 8) routing sp4_h_l_21 <X> lc_trk_g2_0 (14 8) routing sp4_h_l_29 <X> lc_trk_g2_0 (14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 (14 8) routing sp4_v_t_21 <X> lc_trk_g2_0 (14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 (14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 (14 9) routing sp4_h_l_13 <X> lc_trk_g2_0 (14 9) routing sp4_h_l_29 <X> lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 (14 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 (15 0) routing lft_op_1 <X> lc_trk_g0_1 (15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (15 0) routing sp4_v_b_17 <X> lc_trk_g0_1 (15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 (15 1) routing sp4_h_l_5 <X> lc_trk_g0_0 (15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 (15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 @@ -428,10 +498,12 @@ (15 10) routing rgt_op_5 <X> lc_trk_g2_5 (15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 (15 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 (15 10) routing tnl_op_5 <X> lc_trk_g2_5 (15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 (15 11) routing sp12_v_t_3 <X> lc_trk_g2_4 (15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 (15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 @@ -439,13 +511,18 @@ (15 11) routing sp4_v_t_33 <X> lc_trk_g2_4 (15 11) routing tnl_op_4 <X> lc_trk_g2_4 (15 11) routing tnr_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 (15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1 (15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 (15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 (15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 (15 12) routing tnl_op_1 <X> lc_trk_g3_1 (15 12) routing tnr_op_1 <X> lc_trk_g3_1 (15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0 (15 13) routing sp4_h_l_29 <X> lc_trk_g3_0 (15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 (15 13) routing tnl_op_0 <X> lc_trk_g3_0 @@ -454,11 +531,15 @@ (15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 (15 14) routing sp4_h_l_16 <X> lc_trk_g3_5 (15 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 (15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 (15 14) routing tnl_op_5 <X> lc_trk_g3_5 (15 14) routing tnr_op_5 <X> lc_trk_g3_5 (15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4 (15 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (15 15) routing sp4_v_t_33 <X> lc_trk_g3_4 (15 15) routing tnl_op_4 <X> lc_trk_g3_4 (15 15) routing tnr_op_4 <X> lc_trk_g3_4 @@ -480,6 +561,7 @@ (15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 (15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 (15 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 (15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 (15 5) routing sp4_h_l_5 <X> lc_trk_g1_0 (15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 @@ -497,6 +579,7 @@ (15 7) routing sp4_h_r_20 <X> lc_trk_g1_4 (15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 (15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (15 8) routing sp4_h_l_20 <X> lc_trk_g2_1 (15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 @@ -505,17 +588,22 @@ (15 8) routing tnl_op_1 <X> lc_trk_g2_1 (15 8) routing tnr_op_1 <X> lc_trk_g2_1 (15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 (15 9) routing sp4_h_l_13 <X> lc_trk_g2_0 (15 9) routing sp4_h_l_21 <X> lc_trk_g2_0 (15 9) routing sp4_h_l_29 <X> lc_trk_g2_0 (15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 (15 9) routing tnr_op_0 <X> lc_trk_g2_0 (16 0) routing sp12_h_l_6 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_17 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0 (16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 (16 1) routing sp4_h_l_5 <X> lc_trk_g0_0 (16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 @@ -526,6 +614,7 @@ (16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 (16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 (16 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 (16 10) routing sp4_v_b_37 <X> lc_trk_g2_5 @@ -540,6 +629,7 @@ (16 11) routing sp4_v_t_33 <X> lc_trk_g2_4 (16 12) routing sp12_v_b_17 <X> lc_trk_g3_1 (16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1 (16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 (16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 (16 12) routing sp4_v_b_25 <X> lc_trk_g3_1 @@ -547,6 +637,8 @@ (16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 (16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 (16 13) routing sp12_v_t_7 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0 (16 13) routing sp4_h_l_29 <X> lc_trk_g3_0 (16 13) routing sp4_v_b_40 <X> lc_trk_g3_0 (16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 @@ -555,13 +647,19 @@ (16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 (16 14) routing sp4_h_l_16 <X> lc_trk_g3_5 (16 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 (16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 (16 14) routing sp4_v_b_37 <X> lc_trk_g3_5 (16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 +(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4 (16 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 (16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 (16 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5 (16 2) routing sp12_h_r_13 <X> lc_trk_g0_5 (16 2) routing sp4_h_l_8 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 @@ -569,6 +667,8 @@ (16 2) routing sp4_v_b_13 <X> lc_trk_g0_5 (16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 (16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4 (16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 (16 3) routing sp4_h_r_20 <X> lc_trk_g0_4 (16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 @@ -583,6 +683,7 @@ (16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_17 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0 (16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 (16 5) routing sp4_h_l_5 <X> lc_trk_g1_0 (16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 @@ -590,12 +691,16 @@ (16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5 +(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5 (16 6) routing sp4_h_l_8 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 (16 6) routing sp4_v_b_13 <X> lc_trk_g1_5 (16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 (16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 (16 7) routing sp4_h_r_20 <X> lc_trk_g1_4 (16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 @@ -622,6 +727,8 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 @@ -631,6 +738,8 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 @@ -646,6 +755,7 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 @@ -655,6 +765,7 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 @@ -669,9 +780,11 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 @@ -683,8 +796,11 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 @@ -700,6 +816,7 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 @@ -709,7 +826,12 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 @@ -720,6 +842,7 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 @@ -733,6 +856,8 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 @@ -754,7 +879,9 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 @@ -766,6 +893,8 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 @@ -778,6 +907,8 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 @@ -787,6 +918,7 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 @@ -802,6 +934,7 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 @@ -812,6 +945,7 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 <X> lc_trk_g0_1 (18 0) routing lft_op_1 <X> lc_trk_g0_1 @@ -822,12 +956,15 @@ (18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 (18 1) routing bnr_op_1 <X> lc_trk_g0_1 (18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 (18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 (18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 (18 10) routing bnl_op_5 <X> lc_trk_g2_5 (18 10) routing rgt_op_5 <X> lc_trk_g2_5 (18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 (18 10) routing sp4_v_b_37 <X> lc_trk_g2_5 @@ -840,7 +977,9 @@ (18 11) routing sp4_v_b_37 <X> lc_trk_g2_5 (18 11) routing tnl_op_5 <X> lc_trk_g2_5 (18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 (18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1 (18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 (18 12) routing sp4_v_b_25 <X> lc_trk_g3_1 (18 12) routing sp4_v_b_33 <X> lc_trk_g3_1 @@ -856,12 +995,14 @@ (18 14) routing rgt_op_5 <X> lc_trk_g3_5 (18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 (18 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 (18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 (18 14) routing sp4_v_b_37 <X> lc_trk_g3_5 (18 15) routing bnl_op_5 <X> lc_trk_g3_5 (18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 (18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 (18 15) routing sp4_h_l_16 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 (18 15) routing sp4_v_b_37 <X> lc_trk_g3_5 (18 15) routing tnl_op_5 <X> lc_trk_g3_5 @@ -873,6 +1014,7 @@ (18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 (18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 (18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5 (18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 (18 3) routing sp4_h_l_8 <X> lc_trk_g0_5 (18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 @@ -900,12 +1042,14 @@ (18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 (18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5 (18 7) routing sp12_h_r_5 <X> lc_trk_g1_5 (18 7) routing sp4_h_l_8 <X> lc_trk_g1_5 (18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 (18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 (18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (18 8) routing sp4_h_l_20 <X> lc_trk_g2_1 (18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 @@ -941,8 +1085,10 @@ (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK @@ -956,6 +1102,7 @@ (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 (21 0) routing sp12_h_l_0 <X> lc_trk_g0_3 (21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (21 0) routing sp4_h_r_19 <X> lc_trk_g0_3 @@ -963,11 +1110,15 @@ (21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 (21 1) routing bnr_op_3 <X> lc_trk_g0_3 (21 1) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3 (21 1) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 (21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 (21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 (21 10) routing sp12_v_b_7 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 10) routing sp4_v_t_18 <X> lc_trk_g2_7 (21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 @@ -978,6 +1129,7 @@ (21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 (21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 (21 12) routing bnl_op_3 <X> lc_trk_g3_3 (21 12) routing rgt_op_3 <X> lc_trk_g3_3 (21 12) routing sp12_v_t_0 <X> lc_trk_g3_3 @@ -996,21 +1148,28 @@ (21 14) routing bnl_op_7 <X> lc_trk_g3_7 (21 14) routing rgt_op_7 <X> lc_trk_g3_7 (21 14) routing sp12_v_b_7 <X> lc_trk_g3_7 +(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 14) routing sp4_v_t_18 <X> lc_trk_g3_7 (21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (21 15) routing bnl_op_7 <X> lc_trk_g3_7 (21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 (21 15) routing sp12_v_b_7 <X> lc_trk_g3_7 (21 15) routing sp4_h_l_18 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 (21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 (21 2) routing bnr_op_7 <X> lc_trk_g0_7 (21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7 (21 2) routing sp4_h_l_10 <X> lc_trk_g0_7 (21 2) routing sp4_h_l_2 <X> lc_trk_g0_7 (21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 (21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7 +(21 3) routing sp12_h_r_23 <X> lc_trk_g0_7 (21 3) routing sp4_h_l_10 <X> lc_trk_g0_7 (21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 @@ -1024,22 +1183,27 @@ (21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 (21 5) routing bnr_op_3 <X> lc_trk_g1_3 (21 5) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 (21 5) routing sp4_h_r_19 <X> lc_trk_g1_3 (21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 (21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 (21 6) routing bnr_op_7 <X> lc_trk_g1_7 (21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7 (21 6) routing sp4_h_l_10 <X> lc_trk_g1_7 (21 6) routing sp4_h_l_2 <X> lc_trk_g1_7 (21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 (21 7) routing bnr_op_7 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7 +(21 7) routing sp12_h_r_23 <X> lc_trk_g1_7 (21 7) routing sp4_h_l_10 <X> lc_trk_g1_7 (21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 (21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 (21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing rgt_op_3 <X> lc_trk_g2_3 (21 8) routing sp12_v_t_0 <X> lc_trk_g2_3 (21 8) routing sp4_h_l_30 <X> lc_trk_g2_3 (21 8) routing sp4_h_r_35 <X> lc_trk_g2_3 @@ -1049,13 +1213,18 @@ (21 9) routing sp12_v_t_0 <X> lc_trk_g2_3 (21 9) routing sp12_v_t_16 <X> lc_trk_g2_3 (21 9) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 (21 9) routing sp4_v_t_22 <X> lc_trk_g2_3 (21 9) routing tnl_op_3 <X> lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 @@ -1063,6 +1232,8 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 @@ -1072,17 +1243,21 @@ (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 @@ -1135,11 +1310,14 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 @@ -1147,6 +1325,7 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 @@ -1158,6 +1337,9 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1168,7 +1350,9 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 @@ -1176,9 +1360,12 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 @@ -1190,16 +1377,22 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 @@ -1210,19 +1403,25 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1244,12 +1443,18 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_19 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 1) routing sp12_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2 (23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 @@ -1259,6 +1464,7 @@ (23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 (23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 (23 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (23 10) routing sp4_v_b_47 <X> lc_trk_g2_7 (23 10) routing sp4_v_t_18 <X> lc_trk_g2_7 @@ -1290,22 +1496,28 @@ (23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 (23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 (23 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (23 14) routing sp4_v_b_47 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_18 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (23 15) routing sp12_v_b_14 <X> lc_trk_g3_6 (23 15) routing sp12_v_t_21 <X> lc_trk_g3_6 (23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 (23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 (23 15) routing sp4_v_b_30 <X> lc_trk_g3_6 (23 15) routing sp4_v_b_38 <X> lc_trk_g3_6 (23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 +(23 2) routing sp12_h_r_23 <X> lc_trk_g0_7 (23 2) routing sp4_h_l_10 <X> lc_trk_g0_7 (23 2) routing sp4_h_l_2 <X> lc_trk_g0_7 (23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 (23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (23 2) routing sp4_v_t_10 <X> lc_trk_g0_7 (23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6 (23 3) routing sp12_h_l_21 <X> lc_trk_g0_6 (23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 (23 3) routing sp4_h_r_22 <X> lc_trk_g0_6 @@ -1313,6 +1525,8 @@ (23 3) routing sp4_v_b_14 <X> lc_trk_g0_6 (23 3) routing sp4_v_b_22 <X> lc_trk_g0_6 (23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3 (23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 (23 4) routing sp4_h_r_19 <X> lc_trk_g1_3 (23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 @@ -1320,25 +1534,33 @@ (23 4) routing sp4_v_b_19 <X> lc_trk_g1_3 (23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 (23 5) routing sp12_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp12_h_r_18 <X> lc_trk_g1_2 (23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 (23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 (23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 (23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 (23 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7 +(23 6) routing sp12_h_r_23 <X> lc_trk_g1_7 (23 6) routing sp4_h_l_10 <X> lc_trk_g1_7 (23 6) routing sp4_h_l_2 <X> lc_trk_g1_7 (23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 (23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (23 6) routing sp4_v_t_10 <X> lc_trk_g1_7 (23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6 +(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6 (23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 (23 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 (23 7) routing sp4_v_b_22 <X> lc_trk_g1_6 (23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 (23 8) routing sp12_v_b_11 <X> lc_trk_g2_3 (23 8) routing sp12_v_t_16 <X> lc_trk_g2_3 (23 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3 (23 8) routing sp4_h_r_35 <X> lc_trk_g2_3 (23 8) routing sp4_v_t_14 <X> lc_trk_g2_3 (23 8) routing sp4_v_t_22 <X> lc_trk_g2_3 @@ -1351,9 +1573,11 @@ (23 9) routing sp4_v_b_26 <X> lc_trk_g2_2 (23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 (23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 (24 0) routing sp12_h_l_0 <X> lc_trk_g0_3 (24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (24 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (24 0) routing sp4_v_b_19 <X> lc_trk_g0_3 (24 1) routing lft_op_2 <X> lc_trk_g0_2 (24 1) routing sp12_h_r_2 <X> lc_trk_g0_2 @@ -1361,10 +1585,14 @@ (24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 (24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 (24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(24 1) routing top_op_2 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 (24 10) routing sp12_v_b_7 <X> lc_trk_g2_7 (24 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (24 10) routing sp4_v_b_47 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 (24 10) routing tnr_op_7 <X> lc_trk_g2_7 (24 11) routing rgt_op_6 <X> lc_trk_g2_6 (24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 @@ -1393,25 +1621,32 @@ (24 14) routing rgt_op_7 <X> lc_trk_g3_7 (24 14) routing sp12_v_b_7 <X> lc_trk_g3_7 (24 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (24 14) routing sp4_v_b_47 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 (24 14) routing tnr_op_7 <X> lc_trk_g3_7 (24 15) routing rgt_op_6 <X> lc_trk_g3_6 (24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 (24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 (24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 (24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 (24 15) routing tnl_op_6 <X> lc_trk_g3_6 (24 15) routing tnr_op_6 <X> lc_trk_g3_6 (24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7 (24 2) routing sp4_h_l_10 <X> lc_trk_g0_7 (24 2) routing sp4_h_l_2 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 (24 2) routing sp4_v_t_10 <X> lc_trk_g0_7 (24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 (24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 (24 3) routing sp4_h_r_22 <X> lc_trk_g0_6 (24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 (24 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(24 3) routing top_op_6 <X> lc_trk_g0_6 (24 4) routing lft_op_3 <X> lc_trk_g1_3 (24 4) routing sp12_h_l_0 <X> lc_trk_g1_3 (24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 @@ -1422,8 +1657,11 @@ (24 5) routing sp12_h_r_2 <X> lc_trk_g1_2 (24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 (24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 (24 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(24 5) routing top_op_2 <X> lc_trk_g1_2 (24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7 (24 6) routing sp4_h_l_10 <X> lc_trk_g1_7 (24 6) routing sp4_h_l_2 <X> lc_trk_g1_7 (24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 @@ -1432,9 +1670,13 @@ (24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 (24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 (24 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (24 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(24 7) routing top_op_6 <X> lc_trk_g1_6 +(24 8) routing rgt_op_3 <X> lc_trk_g2_3 (24 8) routing sp12_v_t_0 <X> lc_trk_g2_3 (24 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3 (24 8) routing sp4_h_r_35 <X> lc_trk_g2_3 (24 8) routing sp4_v_t_30 <X> lc_trk_g2_3 (24 8) routing tnl_op_3 <X> lc_trk_g2_3 @@ -1445,6 +1687,7 @@ (24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 (24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 (24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 (24 9) routing tnr_op_2 <X> lc_trk_g2_2 (25 0) routing bnr_op_2 <X> lc_trk_g0_2 (25 0) routing lft_op_2 <X> lc_trk_g0_2 @@ -1454,11 +1697,13 @@ (25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 (25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 (25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2 (25 1) routing sp12_h_r_2 <X> lc_trk_g0_2 (25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 (25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 (25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 1) routing top_op_2 <X> lc_trk_g0_2 (25 10) routing bnl_op_6 <X> lc_trk_g2_6 (25 10) routing rgt_op_6 <X> lc_trk_g2_6 (25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 @@ -1499,22 +1744,26 @@ (25 15) routing bnl_op_6 <X> lc_trk_g3_6 (25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 (25 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 (25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 (25 15) routing sp4_v_b_38 <X> lc_trk_g3_6 (25 15) routing tnl_op_6 <X> lc_trk_g3_6 (25 2) routing bnr_op_6 <X> lc_trk_g0_6 (25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 (25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 (25 2) routing sp4_h_r_22 <X> lc_trk_g0_6 (25 2) routing sp4_v_b_14 <X> lc_trk_g0_6 (25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 (25 3) routing bnr_op_6 <X> lc_trk_g0_6 (25 3) routing sp12_h_l_21 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 (25 3) routing sp4_h_r_22 <X> lc_trk_g0_6 (25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 (25 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 3) routing top_op_6 <X> lc_trk_g0_6 (25 4) routing bnr_op_2 <X> lc_trk_g1_2 (25 4) routing lft_op_2 <X> lc_trk_g1_2 (25 4) routing sp12_h_r_2 <X> lc_trk_g1_2 @@ -1523,10 +1772,13 @@ (25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 (25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 (25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_18 <X> lc_trk_g1_2 (25 5) routing sp12_h_r_2 <X> lc_trk_g1_2 (25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 (25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 5) routing top_op_2 <X> lc_trk_g1_2 (25 6) routing bnr_op_6 <X> lc_trk_g1_6 (25 6) routing lft_op_6 <X> lc_trk_g1_6 (25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 @@ -1535,10 +1787,13 @@ (25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 (25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 (25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6 (25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 (25 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 (25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 7) routing top_op_6 <X> lc_trk_g1_6 (25 8) routing bnl_op_2 <X> lc_trk_g2_2 (25 8) routing rgt_op_2 <X> lc_trk_g2_2 (25 8) routing sp12_v_b_2 <X> lc_trk_g2_2 @@ -1553,6 +1808,8 @@ (25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 (25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> input0_0 (26 0) routing lc_trk_g0_6 <X> input0_0 (26 0) routing lc_trk_g1_5 <X> input0_0 (26 0) routing lc_trk_g1_7 <X> input0_0 @@ -1687,6 +1944,7 @@ (27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (27 1) routing lc_trk_g1_1 <X> input0_0 (27 1) routing lc_trk_g1_3 <X> input0_0 (27 1) routing lc_trk_g1_5 <X> input0_0 @@ -1698,6 +1956,7 @@ (27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 @@ -1743,7 +2002,9 @@ (27 15) routing lc_trk_g3_4 <X> input0_7 (27 15) routing lc_trk_g3_6 <X> input0_7 (27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 @@ -1774,6 +2035,7 @@ (27 5) routing lc_trk_g3_7 <X> input0_2 (27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 @@ -1788,6 +2050,7 @@ (27 7) routing lc_trk_g3_4 <X> input0_3 (27 7) routing lc_trk_g3_6 <X> input0_3 (27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_3 @@ -1809,6 +2072,7 @@ (28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (28 1) routing lc_trk_g2_0 <X> input0_0 (28 1) routing lc_trk_g2_2 <X> input0_0 (28 1) routing lc_trk_g2_4 <X> input0_0 @@ -1865,6 +2129,7 @@ (28 15) routing lc_trk_g3_2 <X> input0_7 (28 15) routing lc_trk_g3_4 <X> input0_7 (28 15) routing lc_trk_g3_6 <X> input0_7 +(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 @@ -1898,6 +2163,7 @@ (28 5) routing lc_trk_g3_7 <X> input0_2 (28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 @@ -1942,8 +2208,10 @@ (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 @@ -1958,11 +2226,13 @@ (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 @@ -2051,10 +2321,15 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 @@ -2112,12 +2387,15 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2142,7 +2420,9 @@ (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 @@ -2208,6 +2488,7 @@ (30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_7 @@ -2215,15 +2496,19 @@ (30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 @@ -2260,14 +2545,18 @@ (30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0 +(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 @@ -2288,8 +2577,11 @@ (30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5 +(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 @@ -2302,6 +2594,7 @@ (30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_3 @@ -2309,40 +2602,63 @@ (30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 +(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_7 +(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 +(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 (31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0 @@ -2350,12 +2666,17 @@ (31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 +(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 @@ -2363,23 +2684,37 @@ (31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 (31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4 @@ -2394,45 +2729,75 @@ (31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 @@ -2451,9 +2816,12 @@ (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 @@ -2478,8 +2846,14 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 @@ -2489,23 +2863,38 @@ (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 @@ -2516,12 +2905,17 @@ (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 +(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 +(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_2 +(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 @@ -2531,13 +2925,18 @@ (33 11) routing lc_trk_g2_3 <X> input2_5 (33 11) routing lc_trk_g2_5 <X> input2_5 (33 11) routing lc_trk_g2_7 <X> input2_5 +(33 11) routing lc_trk_g3_0 <X> input2_5 (33 11) routing lc_trk_g3_2 <X> input2_5 (33 11) routing lc_trk_g3_4 <X> input2_5 (33 11) routing lc_trk_g3_6 <X> input2_5 +(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 (33 13) routing lc_trk_g2_0 <X> input2_6 (33 13) routing lc_trk_g2_2 <X> input2_6 (33 13) routing lc_trk_g2_4 <X> input2_6 @@ -2546,6 +2945,7 @@ (33 13) routing lc_trk_g3_3 <X> input2_6 (33 13) routing lc_trk_g3_5 <X> input2_6 (33 13) routing lc_trk_g3_7 <X> input2_6 +(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 @@ -2561,6 +2961,8 @@ (33 15) routing lc_trk_g3_2 <X> input2_7 (33 15) routing lc_trk_g3_4 <X> input2_7 (33 15) routing lc_trk_g3_6 <X> input2_7 +(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_6 @@ -2568,14 +2970,20 @@ (33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 (33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3 @@ -2586,24 +2994,37 @@ (33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 (34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 +(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(34 11) routing lc_trk_g1_0 <X> input2_5 +(34 11) routing lc_trk_g1_2 <X> input2_5 +(34 11) routing lc_trk_g1_4 <X> input2_5 +(34 11) routing lc_trk_g1_6 <X> input2_5 +(34 11) routing lc_trk_g3_0 <X> input2_5 (34 11) routing lc_trk_g3_2 <X> input2_5 (34 11) routing lc_trk_g3_4 <X> input2_5 (34 11) routing lc_trk_g3_6 <X> input2_5 +(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 (34 13) routing lc_trk_g1_1 <X> input2_6 (34 13) routing lc_trk_g1_3 <X> input2_6 (34 13) routing lc_trk_g1_5 <X> input2_6 @@ -2613,6 +3034,7 @@ (34 13) routing lc_trk_g3_5 <X> input2_6 (34 13) routing lc_trk_g3_7 <X> input2_6 (34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_0 @@ -2627,22 +3049,32 @@ (34 15) routing lc_trk_g3_2 <X> input2_7 (34 15) routing lc_trk_g3_4 <X> input2_7 (34 15) routing lc_trk_g3_6 <X> input2_7 +(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 +(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_3 +(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_3 @@ -2651,11 +3083,16 @@ (34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 (35 10) routing lc_trk_g0_5 <X> input2_5 (35 10) routing lc_trk_g0_7 <X> input2_5 +(35 10) routing lc_trk_g1_4 <X> input2_5 +(35 10) routing lc_trk_g1_6 <X> input2_5 (35 10) routing lc_trk_g2_5 <X> input2_5 (35 10) routing lc_trk_g2_7 <X> input2_5 (35 10) routing lc_trk_g3_4 <X> input2_5 (35 10) routing lc_trk_g3_6 <X> input2_5 +(35 11) routing lc_trk_g0_3 <X> input2_5 (35 11) routing lc_trk_g0_7 <X> input2_5 +(35 11) routing lc_trk_g1_2 <X> input2_5 +(35 11) routing lc_trk_g1_6 <X> input2_5 (35 11) routing lc_trk_g2_3 <X> input2_5 (35 11) routing lc_trk_g2_7 <X> input2_5 (35 11) routing lc_trk_g3_2 <X> input2_5 @@ -2693,16 +3130,21 @@ (35 15) routing lc_trk_g3_2 <X> input2_7 (35 15) routing lc_trk_g3_6 <X> input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 +(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 +(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 +(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 +(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 +(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 @@ -2721,6 +3163,7 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 +(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 @@ -2814,6 +3257,7 @@ (4 9) routing sp4_h_l_47 <X> sp4_h_r_6 (4 9) routing sp4_v_b_0 <X> sp4_h_r_6 (4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 @@ -2821,6 +3265,7 @@ (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 +(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 @@ -2829,6 +3274,7 @@ (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 +(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 @@ -2986,6 +3432,7 @@ (7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 @@ -2994,6 +3441,7 @@ (7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 |