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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-31 15:59:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-31 15:59:14 +0200 |
| commit | 6948c4370dc3f10d05eedfc4408ecb0cbd5f373c (patch) | |
| tree | c9431ec1cb435318f0b3ded7d28ee8b18bd5e768 | |
| parent | 81e943e050dad652da795d21375bb700064116f4 (diff) | |
| parent | 1f9d00bb9cb2eeea0261d00324ff44e9b3f02136 (diff) | |
| download | icestorm-6948c4370dc3f10d05eedfc4408ecb0cbd5f373c.tar.gz icestorm-6948c4370dc3f10d05eedfc4408ecb0cbd5f373c.tar.bz2 icestorm-6948c4370dc3f10d05eedfc4408ecb0cbd5f373c.zip | |
Merge branch 'ice5k'
35 files changed, 9164 insertions, 354 deletions
diff --git a/icebox/.gitignore b/icebox/.gitignore index 14a9fb4..035ca9c 100644 --- a/icebox/.gitignore +++ b/icebox/.gitignore @@ -1,4 +1,5 @@ chipdb-1k.txt +chipdb-5k.txt chipdb-8k.txt chipdb-384.txt __pycache__ diff --git a/icebox/Makefile b/icebox/Makefile index afeb13c..430fb17 100644 --- a/icebox/Makefile +++ b/icebox/Makefile @@ -10,12 +10,16 @@ chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py > chipdb-1k.new mv chipdb-1k.new chipdb-1k.txt +chipdb-5k.txt: icebox.py iceboxdb.py icebox_chipdb.py + python3 icebox_chipdb.py -5 > chipdb-5k.new + mv chipdb-5k.new chipdb-5k.txt + chipdb-8k.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py -8 > chipdb-8k.new mv chipdb-8k.new chipdb-8k.txt clean: - rm -f chipdb-1k.txt chipdb-8k.txt chipdb-384.txt + rm -f chipdb-1k.txt chipdb-8k.txt chipdb-384.txt chipdb-5k.txt rm -f icebox.pyc iceboxdb.pyc install: all @@ -52,4 +56,3 @@ uninstall: -rmdir $(DESTDIR)$(PREFIX)/share/icebox .PHONY: all clean install uninstall - diff --git a/icebox/icebox.py b/icebox/icebox.py index 289f070..00f451d 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -76,6 +76,26 @@ class iceconfig: self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)] self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)] + def setup_empty_5k(self): + self.clear() + self.device = "5k" + self.max_x = 26 + self.max_y = 33 + + for x in range(1, self.max_x): + for y in range(1, self.max_y): + if x in (7, 20): + if y % 2 == 1: + self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)] + else: + self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)] + else: + self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)] + + for x in range(1, self.max_x): + self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)] + self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)] + def setup_empty_8k(self): self.clear() self.device = "8k" @@ -116,6 +136,7 @@ class iceconfig: def pinloc_db(self): if self.device == "384": return pinloc_db["384-qn32"] if self.device == "1k": return pinloc_db["1k-tq144"] + if self.device == "5k": return pinloc_db["5k-sg48"] if self.device == "8k": return pinloc_db["8k-ct256"] assert False @@ -137,6 +158,8 @@ class iceconfig: def pll_list(self): if self.device == "1k": return ["1k"] + if self.device == "5k": + return ["5k"] if self.device == "8k": return ["8k_0", "8k_1"] if self.device == "384": @@ -185,20 +208,28 @@ class iceconfig: assert False def tile_db(self, x, y): - if x == 0: return iotile_l_db + # Only these devices have IO on the left and right sides. + if self.device in ["384", "1k", "8k"]: + if x == 0: return iotile_l_db + if x == self.max_x: return iotile_r_db if y == 0: return iotile_b_db - if x == self.max_x: return iotile_r_db if y == self.max_y: return iotile_t_db if self.device == "1k": if (x, y) in self.logic_tiles: return logictile_db if (x, y) in self.ramb_tiles: return rambtile_db if (x, y) in self.ramt_tiles: return ramttile_db - if self.device == "8k": + elif self.device == "5k": + if (x, y) in self.logic_tiles: return logictile_5k_db + if (x, y) in self.ramb_tiles: return rambtile_5k_db + if (x, y) in self.ramt_tiles: return ramttile_5k_db + elif self.device == "8k": if (x, y) in self.logic_tiles: return logictile_8k_db if (x, y) in self.ramb_tiles: return rambtile_8k_db if (x, y) in self.ramt_tiles: return ramttile_8k_db - if self.device == "384": + elif self.device == "384": if (x, y) in self.logic_tiles: return logictile_384_db + + print("Tile type unknown at (%d, %d)" % (x, y)) assert False def tile_type(self, x, y): @@ -292,6 +323,8 @@ class iceconfig: if (nx, ny) in self.ramb_tiles: if self.device == "1k": return (nx, ny, "ram/RDATA_%d" % func) + elif self.device == "5k": + return (nx, ny, "ram/RDATA_%d" % (15-func)) elif self.device == "8k": return (nx, ny, "ram/RDATA_%d" % (15-func)) else: @@ -299,6 +332,8 @@ class iceconfig: if (nx, ny) in self.ramt_tiles: if self.device == "1k": return (nx, ny, "ram/RDATA_%d" % (8+func)) + elif self.device == "5k": + return (nx, ny, "ram/RDATA_%d" % (7-func)) elif self.device == "8k": return (nx, ny, "ram/RDATA_%d" % (7-func)) else: @@ -339,6 +374,8 @@ class iceconfig: if match: if self.device == "1k": funcnets |= self.follow_funcnet(x, y, int(match.group(1)) % 8) + elif self.device == "5k": + funcnets |= self.follow_funcnet(x, y, 7 - int(match.group(1)) % 8) elif self.device == "8k": funcnets |= self.follow_funcnet(x, y, 7 - int(match.group(1)) % 8) else: @@ -349,6 +386,9 @@ class iceconfig: def follow_net(self, netspec): x, y, netname = netspec neighbours = self.rlookup_funcnet(x, y, netname) + + #print(netspec) + #print('\t', neighbours) if netname == "carry_in" and y > 1: neighbours.add((x, y-1, "lutff_7/cout")) @@ -365,6 +405,7 @@ class iceconfig: match = re.match(r"sp4_r_v_b_(\d+)", netname) if match and 0 < x < self.max_x-1: neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1)))) + #print('\tafter r_v_b', neighbours) match = re.match(r"sp4_v_[bt]_(\d+)", netname) if match and 1 < x < self.max_x: @@ -372,6 +413,7 @@ class iceconfig: if n is not None: n = n.replace("sp4_", "sp4_r_") neighbours.add((x-1, y, n)) + #print('\tafter v_[bt]', neighbours) match = re.match(r"(logic|neigh)_op_(...)_(\d+)", netname) if match: @@ -421,6 +463,8 @@ class iceconfig: if self.tile_has_net(s[0], s[1], s[2]): neighbours.add((s[0], s[1], s[2])) + + #print('\tafter directions', neighbours) return neighbours def group_segments(self, all_from_tiles=set(), extra_connections=list(), extra_segments=list(), connect_gb=True): @@ -431,14 +475,14 @@ class iceconfig: for seg in extra_segments: seed_segments.add(seg) - + for conn in extra_connections: s1, s2 = conn connected_segments.setdefault(s1, set()).add(s2) connected_segments.setdefault(s2, set()).add(s1) seed_segments.add(s1) seed_segments.add(s2) - + for idx, tile in self.io_tiles.items(): tc = tileconfig(tile) pintypes = [ list("000000"), list("000000") ] @@ -474,6 +518,8 @@ class iceconfig: seed_segments.add((idx[0], idx[1], "lutff_7/cout")) if self.device == "1k": add_seed_segments(idx, tile, logictile_db) + elif self.device == "5k": + add_seed_segments(idx, tile, logictile_5k_db) elif self.device == "8k": add_seed_segments(idx, tile, logictile_8k_db) elif self.device == "384": @@ -484,6 +530,8 @@ class iceconfig: for idx, tile in self.ramb_tiles.items(): if self.device == "1k": add_seed_segments(idx, tile, rambtile_db) + elif self.device == "5k": + add_seed_segments(idx, tile, rambtile_5k_db) elif self.device == "8k": add_seed_segments(idx, tile, rambtile_8k_db) else: @@ -492,6 +540,8 @@ class iceconfig: for idx, tile in self.ramt_tiles.items(): if self.device == "1k": add_seed_segments(idx, tile, ramttile_db) + elif self.device == "5k": + add_seed_segments(idx, tile, ramttile_5k_db) elif self.device == "8k": add_seed_segments(idx, tile, ramttile_8k_db) else: @@ -536,10 +586,14 @@ class iceconfig: segments = set() queue.add(seed_segments.pop()) while queue: - for s in self.expand_net(queue.pop()): + next_segment = queue.pop() + expanded = self.expand_net(next_segment) + for s in expanded: if s not in segments: segments.add(s) - assert s not in seen_segments + if s in seen_segments: + print("//", s, "has already been seen. Check your bitmapping.") + assert False seen_segments.add(s) seed_segments.discard(s) if s in connected_segments: @@ -611,7 +665,7 @@ class iceconfig: self.extra_bits.add((int(line[1]), int(line[2]), int(line[3]))) continue if line[0] == ".device": - assert line[1] in ["1k", "8k", "384"] + assert line[1] in ["1k", "5k", "8k", "384"] self.device = line[1] continue if line[0] == ".sym": @@ -983,7 +1037,8 @@ def key_netname(netname): def run_checks_neigh(): print("Running consistency checks on neighbour finder..") ic = iceconfig() - ic.setup_empty_1k() + # ic.setup_empty_1k() + ic.setup_empty_5k() # ic.setup_empty_8k() # ic.setup_empty_384() @@ -999,15 +1054,19 @@ def run_checks_neigh(): for x in range(ic.max_x+1): for y in range(ic.max_x+1): + # Skip the corners. if x in (0, ic.max_x) and y in (0, ic.max_y): continue + # Skip the sides of a 5k device. + if ic.device == "5k" and x in (0, ic.max_x): + continue add_segments((x, y), ic.tile_db(x, y)) if (x, y) in ic.logic_tiles: all_segments.add((x, y, "lutff_7/cout")) for s1 in all_segments: - # if s1[1] > 4: continue for s2 in ic.follow_net(s1): + # if s1[1] > 4: continue if s1 not in ic.follow_net(s2): print("ERROR: %s -> %s, but not vice versa!" % (s1, s2)) print("Neighbours of %s:" % (s1,)) @@ -1021,24 +1080,27 @@ def run_checks_neigh(): def run_checks(): run_checks_neigh() -def parse_db(text, grep_8k=False, grep_384=False): +def parse_db(text, device="1k"): db = list() for line in text.split("\n"): line_384 = line.replace("384_glb_netwk_", "glb_netwk_") line_1k = line.replace("1k_glb_netwk_", "glb_netwk_") + line_5k = line.replace("5k_glb_netwk_", "glb_netwk_") line_8k = line.replace("8k_glb_netwk_", "glb_netwk_") if line_1k != line: - if grep_8k: - continue - if grep_384: + if device != "1k": continue line = line_1k elif line_8k != line: - if not grep_8k: + if device != "8k": continue line = line_8k + elif line_5k != line: + if device != "5k": + continue + line = line_5k elif line_384 != line: - if not grep_384: + if device != "384": continue line = line_384 line = line.split("\t") @@ -1053,12 +1115,22 @@ extra_bits_db = { (0, 330, 142): ("padin_glb_netwk", "0"), (0, 331, 142): ("padin_glb_netwk", "1"), (1, 330, 143): ("padin_glb_netwk", "2"), - (1, 331, 143): ("padin_glb_netwk", "3"), + (1, 331, 143): ("padin_glb_netwk", "3"), # (1 3) (331 144) (331 144) routing T_0_0.padin_3 <X> T_0_0.glb_netwk_3 (1, 330, 142): ("padin_glb_netwk", "4"), (1, 331, 142): ("padin_glb_netwk", "5"), - (0, 330, 143): ("padin_glb_netwk", "6"), + (0, 330, 143): ("padin_glb_netwk", "6"), # (0 0) (330 143) (330 143) routing T_0_0.padin_6 <X> T_0_0.glb_netwk_6 (0, 331, 143): ("padin_glb_netwk", "7"), }, + "5k": { + (0, 690, 334): ("padin_glb_netwk", "0"), # (0 1) (690 334) (690 334) routing T_0_0.padin_0 <X> T_0_0.glb_netwk_0 + (1, 691, 334): ("padin_glb_netwk", "1"), # (1 1) (691 334) (691 334) routing T_0_0.padin_1 <X> T_0_0.glb_netwk_1 + (0, 690, 336): ("padin_glb_netwk", "2"), # (0 3) (690 336) (690 336) routing T_0_0.padin_2 <X> T_0_0.glb_netwk_2 + (1, 871, 271): ("padin_glb_netwk", "3"), + (1, 870, 270): ("padin_glb_netwk", "4"), + (1, 871, 270): ("padin_glb_netwk", "5"), + (0, 870, 271): ("padin_glb_netwk", "6"), + (1, 691, 335): ("padin_glb_netwk", "7"), # (1 0) (691 335) (691 335) routing T_0_0.padin_7 <X> T_0_0.glb_netwk_7 + }, "8k": { (0, 870, 270): ("padin_glb_netwk", "0"), (0, 871, 270): ("padin_glb_netwk", "1"), @@ -1092,6 +1164,16 @@ gbufin_db = { ( 6, 0, 5), ( 6, 17, 4), ], + "5k": [ # not sure how to get the third column, currently based on diagram in pdf. + ( 6, 0, 0), + (12, 0, 1), + (13, 0, 3), + (19, 0, 6), + ( 6, 31, 5), + (12, 31, 2), + (13, 31, 7), + (19, 31, 4), + ], "8k": [ (33, 16, 7), ( 0, 16, 6), @@ -1114,6 +1196,14 @@ gbufin_db = { ] } +# To figure these out: +# 1. Copy io_latched.sh and convert it for your pinout (like io_latched_5k.sh). +# 2. Run it. It will create an io_latched_<device>.work directory with a bunch of files. +# 3. Grep the *.ve files in that directory for "'fabout')". The coordinates +# before it are where the io latches are. +# +# Note: This may not work if your icepack configuration of cell sizes is incorrect because +# icebox_vlog.py won't correctly interpret the meaning of particular bits. iolatch_db = { "1k": [ ( 0, 7), @@ -1121,6 +1211,10 @@ iolatch_db = { ( 5, 0), ( 8, 17), ], + "5k": [ + (14, 0), + (14, 31), + ], "8k": [ ( 0, 15), (33, 18), @@ -1135,12 +1229,20 @@ iolatch_db = { ], } +# The x, y cell locations of the WARMBOOT controls. Run tests/sb_warmboot.v +# through icecube.sh to determine these values. warmbootinfo_db = { "1k": { "BOOT": ( 12, 0, "fabout" ), "S0": ( 13, 1, "fabout" ), "S1": ( 13, 2, "fabout" ), }, + "5k": { + # These are the right locations but may be the wrong order. + "BOOT": ( 22, 0, "fabout" ), + "S0": ( 23, 0, "fabout" ), + "S1": ( 24, 0, "fabout" ), + }, "8k": { "BOOT": ( 31, 0, "fabout" ), "S0": ( 33, 1, "fabout" ), @@ -1164,6 +1266,7 @@ noplls_db = { "1k-cb121": [ "1k" ], "1k-vq100": [ "1k" ], "384-qn32": [ "384" ], + "5k-sg48": [ "5k" ], } pllinfo_db = { @@ -1260,6 +1363,99 @@ pllinfo_db = { "SDI": ( 4, 0, "fabout"), "SCLK": ( 3, 0, "fabout"), }, + "5k": { + "LOC" : (12, 31), + + # 3'b000 = "DISABLED" + # 3'b010 = "SB_PLL40_PAD" + # 3'b100 = "SB_PLL40_2_PAD" + # 3'b110 = "SB_PLL40_2F_PAD" + # 3'b011 = "SB_PLL40_CORE" + # 3'b111 = "SB_PLL40_2F_CORE" + "PLLTYPE_0": ( 16, 0, "PLLCONFIG_5"), + "PLLTYPE_1": ( 18, 0, "PLLCONFIG_1"), + "PLLTYPE_2": ( 18, 0, "PLLCONFIG_3"), + + # 3'b000 = "DELAY" + # 3'b001 = "SIMPLE" + # 3'b010 = "PHASE_AND_DELAY" + # 3'b110 = "EXTERNAL" + "FEEDBACK_PATH_0": ( 18, 0, "PLLCONFIG_5"), + "FEEDBACK_PATH_1": ( 15, 0, "PLLCONFIG_9"), + "FEEDBACK_PATH_2": ( 16, 0, "PLLCONFIG_1"), + + # 1'b0 = "FIXED" + # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111) + "DELAY_ADJMODE_FB": ( 17, 0, "PLLCONFIG_4"), + + # 1'b0 = "FIXED" + # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111) + "DELAY_ADJMODE_REL": ( 17, 0, "PLLCONFIG_9"), + + # 2'b00 = "GENCLK" + # 2'b01 = "GENCLK_HALF" + # 2'b10 = "SHIFTREG_90deg" + # 2'b11 = "SHIFTREG_0deg" + "PLLOUT_SELECT_A_0": ( 16, 0, "PLLCONFIG_6"), + "PLLOUT_SELECT_A_1": ( 16, 0, "PLLCONFIG_7"), + + # 2'b00 = "GENCLK" + # 2'b01 = "GENCLK_HALF" + # 2'b10 = "SHIFTREG_90deg" + # 2'b11 = "SHIFTREG_0deg" + "PLLOUT_SELECT_B_0": ( 16, 0, "PLLCONFIG_2"), + "PLLOUT_SELECT_B_1": ( 16, 0, "PLLCONFIG_3"), + + # Numeric Parameters + "SHIFTREG_DIV_MODE": ( 16, 0, "PLLCONFIG_4"), + "FDA_FEEDBACK_0": ( 16, 0, "PLLCONFIG_9"), + "FDA_FEEDBACK_1": ( 17, 0, "PLLCONFIG_1"), + "FDA_FEEDBACK_2": ( 17, 0, "PLLCONFIG_2"), + "FDA_FEEDBACK_3": ( 17, 0, "PLLCONFIG_3"), + "FDA_RELATIVE_0": ( 17, 0, "PLLCONFIG_5"), + "FDA_RELATIVE_1": ( 17, 0, "PLLCONFIG_6"), + "FDA_RELATIVE_2": ( 17, 0, "PLLCONFIG_7"), + "FDA_RELATIVE_3": ( 17, 0, "PLLCONFIG_8"), + "DIVR_0": ( 14, 0, "PLLCONFIG_1"), + "DIVR_1": ( 14, 0, "PLLCONFIG_2"), + "DIVR_2": ( 14, 0, "PLLCONFIG_3"), + "DIVR_3": ( 14, 0, "PLLCONFIG_4"), + "DIVF_0": ( 14, 0, "PLLCONFIG_5"), + "DIVF_1": ( 14, 0, "PLLCONFIG_6"), + "DIVF_2": ( 14, 0, "PLLCONFIG_7"), + "DIVF_3": ( 14, 0, "PLLCONFIG_8"), + "DIVF_4": ( 14, 0, "PLLCONFIG_9"), + "DIVF_5": ( 15, 0, "PLLCONFIG_1"), + "DIVF_6": ( 15, 0, "PLLCONFIG_2"), + "DIVQ_0": ( 15, 0, "PLLCONFIG_3"), + "DIVQ_1": ( 15, 0, "PLLCONFIG_4"), + "DIVQ_2": ( 15, 0, "PLLCONFIG_5"), + "FILTER_RANGE_0": ( 15, 0, "PLLCONFIG_6"), + "FILTER_RANGE_1": ( 15, 0, "PLLCONFIG_7"), + "FILTER_RANGE_2": ( 15, 0, "PLLCONFIG_8"), + "TEST_MODE": ( 16, 0, "PLLCONFIG_8"), + + # PLL Ports + "PLLOUT_A": ( 16, 0, 1), + "PLLOUT_B": ( 17, 0, 0), + "REFERENCECLK": ( 13, 0, "fabout"), + "EXTFEEDBACK": ( 14, 0, "fabout"), + "DYNAMICDELAY_0": ( 5, 0, "fabout"), + "DYNAMICDELAY_1": ( 6, 0, "fabout"), + "DYNAMICDELAY_2": ( 7, 0, "fabout"), + "DYNAMICDELAY_3": ( 8, 0, "fabout"), + "DYNAMICDELAY_4": ( 9, 0, "fabout"), + "DYNAMICDELAY_5": ( 10, 0, "fabout"), + "DYNAMICDELAY_6": ( 11, 0, "fabout"), + "DYNAMICDELAY_7": ( 12, 0, "fabout"), + "LOCK": ( 1, 1, "neigh_op_bnl_1"), + "BYPASS": ( 19, 0, "fabout"), + "RESETB": ( 20, 0, "fabout"), + "LATCHINPUTVALUE": ( 15, 0, "fabout"), + "SDO": ( 32, 1, "neigh_op_bnr_3"), + "SDI": ( 22, 0, "fabout"), + "SCLK": ( 21, 0, "fabout"), + }, "8k_0": { "LOC" : (16, 0), @@ -1459,6 +1655,13 @@ padin_pio_db = { ( 6, 0, 1), # glb_netwk_6 ( 6, 17, 1), # glb_netwk_7 ], + "5k": [ + ( 6, 0, 1), + (19, 0, 1), + ( 6, 31, 0), + (12, 31, 1), + (13, 31, 0), + ], "8k": [ (33, 16, 1), ( 0, 16, 1), @@ -1847,6 +2050,9 @@ ieren_db = { ], } +# This dictionary maps package variants to a table of pin names and their +# corresponding grid location (x, y, block). This is most easily found through +# the package view in iCEcube2 by hovering the mouse over each pin. pinloc_db = { "1k-swg16tr": [ ( "A2", 6, 17, 1), @@ -3850,17 +4056,61 @@ pinloc_db = { ( "G3", 3, 0, 0), ( "G4", 4, 0, 1), ( "G6", 5, 0, 1), - ] + ], + "5k-sg48": [ + ( "2", 8, 0, 0), + ( "3", 9, 0, 1), + ( "4", 9, 0, 0), + ( "6", 13, 0, 1), + ( "9", 15, 0, 0), + ( "10", 16, 0, 0), + ( "11", 17, 0, 0), + ( "12", 18, 0, 0), + ( "13", 19, 0, 0), + ( "14", 23, 0, 0), + ( "15", 24, 0, 0), + ( "16", 24, 0, 1), + ( "17", 23, 0, 1), + ( "18", 22, 0, 1), + ( "19", 21, 0, 1), + ( "20", 19, 0, 1), + ( "21", 18, 0, 1), + ( "23", 19, 31, 0), + ( "25", 19, 31, 1), + ( "26", 18, 31, 0), + ( "27", 18, 31, 1), + ( "28", 17, 31, 0), + ( "31", 16, 31, 1), + ( "32", 16, 31, 0), + ( "34", 13, 31, 1), + ( "35", 12, 31, 1), + ( "36", 9, 31, 1), + ( "37", 13, 31, 0), + ( "38", 8, 31, 1), + ( "39", 4, 31, 0), + ( "40", 5, 31, 0), + ( "41", 6, 31, 0), + ( "42", 8, 31, 0), + ( "43", 9, 31, 0), + ( "44", 6, 0, 1), + ( "45", 7, 0, 1), + ( "46", 5, 0, 0), + ( "47", 6, 0, 0), + ( "48", 7, 0, 0), + ], } iotile_full_db = parse_db(iceboxdb.database_io_txt) -logictile_db = parse_db(iceboxdb.database_logic_txt) -logictile_8k_db = parse_db(iceboxdb.database_logic_txt, True) -logictile_384_db = parse_db(iceboxdb.database_logic_txt, False, True) -rambtile_db = parse_db(iceboxdb.database_ramb_txt) -ramttile_db = parse_db(iceboxdb.database_ramt_txt) -rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, True) -ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, True) +logictile_db = parse_db(iceboxdb.database_logic_txt, "1k") +logictile_5k_db = parse_db(iceboxdb.database_logic_txt, "5k") +logictile_8k_db = parse_db(iceboxdb.database_logic_txt, "8k") +logictile_384_db = parse_db(iceboxdb.database_logic_txt, "384") +rambtile_db = parse_db(iceboxdb.database_ramb_txt, "1k") +ramttile_db = parse_db(iceboxdb.database_ramt_txt, "1k") +rambtile_5k_db = parse_db(iceboxdb.database_ramb_5k_txt, "5k") +ramttile_5k_db = parse_db(iceboxdb.database_ramt_5k_txt, "5k") +rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, "8k") +ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, "8k") iotile_l_db = list() iotile_r_db = list() @@ -3899,11 +4149,19 @@ logictile_8k_db.append([["B1[50]"], "CarryInSet"]) logictile_384_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"]) logictile_384_db.append([["B1[50]"], "CarryInSet"]) -for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_8k_db, ramttile_8k_db]: +for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db]: for entry in db: if entry[1] in ("buffer", "routing"): - entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db), ramb_8k=(db == rambtile_8k_db), ramt_8k=(db == ramttile_8k_db)) - entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db), ramb_8k=(db == rambtile_8k_db), ramt_8k=(db == ramttile_8k_db)) + entry[2] = netname_normalize(entry[2], + ramb=(db == rambtile_db), + ramt=(db == ramttile_db), + ramb_8k=(db in (rambtile_8k_db, rambtile_5k_db)), + ramt_8k=(db in (ramttile_8k_db, ramttile_5k_db))) + entry[3] = netname_normalize(entry[3], + ramb=(db == rambtile_db), + ramt=(db == ramttile_db), + ramb_8k=(db in (rambtile_8k_db, rambtile_5k_db)), + ramt_8k=(db in (ramttile_8k_db, ramttile_5k_db))) unique_entries = dict() while db: entry = db.pop() @@ -3914,4 +4172,3 @@ for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, log if __name__ == "__main__": run_checks() - diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py index 7988e6a..ca7f483 100755 --- a/icebox/icebox_chipdb.py +++ b/icebox/icebox_chipdb.py @@ -19,6 +19,7 @@ import icebox import getopt, sys, re mode_384 = False +mode_5k = False mode_8k = False def usage(): @@ -28,19 +29,24 @@ Usage: icebox_chipdb [options] [bitmap.asc] -3 create chipdb for 384 device + -5 + create chipdb for 5k device + -8 create chipdb for 8k device """) sys.exit(0) try: - opts, args = getopt.getopt(sys.argv[1:], "38") + opts, args = getopt.getopt(sys.argv[1:], "358") except: usage() for o, a in opts: if o == "-8": mode_8k = True + elif o == "-5": + mode_5k = True elif o == "-3": mode_384 = True else: @@ -49,6 +55,8 @@ for o, a in opts: ic = icebox.iceconfig() if mode_8k: ic.setup_empty_8k() +elif mode_5k: + ic.setup_empty_5k() elif mode_384: ic.setup_empty_384() else: @@ -142,7 +150,7 @@ print("""# # # declares a special-purpose cell that is not part of the FPGA fabric # -# +# # .extra_bits # FUNCTION BANK_NUM ADDR_X ADDR_Y # ... @@ -233,21 +241,21 @@ print() def print_tile_nonrouting_bits(tile_type, idx): tx = idx[0] ty = idx[1] - + tile = ic.tile(tx, ty) - + print(".%s_tile_bits %d %d" % (tile_type, len(tile[0]), len(tile))) - + function_bits = dict() for entry in ic.tile_db(tx, ty): if not ic.tile_has_entry(tx, ty, entry): continue if entry[1] in ("routing", "buffer"): continue - + func = ".".join(entry[1:]) function_bits[func] = entry[0] - + for x in sorted(function_bits): print(" ".join([x] + function_bits[x])) print() @@ -318,4 +326,3 @@ for idx in sorted(all_tiles): assert (idx[0], idx[1], entry[2]) in seg_to_net print("%s %d" % (pattern, seg_to_net[(idx[0], idx[1], entry[2])])) print() - diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py index 4033f01..d28336d 100755 --- a/icebox/icebox_vlog.py +++ b/icebox/icebox_vlog.py @@ -396,6 +396,7 @@ if lookup_symbols: current_net = -1 text_func.append("") +#print(nets) wb_boot = seg_to_net(icebox.warmbootinfo_db[ic.device]["BOOT"], "") wb_s0 = seg_to_net(icebox.warmbootinfo_db[ic.device]["S0"], "") wb_s1 = seg_to_net(icebox.warmbootinfo_db[ic.device]["S1"], "") @@ -728,7 +729,7 @@ for tile in ic.ramb_tiles: if len(wire_bits) > 1: return "{%s}" % ", ".join(wire_bits) return wire_bits[0] - if get_ram_config('PowerUp') == (ic.device == "8k"): + if get_ram_config('PowerUp') == (ic.device in ("8k", "5k")): if not strip_comments: text_func.append("// RAM TILE %d %d" % tile) text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else "")); diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index e9c5524..63f2079 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -5329,6 +5329,2343 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ +database_ramb_5k_txt = """ +B9[7] ColBufCtrl 8k_glb_netwk_0 +B8[7] ColBufCtrl 8k_glb_netwk_1 +B11[7] ColBufCtrl 8k_glb_netwk_2 +B10[7] ColBufCtrl 8k_glb_netwk_3 +B13[7] ColBufCtrl 8k_glb_netwk_4 +B12[7] ColBufCtrl 8k_glb_netwk_5 +B15[7] ColBufCtrl 8k_glb_netwk_6 +B14[7] ColBufCtrl 8k_glb_netwk_7 +B0[0] NegClk +B1[7] RamConfig PowerUp +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 +!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 +!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 +!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 +!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 +!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 +!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 +!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 +!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 +!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 +B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 +B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 +B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 +B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 +B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 +B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 +B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 +B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 +B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 +!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 +!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 +!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 +!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 +!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 +!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 +!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 +!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 +!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 +!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 +B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 +B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 +B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 +B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 +B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 +B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 +B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 +B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 +B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 +B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 +!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 +!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 +!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 +!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 +!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 +!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 +!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 +!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 +!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 +!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 +B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 +B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 +B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 +B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 +B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 +B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 +B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 +B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 +B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 +!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 +!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 +!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 +!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 +!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 +!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 +!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 +!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 +!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 +!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 +B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 +B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 +B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 +B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 +B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 +B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 +B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 +B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 +B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 +B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 +B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 +B12[19] buffer sp12_h_l_1 sp4_h_r_13 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 +B8[2] buffer sp12_h_l_15 sp4_h_l_9 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +B4[2] buffer sp12_h_r_12 sp4_h_r_18 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_l_6 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_b_12 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 +B7[19] buffer sp12_v_b_13 sp4_v_t_7 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_t_8 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 +B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_t_6 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 +B11[19] buffer sp12_v_t_18 sp4_v_t_11 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 +B10[19] buffer sp12_v_t_20 sp4_v_b_23 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 +B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 +B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 +B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 +B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 +B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 +B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 +B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 +B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 +B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 +B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 +B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 +B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 +B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 +B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 +B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 +B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 +B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 +B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 +B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 +B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 +B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 +B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 +B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 +B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 +B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 +B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 +B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 +B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 +B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 +B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 +B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 +B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 +B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 +B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 +B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 +B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 +B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 +B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 +B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 +B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 +B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 +B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 +B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 +B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 +B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 +B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 +B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 +B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 +B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 +B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 +B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 +B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 +B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 +B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 +B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 +B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 +B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 +B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 +B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 +B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 +B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 +B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 +B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 +B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 +B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 +B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 +B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 +B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 +B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 +B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 +B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 +B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 +B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 +B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11] routing sp4_v_t_39 sp4_h_r_2 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +B13[4] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +B8[9] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +B1[13] routing sp4_v_t_44 sp4_h_r_2 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_ramt_5k_txt = """ +B9[7] ColBufCtrl 8k_glb_netwk_0 +B8[7] ColBufCtrl 8k_glb_netwk_1 +B11[7] ColBufCtrl 8k_glb_netwk_2 +B10[7] ColBufCtrl 8k_glb_netwk_3 +B13[7] ColBufCtrl 8k_glb_netwk_4 +B12[7] ColBufCtrl 8k_glb_netwk_5 +B15[7] ColBufCtrl 8k_glb_netwk_6 +B14[7] ColBufCtrl 8k_glb_netwk_7 +B0[0] NegClk +B5[7] RamCascade CBIT_4 +B4[7] RamCascade CBIT_5 +B7[7] RamCascade CBIT_6 +B6[7] RamCascade CBIT_7 +B1[7] RamConfig CBIT_0 +B0[7] RamConfig CBIT_1 +B3[7] RamConfig CBIT_2 +B2[7] RamConfig CBIT_3 +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0] buffer glb_netwk_3 glb2local_1 +!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 +!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 +!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 +!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 +!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 +!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 +!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 +!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 +!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 +!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 +!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 +B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 +B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 +B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 +B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 +B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 +B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 +B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 +B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 +B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 +B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 +!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 +!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 +!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 +!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 +!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 +!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 +!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 +!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 +!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 +B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 +B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 +B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 +B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 +B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 +B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 +B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 +B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 +B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 +B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 +B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 +!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 +!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 +!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 +!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 +!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 +!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 +!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 +!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 +!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 +!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 +B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 +B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 +B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 +B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 +B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 +B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 +B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 +B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 +B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 +B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 +!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 +!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 +!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 +!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 +!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 +!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 +!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 +!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 +!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 +!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 +!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 +B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 +B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 +B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 +B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 +B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 +B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 +B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 +B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 +B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 +B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 +B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 +B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 +B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 +B3[1] buffer sp12_h_r_10 sp4_h_r_17 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 +B10[2] buffer sp12_h_r_18 sp4_h_l_8 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 +B9[19] buffer sp12_v_b_17 sp4_v_b_20 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 +B2[19] buffer sp12_v_b_7 sp4_v_t_2 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_t_7 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 +B8[19] buffer sp12_v_t_16 sp4_v_t_8 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 +B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 +B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 +B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 +B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 +B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 +B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 +B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 +B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 +B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 +B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 +B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 +B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 +B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 +B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 +B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 +B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 +B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 +B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 +B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 +B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 +B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 +B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 +B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 +B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 +B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 +B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 +B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 +B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 +B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 +B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 +B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 +B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 +B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 +B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 +B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 +B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 +B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 +B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 +B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 +B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 +B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 +B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 +B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 +B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 +B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 +B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 +B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 +B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 +B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 +B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 +B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 +B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 +B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 +B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 +B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 +B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 +B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 +B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 +B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 +B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 +B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 +B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 +B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 +B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 +B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 +B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 +B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 +B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 +B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 +B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 +B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 +B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 +B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 +B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 +B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 +B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 +B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 +B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 +B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 +B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 +B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 +B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 +B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 +B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 +B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +B1[6] routing sp4_h_l_37 sp4_h_r_0 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +B7[13] routing sp4_v_b_0 sp4_h_l_40 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B8[5],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +B3[4] routing sp4_v_b_7 sp4_h_l_37 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +B0[9] routing sp4_v_t_36 sp4_h_r_1 +B9[4] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5] routing sp4_v_t_37 sp4_h_r_0 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +B8[12] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" database_ramb_8k_txt = """ B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 diff --git a/icefuzz/Makefile b/icefuzz/Makefile index ca1c583..2e42889 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -2,8 +2,26 @@ include ../config.mk export LC_ALL=C export ICE_SBTIMER_LP=1 -#EIGTHK = _8k -THREEH = _384 +DEVICECLASS = 1k + +ifeq ($(DEVICECLASS), 384) + DEVICE := lp384-cm49 + THREEH = _384 +endif + +ifeq ($(DEVICECLASS), 1k) + DEVICE := hx1k-tq144 +endif + +ifeq ($(DEVICECLASS), 5k) + DEVICE := up5k-sg48 + RAM_SUFFIX := _5k +endif + +ifeq ($(DEVICECLASS), 8k) + DEVICE := hx8k-ct256 + RAM_SUFFIX = _8k +endif TESTS = TESTS += binop @@ -18,49 +36,52 @@ TESTS += gbio TESTS += gbio2 TESTS += prim TESTS += fflogic -ifneq ($(THREEH),_384) +ifneq ($(DEVICECLASS),384) TESTS += ram40 TESTS += mem TESTS += pll TESTS += aig endif -database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(EIGTHK).txt bitdata_ramt$(EIGTHK).txt -ifeq ($(EIGTHK),_8k) +database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt +ifneq ($(RAM_SUFFIX),) cp cached_ramb.txt bitdata_ramb.txt cp cached_ramt.txt bitdata_ramt.txt -else +endif +ifneq ($(RAM_SUFFIX),_8k) cp cached_ramb_8k.txt bitdata_ramb_8k.txt cp cached_ramt_8k.txt bitdata_ramt_8k.txt endif - python3 database.py +ifneq ($(RAM_SUFFIX),_5k) + cp cached_ramb_5k.txt bitdata_ramb_5k.txt + cp cached_ramt_5k.txt bitdata_ramt_5k.txt +endif + ICEDEVICE=$(DEVICECLASS) python3 database.py python3 export.py diff -U0 cached_io.txt bitdata_io.txt || cp -v bitdata_io.txt cached_io.txt diff -U0 cached_logic.txt bitdata_logic.txt || cp -v bitdata_logic.txt cached_logic.txt - diff -U0 cached_ramb.txt bitdata_ramb.txt || cp -v bitdata_ramb.txt cached_ramb.txt - diff -U0 cached_ramt.txt bitdata_ramt.txt || cp -v bitdata_ramt.txt cached_ramt.txt - diff -U0 cached_ramb_8k.txt bitdata_ramb_8k.txt || cp -v bitdata_ramb_8k.txt cached_ramb_8k.txt - diff -U0 cached_ramt_8k.txt bitdata_ramt_8k.txt || cp -v bitdata_ramt_8k.txt cached_ramt_8k.txt + diff -U0 cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt || cp -v bitdata_ramb$(RAM_SUFFIX).txt cached_ramb$(RAM_SUFFIX).txt + diff -U0 cached_ramt$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt || cp -v bitdata_ramt$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt timings: -ifeq ($(EIGTHK),_8k) +ifeq ($(DEVICECLASS),8k) cp tmedges.txt tmedges.tmp - set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_hx8k.txt work_*/*.sdf > timings_hx8k.new mv timings_hx8k.new timings_hx8k.txt python3 timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new mv timings_lp8k.new timings_lp8k.txt else - ifeq ($(THREEH),_384) + ifeq ($(DEVICECLASS),384) cp tmedges.txt tmedges.tmp - set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_lp384.txt work_*/*.slp > timings_lp384.new mv timings_lp384.new timings_lp384.txt else cp tmedges.txt tmedges.tmp - set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_hx1k.txt work_*/*.sdf > timings_hx1k.new mv timings_hx1k.new timings_hx1k.txt @@ -76,24 +97,24 @@ timings_html: python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html python3 timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html -data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt +data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new - gawk '{ print "ramb$(EIGTHK)", $$0; }' cached_ramb$(EIGTHK).txt >> data_cached.new - gawk '{ print "ramt$(EIGTHK)", $$0; }' cached_ramt$(EIGTHK).txt >> data_cached.new + gawk '{ print "ramb$(RAM_SUFFIX)", $$0; }' cached_ramb$(RAM_SUFFIX).txt >> data_cached.new + gawk '{ print "ramt$(RAM_SUFFIX)", $$0; }' cached_ramt$(RAM_SUFFIX).txt >> data_cached.new mv data_cached.new data_cached.txt -bitdata_io.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) +bitdata_io.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^io $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ -bitdata_logic.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) +bitdata_logic.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^logic $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ -bitdata_ramb$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) - grep ^ramb$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ +bitdata_ramb$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^ramb$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ -bitdata_ramt$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) - grep ^ramt$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ +bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^ramt$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) @@ -101,22 +122,10 @@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) $(MAKE) -C ../icepack define data_template -data_$(1).txt: make_$(1).py ../icepack/icepack -ifeq ($(EIGTHK),_8k) - ICE8KPINS=1 python3 make_$(1).py - +ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1) - python3 extract.py -8 work_$(1)/*.glb > $$@ -else - ifeq ($(THREEH),_384) - ICE384PINS=1 python3 make_$(1).py - +ICEDEV=lp384-cm49 $(MAKE) -C work_$(1) - python3 extract.py -3 work_$(1)/*.glb > $$@ - else - python3 make_$(1).py - +$(MAKE) -C work_$(1) - python3 extract.py work_$(1)/*.glb > $$@ - endif -endif +data_$(DEVICECLASS)_$(1).txt: make_$(1).py ../icepack/icepack + ICEDEVICE=$(DEVICECLASS) python3 make_$(1).py + +ICEDEV=$(DEVICE) $(MAKE) -C work_$(DEVICECLASS)_$(1) + ICEDEVICE=$(DEVICECLASS) python3 extract.py work_$(DEVICECLASS)_$(1)/*.glb > $$@ endef $(foreach test,$(TESTS),$(eval $(call data_template,$(test)))) @@ -124,21 +133,20 @@ $(foreach test,$(TESTS),$(eval $(call data_template,$(test)))) %.ok: %.bin bash check.sh $< -check: $(addsuffix .ok,$(basename $(wildcard work_binop/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_pin2pin/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_mesh/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_fanout/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_logic/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_cluster/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_iopack/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_pll/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_binop/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_pin2pin/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_mesh/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_fanout/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_logic/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_cluster/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_iopack/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_pll/*.bin))) clean: - rm -rf work_* + rm -rf work_$(DEVICECLASS)_* rm -rf data_*.txt rm -rf bitdata_*.txt rm -rf database_*.txt rm -rf timings_*.html .PHONY: database datafiles check clean - diff --git a/icefuzz/cached_io.txt b/icefuzz/cached_io.txt index 9d7355e..eb247af 100644 --- a/icefuzz/cached_io.txt +++ b/icefuzz/cached_io.txt @@ -340,6 +340,19 @@ (14 14) routing glb_netwk_5 <X> wire_io_cluster/io_1/outclk (14 14) routing glb_netwk_6 <X> wire_io_cluster/io_1/outclk (14 14) routing glb_netwk_7 <X> wire_io_cluster/io_1/outclk +(14 15) IO control bit: BIODOWN_extra_padeb_test_0 +(14 15) IO control bit: BIOUP_extra_padeb_test_0 +(14 15) IO control bit: GIODOWN0_extra_padeb_test_0 +(14 15) IO control bit: GIODOWN1_extra_padeb_test_0 +(14 15) IO control bit: GIOLEFT0_extra_padeb_test_0 +(14 15) IO control bit: GIOLEFT1_extra_padeb_test_0 +(14 15) IO control bit: GIORIGHT0_extra_padeb_test_0 +(14 15) IO control bit: GIORIGHT1_extra_padeb_test_0 +(14 15) IO control bit: GIOUP0_extra_padeb_test_0 +(14 15) IO control bit: GIOUP1_extra_padeb_test_0 +(14 15) IO control bit: HIPBIOUP_extra_padeb_test_0 +(14 15) IO control bit: IODOWN_extra_padeb_test_0 +(14 15) IO control bit: IOUP_extra_padeb_test_0 (14 2) routing span4_horz_l_13 <X> span4_vert_7 (14 2) routing span4_horz_r_1 <X> span4_vert_7 (14 2) routing span4_vert_b_1 <X> span4_horz_7 @@ -388,6 +401,28 @@ (15 11) routing glb_netwk_7 <X> wire_io_cluster/io_1/cen (15 11) routing lc_trk_g1_2 <X> wire_io_cluster/io_1/cen (15 11) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/cen +(15 12) IO control bit: BIODOWN_cf_bit_39 +(15 12) IO control bit: BIOUP_cf_bit_39 +(15 12) IO control bit: GIODOWN0_cf_bit_39 +(15 12) IO control bit: GIOLEFT1_cf_bit_39 +(15 12) IO control bit: GIORIGHT0_cf_bit_39 +(15 12) IO control bit: GIORIGHT1_cf_bit_39 +(15 12) IO control bit: GIOUP0_cf_bit_39 +(15 12) IO control bit: GIOUP1_cf_bit_39 +(15 12) IO control bit: IODOWN_cf_bit_39 +(15 14) IO control bit: BIODOWN_extra_padeb_test_1 +(15 14) IO control bit: BIOUP_extra_padeb_test_1 +(15 14) IO control bit: GIODOWN0_extra_padeb_test_1 +(15 14) IO control bit: GIODOWN1_extra_padeb_test_1 +(15 14) IO control bit: GIOLEFT0_extra_padeb_test_1 +(15 14) IO control bit: GIOLEFT1_extra_padeb_test_1 +(15 14) IO control bit: GIORIGHT0_extra_padeb_test_1 +(15 14) IO control bit: GIORIGHT1_extra_padeb_test_1 +(15 14) IO control bit: GIOUP0_extra_padeb_test_1 +(15 14) IO control bit: GIOUP1_extra_padeb_test_1 +(15 14) IO control bit: HIPBIOUP_extra_padeb_test_1 +(15 14) IO control bit: IODOWN_extra_padeb_test_1 +(15 14) IO control bit: IOUP_extra_padeb_test_1 (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_0 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_1 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_2 wire_io_cluster/io_1/outclk @@ -424,6 +459,13 @@ (15 5) routing lc_trk_g1_4 <X> wire_gbuf/in (15 5) routing lc_trk_g1_6 <X> fabout (15 5) routing lc_trk_g1_6 <X> wire_gbuf/in +(15 6) IO control bit: BIODOWN_cf_bit_35 +(15 6) IO control bit: BIOUP_cf_bit_35 +(15 6) IO control bit: GIOLEFT1_cf_bit_35 +(15 6) IO control bit: GIORIGHT0_cf_bit_35 +(15 6) IO control bit: GIORIGHT1_cf_bit_35 +(15 6) IO control bit: GIOUP0_cf_bit_35 +(15 6) IO control bit: IODOWN_cf_bit_35 (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_0 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_1 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_2 wire_io_cluster/io_1/inclk @@ -489,7 +531,12 @@ (2 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_1 +(2 0) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_1 +(2 0) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_1 +(2 0) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_1 +(2 0) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_1 (2 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_1 +(2 0) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_1 (2 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_1 (2 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_1 (2 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_1 @@ -506,7 +553,12 @@ (2 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_4 (2 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_4 (2 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_4 @@ -518,6 +570,10 @@ (2 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_7 (2 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_7 (2 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_7 +(2 4) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_7 +(2 4) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_7 +(2 4) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_7 +(2 4) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_7 (2 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_7 (2 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_7 (2 4) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_7 @@ -525,6 +581,7 @@ (2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_34 (2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_34 (2 6) IO control bit: BIODOWN_REN_0 +(2 6) IO control bit: BIODOWN_REN_1 (2 6) IO control bit: BIOLEFT_REN_0 (2 6) IO control bit: BIORIGHT_REN_0 (2 6) IO control bit: BIORIGHT_REN_1 @@ -563,12 +620,18 @@ (3 0) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_2 (3 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_2 (3 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_2 +(3 0) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_2 +(3 0) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_2 +(3 0) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_2 +(3 0) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_2 (3 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_2 +(3 0) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_2 (3 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_2 +(3 1) IO control bit: BIODOWN_REN_0 (3 1) IO control bit: BIODOWN_REN_1 (3 1) IO control bit: BIOLEFT_REN_1 (3 1) IO control bit: BIORIGHT_REN_0 @@ -611,7 +674,12 @@ (3 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_5 (3 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_5 (3 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_5 @@ -621,7 +689,12 @@ (3 3) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_3 (3 3) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_3 (3 3) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_3 @@ -630,6 +703,9 @@ (3 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_8 (3 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_8 (3 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_8 +(3 4) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_8 +(3 4) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_8 +(3 4) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_8 (3 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_8 (3 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_8 (3 4) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_8 @@ -637,10 +713,15 @@ (3 5) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_6 +(3 5) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_6 +(3 5) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_6 +(3 5) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_6 +(3 5) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_6 (3 5) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_6 +(3 6) IO control bit: BIODOWN_IE_0 (3 6) IO control bit: BIODOWN_IE_1 (3 6) IO control bit: BIOLEFT_IE_1 (3 6) IO control bit: BIORIGHT_IE_0 @@ -674,11 +755,16 @@ (3 7) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_9 (3 7) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_9 (3 7) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_9 +(3 7) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_9 +(3 7) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_9 +(3 7) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_9 +(3 7) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_9 (3 7) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_9 (3 7) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_9 (3 7) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_9 (3 7) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_9 (3 9) IO control bit: BIODOWN_IE_0 +(3 9) IO control bit: BIODOWN_IE_1 (3 9) IO control bit: BIOLEFT_IE_0 (3 9) IO control bit: BIORIGHT_IE_0 (3 9) IO control bit: BIORIGHT_IE_1 diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt new file mode 100644 index 0000000..ad427d9 --- /dev/null +++ b/icefuzz/cached_ramb_5k.txt @@ -0,0 +1,2911 @@ +(0 0) Negative Clock bit +(0 10) routing glb_netwk_6 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 14) routing glb_netwk_6 <X> wire_bram/ram/RE +(0 14) routing lc_trk_g2_4 <X> wire_bram/ram/RE +(0 14) routing lc_trk_g3_5 <X> wire_bram/ram/RE +(0 15) routing glb_netwk_6 <X> wire_bram/ram/RE +(0 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE +(0 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE +(0 2) routing glb_netwk_2 <X> wire_bram/ram/RCLK +(0 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK +(0 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK +(0 2) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK +(0 2) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK +(0 3) routing glb_netwk_5 <X> wire_bram/ram/RCLK +(0 3) routing glb_netwk_7 <X> wire_bram/ram/RCLK +(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK +(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK +(0 4) routing glb_netwk_5 <X> wire_bram/ram/RCLKE +(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE +(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE +(0 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE +(0 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 11) routing glb_netwk_6 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE +(1 15) routing lc_trk_g0_4 <X> wire_bram/ram/RE +(1 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE +(1 15) routing lc_trk_g2_4 <X> wire_bram/ram/RE +(1 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE +(1 2) routing glb_netwk_4 <X> wire_bram/ram/RCLK +(1 2) routing glb_netwk_5 <X> wire_bram/ram/RCLK +(1 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK +(1 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/RCLKE +(1 5) routing lc_trk_g0_2 <X> wire_bram/ram/RCLKE +(1 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE +(1 5) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE +(1 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(10 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(10 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(10 0) routing sp4_v_t_45 <X> sp4_h_r_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(10 14) routing sp4_h_r_7 <X> sp4_h_l_47 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_36 <X> sp4_h_r_4 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_v_b_2 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_h_r_8 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_h_r_11 <X> sp4_h_l_46 +(11 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(11 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 0) routing sp4_v_b_2 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_2 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_8 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_v_b_2 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_v_b_11 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_h_r_2 <X> sp4_h_l_40 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_46 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_v_b_2 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(13 10) routing sp4_h_r_8 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_v_b_3 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(13 5) routing sp4_v_t_37 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_h_r_2 <X> sp4_h_l_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp12_v_b_4 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_4 <X> lc_trk_g2_4 +(14 11) routing sp4_h_r_28 <X> lc_trk_g2_4 +(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing tnl_op_4 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 12) routing sp4_v_b_32 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_b_32 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_b_4 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_4 <X> lc_trk_g3_4 +(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing tnl_op_4 <X> lc_trk_g3_4 +(14 2) routing bnr_op_4 <X> lc_trk_g0_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 2) routing sp4_h_l_1 <X> lc_trk_g0_4 +(14 2) routing sp4_h_l_9 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_12 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 3) routing bnr_op_4 <X> lc_trk_g0_4 +(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_b_12 <X> lc_trk_g0_4 +(14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing lft_op_4 <X> lc_trk_g1_4 +(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 6) routing sp4_h_l_1 <X> lc_trk_g1_4 +(14 6) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_12 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_b_12 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_32 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 8) routing sp4_v_b_32 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_b_32 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(15 10) routing rgt_op_5 <X> lc_trk_g2_5 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp12_v_b_4 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_28 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(15 11) routing sp4_v_b_44 <X> lc_trk_g2_4 +(15 11) routing tnl_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(15 14) routing tnl_op_5 <X> lc_trk_g3_5 +(15 14) routing tnr_op_5 <X> lc_trk_g3_5 +(15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_b_4 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(15 15) routing sp4_v_b_44 <X> lc_trk_g3_4 +(15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 15) routing tnr_op_4 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_l_2 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(15 3) routing sp4_h_l_1 <X> lc_trk_g0_4 +(15 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(15 4) routing lft_op_1 <X> lc_trk_g1_1 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_l_2 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 7) routing lft_op_4 <X> lc_trk_g1_4 +(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(15 7) routing sp4_h_l_1 <X> lc_trk_g1_4 +(15 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 10) routing sp12_v_t_18 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_t_24 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(16 11) routing sp12_v_t_11 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_28 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_44 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_32 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_13 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_18 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_t_24 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(16 15) routing sp12_v_t_11 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_44 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_l_1 <X> lc_trk_g0_4 +(16 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_12 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_l_1 <X> lc_trk_g1_4 +(16 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_12 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_32 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing rgt_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(18 10) routing sp4_v_t_24 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_t_18 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_t_24 <X> lc_trk_g2_5 +(18 11) routing tnl_op_5 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1 +(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(18 14) routing sp4_v_t_24 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_t_18 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_29 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_t_24 <X> lc_trk_g3_5 +(18 15) routing tnl_op_5 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_l_2 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_l_2 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing lft_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing bnr_op_5 <X> lc_trk_g1_5 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_l_2 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_l_2 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 +(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_b_23 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/RCLK +(2 3) routing lc_trk_g0_0 <X> wire_bram/ram/RCLK +(2 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK +(2 3) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK +(2 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_r_18 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 +(21 0) routing sp12_h_r_3 <X> lc_trk_g0_3 +(21 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3 +(21 1) routing sp12_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 10) routing sp4_v_b_31 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_20 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 13) routing sp4_h_l_14 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing rgt_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 14) routing sp4_v_b_31 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_31 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 +(21 2) routing bnr_op_7 <X> lc_trk_g0_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_23 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_r_3 <X> lc_trk_g1_3 +(21 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 +(21 5) routing sp12_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_h_l_6 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 +(21 7) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_23 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing rgt_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 9) routing sp4_h_l_14 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_18 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_20 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_31 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6 +(23 11) routing sp12_v_b_22 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_19 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_27 <X> lc_trk_g2_6 +(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3 +(23 12) routing sp12_v_t_8 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_14 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(23 13) routing sp12_v_b_10 <X> lc_trk_g3_2 +(23 13) routing sp12_v_b_18 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(23 13) routing sp4_v_b_34 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_15 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_31 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6 +(23 15) routing sp12_v_b_22 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_19 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_27 <X> lc_trk_g3_6 +(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 +(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6 +(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_t_6 <X> lc_trk_g1_3 +(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_18 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6 +(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3 +(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_43 <X> lc_trk_g2_3 +(23 9) routing sp12_v_b_10 <X> lc_trk_g2_2 +(23 9) routing sp12_v_b_18 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(23 9) routing sp4_v_b_34 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_15 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 +(24 0) routing sp12_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(24 1) routing lft_op_2 <X> lc_trk_g0_2 +(24 1) routing sp12_h_l_1 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_18 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 +(24 11) routing rgt_op_6 <X> lc_trk_g2_6 +(24 11) routing sp12_v_t_5 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(24 11) routing tnl_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_14 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(24 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_t_1 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 14) routing rgt_op_7 <X> lc_trk_g3_7 +(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_t_5 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_19 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(24 15) routing tnl_op_6 <X> lc_trk_g3_6 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(24 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_t_6 <X> lc_trk_g1_3 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_l_1 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_18 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(24 8) routing rgt_op_3 <X> lc_trk_g2_3 +(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(24 8) routing sp4_v_b_43 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 8) routing tnr_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_t_1 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing bnr_op_2 <X> lc_trk_g0_2 +(25 0) routing lft_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_l_1 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_18 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_1 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_18 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing rgt_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_t_5 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_19 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_27 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_22 <X> lc_trk_g2_6 +(25 11) routing sp12_v_t_5 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_t_27 <X> lc_trk_g2_6 +(25 11) routing tnl_op_6 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_t_1 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 12) routing sp4_v_b_34 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_15 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_b_18 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_1 <X> lc_trk_g3_2 +(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_b_34 <X> lc_trk_g3_2 +(25 13) routing tnl_op_2 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_t_5 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 14) routing sp4_v_t_27 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_22 <X> lc_trk_g3_6 +(25 15) routing sp12_v_t_5 <X> lc_trk_g3_6 +(25 15) routing sp4_h_l_19 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_t_27 <X> lc_trk_g3_6 +(25 15) routing tnl_op_6 <X> lc_trk_g3_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_l_1 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_18 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_1 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_18 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_t_1 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 8) routing sp4_v_b_34 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_15 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_b_18 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_1 <X> lc_trk_g2_2 +(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_b_34 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> input0_0 +(26 0) routing lc_trk_g0_6 <X> input0_0 +(26 0) routing lc_trk_g1_5 <X> input0_0 +(26 0) routing lc_trk_g1_7 <X> input0_0 +(26 0) routing lc_trk_g2_4 <X> input0_0 +(26 0) routing lc_trk_g2_6 <X> input0_0 +(26 0) routing lc_trk_g3_5 <X> input0_0 +(26 0) routing lc_trk_g3_7 <X> input0_0 +(26 1) routing lc_trk_g0_2 <X> input0_0 +(26 1) routing lc_trk_g0_6 <X> input0_0 +(26 1) routing lc_trk_g1_3 <X> input0_0 +(26 1) routing lc_trk_g1_7 <X> input0_0 +(26 1) routing lc_trk_g2_2 <X> input0_0 +(26 1) routing lc_trk_g2_6 <X> input0_0 +(26 1) routing lc_trk_g3_3 <X> input0_0 +(26 1) routing lc_trk_g3_7 <X> input0_0 +(26 10) routing lc_trk_g0_5 <X> input0_5 +(26 10) routing lc_trk_g0_7 <X> input0_5 +(26 10) routing lc_trk_g1_4 <X> input0_5 +(26 10) routing lc_trk_g1_6 <X> input0_5 +(26 10) routing lc_trk_g2_5 <X> input0_5 +(26 10) routing lc_trk_g2_7 <X> input0_5 +(26 10) routing lc_trk_g3_4 <X> input0_5 +(26 10) routing lc_trk_g3_6 <X> input0_5 +(26 11) routing lc_trk_g0_3 <X> input0_5 +(26 11) routing lc_trk_g0_7 <X> input0_5 +(26 11) routing lc_trk_g1_2 <X> input0_5 +(26 11) routing lc_trk_g1_6 <X> input0_5 +(26 11) routing lc_trk_g2_3 <X> input0_5 +(26 11) routing lc_trk_g2_7 <X> input0_5 +(26 11) routing lc_trk_g3_2 <X> input0_5 +(26 11) routing lc_trk_g3_6 <X> input0_5 +(26 12) routing lc_trk_g0_4 <X> input0_6 +(26 12) routing lc_trk_g0_6 <X> input0_6 +(26 12) routing lc_trk_g1_5 <X> input0_6 +(26 12) routing lc_trk_g1_7 <X> input0_6 +(26 12) routing lc_trk_g2_4 <X> input0_6 +(26 12) routing lc_trk_g2_6 <X> input0_6 +(26 12) routing lc_trk_g3_5 <X> input0_6 +(26 12) routing lc_trk_g3_7 <X> input0_6 +(26 13) routing lc_trk_g0_2 <X> input0_6 +(26 13) routing lc_trk_g0_6 <X> input0_6 +(26 13) routing lc_trk_g1_3 <X> input0_6 +(26 13) routing lc_trk_g1_7 <X> input0_6 +(26 13) routing lc_trk_g2_2 <X> input0_6 +(26 13) routing lc_trk_g2_6 <X> input0_6 +(26 13) routing lc_trk_g3_3 <X> input0_6 +(26 13) routing lc_trk_g3_7 <X> input0_6 +(26 14) routing lc_trk_g0_7 <X> input0_7 +(26 14) routing lc_trk_g1_4 <X> input0_7 +(26 14) routing lc_trk_g1_6 <X> input0_7 +(26 14) routing lc_trk_g2_5 <X> input0_7 +(26 14) routing lc_trk_g2_7 <X> input0_7 +(26 14) routing lc_trk_g3_4 <X> input0_7 +(26 14) routing lc_trk_g3_6 <X> input0_7 +(26 15) routing lc_trk_g0_3 <X> input0_7 +(26 15) routing lc_trk_g0_7 <X> input0_7 +(26 15) routing lc_trk_g1_2 <X> input0_7 +(26 15) routing lc_trk_g1_6 <X> input0_7 +(26 15) routing lc_trk_g2_3 <X> input0_7 +(26 15) routing lc_trk_g2_7 <X> input0_7 +(26 15) routing lc_trk_g3_2 <X> input0_7 +(26 15) routing lc_trk_g3_6 <X> input0_7 +(26 2) routing lc_trk_g0_5 <X> input0_1 +(26 2) routing lc_trk_g0_7 <X> input0_1 +(26 2) routing lc_trk_g1_4 <X> input0_1 +(26 2) routing lc_trk_g1_6 <X> input0_1 +(26 2) routing lc_trk_g2_5 <X> input0_1 +(26 2) routing lc_trk_g2_7 <X> input0_1 +(26 2) routing lc_trk_g3_4 <X> input0_1 +(26 2) routing lc_trk_g3_6 <X> input0_1 +(26 3) routing lc_trk_g0_3 <X> input0_1 +(26 3) routing lc_trk_g0_7 <X> input0_1 +(26 3) routing lc_trk_g1_2 <X> input0_1 +(26 3) routing lc_trk_g1_6 <X> input0_1 +(26 3) routing lc_trk_g2_3 <X> input0_1 +(26 3) routing lc_trk_g2_7 <X> input0_1 +(26 3) routing lc_trk_g3_2 <X> input0_1 +(26 3) routing lc_trk_g3_6 <X> input0_1 +(26 4) routing lc_trk_g0_4 <X> input0_2 +(26 4) routing lc_trk_g0_6 <X> input0_2 +(26 4) routing lc_trk_g1_5 <X> input0_2 +(26 4) routing lc_trk_g1_7 <X> input0_2 +(26 4) routing lc_trk_g2_4 <X> input0_2 +(26 4) routing lc_trk_g2_6 <X> input0_2 +(26 4) routing lc_trk_g3_5 <X> input0_2 +(26 4) routing lc_trk_g3_7 <X> input0_2 +(26 5) routing lc_trk_g0_2 <X> input0_2 +(26 5) routing lc_trk_g0_6 <X> input0_2 +(26 5) routing lc_trk_g1_3 <X> input0_2 +(26 5) routing lc_trk_g1_7 <X> input0_2 +(26 5) routing lc_trk_g2_2 <X> input0_2 +(26 5) routing lc_trk_g2_6 <X> input0_2 +(26 5) routing lc_trk_g3_3 <X> input0_2 +(26 5) routing lc_trk_g3_7 <X> input0_2 +(26 6) routing lc_trk_g0_5 <X> input0_3 +(26 6) routing lc_trk_g0_7 <X> input0_3 +(26 6) routing lc_trk_g1_4 <X> input0_3 +(26 6) routing lc_trk_g1_6 <X> input0_3 +(26 6) routing lc_trk_g2_5 <X> input0_3 +(26 6) routing lc_trk_g2_7 <X> input0_3 +(26 6) routing lc_trk_g3_4 <X> input0_3 +(26 6) routing lc_trk_g3_6 <X> input0_3 +(26 7) routing lc_trk_g0_3 <X> input0_3 +(26 7) routing lc_trk_g0_7 <X> input0_3 +(26 7) routing lc_trk_g1_2 <X> input0_3 +(26 7) routing lc_trk_g1_6 <X> input0_3 +(26 7) routing lc_trk_g2_3 <X> input0_3 +(26 7) routing lc_trk_g2_7 <X> input0_3 +(26 7) routing lc_trk_g3_2 <X> input0_3 +(26 7) routing lc_trk_g3_6 <X> input0_3 +(26 8) routing lc_trk_g0_4 <X> input0_4 +(26 8) routing lc_trk_g0_6 <X> input0_4 +(26 8) routing lc_trk_g1_5 <X> input0_4 +(26 8) routing lc_trk_g1_7 <X> input0_4 +(26 8) routing lc_trk_g2_4 <X> input0_4 +(26 8) routing lc_trk_g2_6 <X> input0_4 +(26 8) routing lc_trk_g3_5 <X> input0_4 +(26 8) routing lc_trk_g3_7 <X> input0_4 +(26 9) routing lc_trk_g0_2 <X> input0_4 +(26 9) routing lc_trk_g0_6 <X> input0_4 +(26 9) routing lc_trk_g1_3 <X> input0_4 +(26 9) routing lc_trk_g1_7 <X> input0_4 +(26 9) routing lc_trk_g2_2 <X> input0_4 +(26 9) routing lc_trk_g2_6 <X> input0_4 +(26 9) routing lc_trk_g3_3 <X> input0_4 +(26 9) routing lc_trk_g3_7 <X> input0_4 +(27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 +(27 1) routing lc_trk_g1_1 <X> input0_0 +(27 1) routing lc_trk_g1_3 <X> input0_0 +(27 1) routing lc_trk_g1_5 <X> input0_0 +(27 1) routing lc_trk_g1_7 <X> input0_0 +(27 1) routing lc_trk_g3_1 <X> input0_0 +(27 1) routing lc_trk_g3_3 <X> input0_0 +(27 1) routing lc_trk_g3_5 <X> input0_0 +(27 1) routing lc_trk_g3_7 <X> input0_0 +(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 +(27 11) routing lc_trk_g1_0 <X> input0_5 +(27 11) routing lc_trk_g1_2 <X> input0_5 +(27 11) routing lc_trk_g1_4 <X> input0_5 +(27 11) routing lc_trk_g1_6 <X> input0_5 +(27 11) routing lc_trk_g3_0 <X> input0_5 +(27 11) routing lc_trk_g3_2 <X> input0_5 +(27 11) routing lc_trk_g3_4 <X> input0_5 +(27 11) routing lc_trk_g3_6 <X> input0_5 +(27 12) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_9 +(27 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9 +(27 13) routing lc_trk_g1_1 <X> input0_6 +(27 13) routing lc_trk_g1_3 <X> input0_6 +(27 13) routing lc_trk_g1_5 <X> input0_6 +(27 13) routing lc_trk_g1_7 <X> input0_6 +(27 13) routing lc_trk_g3_1 <X> input0_6 +(27 13) routing lc_trk_g3_3 <X> input0_6 +(27 13) routing lc_trk_g3_5 <X> input0_6 +(27 13) routing lc_trk_g3_7 <X> input0_6 +(27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8 +(27 15) routing lc_trk_g1_0 <X> input0_7 +(27 15) routing lc_trk_g1_2 <X> input0_7 +(27 15) routing lc_trk_g1_4 <X> input0_7 +(27 15) routing lc_trk_g1_6 <X> input0_7 +(27 15) routing lc_trk_g3_0 <X> input0_7 +(27 15) routing lc_trk_g3_2 <X> input0_7 +(27 15) routing lc_trk_g3_4 <X> input0_7 +(27 15) routing lc_trk_g3_6 <X> input0_7 +(27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14 +(27 3) routing lc_trk_g1_0 <X> input0_1 +(27 3) routing lc_trk_g1_2 <X> input0_1 +(27 3) routing lc_trk_g1_4 <X> input0_1 +(27 3) routing lc_trk_g1_6 <X> input0_1 +(27 3) routing lc_trk_g3_0 <X> input0_1 +(27 3) routing lc_trk_g3_2 <X> input0_1 +(27 3) routing lc_trk_g3_4 <X> input0_1 +(27 3) routing lc_trk_g3_6 <X> input0_1 +(27 4) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_13 +(27 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13 +(27 5) routing lc_trk_g1_1 <X> input0_2 +(27 5) routing lc_trk_g1_3 <X> input0_2 +(27 5) routing lc_trk_g1_5 <X> input0_2 +(27 5) routing lc_trk_g1_7 <X> input0_2 +(27 5) routing lc_trk_g3_1 <X> input0_2 +(27 5) routing lc_trk_g3_3 <X> input0_2 +(27 5) routing lc_trk_g3_5 <X> input0_2 +(27 5) routing lc_trk_g3_7 <X> input0_2 +(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_12 +(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 +(27 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 +(27 7) routing lc_trk_g1_0 <X> input0_3 +(27 7) routing lc_trk_g1_2 <X> input0_3 +(27 7) routing lc_trk_g1_4 <X> input0_3 +(27 7) routing lc_trk_g1_6 <X> input0_3 +(27 7) routing lc_trk_g3_0 <X> input0_3 +(27 7) routing lc_trk_g3_2 <X> input0_3 +(27 7) routing lc_trk_g3_4 <X> input0_3 +(27 7) routing lc_trk_g3_6 <X> input0_3 +(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 +(27 9) routing lc_trk_g1_1 <X> input0_4 +(27 9) routing lc_trk_g1_3 <X> input0_4 +(27 9) routing lc_trk_g1_5 <X> input0_4 +(27 9) routing lc_trk_g1_7 <X> input0_4 +(27 9) routing lc_trk_g3_1 <X> input0_4 +(27 9) routing lc_trk_g3_3 <X> input0_4 +(27 9) routing lc_trk_g3_5 <X> input0_4 +(27 9) routing lc_trk_g3_7 <X> input0_4 +(28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 +(28 1) routing lc_trk_g2_0 <X> input0_0 +(28 1) routing lc_trk_g2_2 <X> input0_0 +(28 1) routing lc_trk_g2_4 <X> input0_0 +(28 1) routing lc_trk_g2_6 <X> input0_0 +(28 1) routing lc_trk_g3_1 <X> input0_0 +(28 1) routing lc_trk_g3_3 <X> input0_0 +(28 1) routing lc_trk_g3_5 <X> input0_0 +(28 1) routing lc_trk_g3_7 <X> input0_0 +(28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 +(28 11) routing lc_trk_g2_1 <X> input0_5 +(28 11) routing lc_trk_g2_3 <X> input0_5 +(28 11) routing lc_trk_g2_5 <X> input0_5 +(28 11) routing lc_trk_g2_7 <X> input0_5 +(28 11) routing lc_trk_g3_0 <X> input0_5 +(28 11) routing lc_trk_g3_2 <X> input0_5 +(28 11) routing lc_trk_g3_4 <X> input0_5 +(28 11) routing lc_trk_g3_6 <X> input0_5 +(28 12) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_9 +(28 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9 +(28 13) routing lc_trk_g2_0 <X> input0_6 +(28 13) routing lc_trk_g2_2 <X> input0_6 +(28 13) routing lc_trk_g2_4 <X> input0_6 +(28 13) routing lc_trk_g2_6 <X> input0_6 +(28 13) routing lc_trk_g3_1 <X> input0_6 +(28 13) routing lc_trk_g3_3 <X> input0_6 +(28 13) routing lc_trk_g3_5 <X> input0_6 +(28 13) routing lc_trk_g3_7 <X> input0_6 +(28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8 +(28 15) routing lc_trk_g2_1 <X> input0_7 +(28 15) routing lc_trk_g2_3 <X> input0_7 +(28 15) routing lc_trk_g2_5 <X> input0_7 +(28 15) routing lc_trk_g2_7 <X> input0_7 +(28 15) routing lc_trk_g3_0 <X> input0_7 +(28 15) routing lc_trk_g3_2 <X> input0_7 +(28 15) routing lc_trk_g3_4 <X> input0_7 +(28 15) routing lc_trk_g3_6 <X> input0_7 +(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 +(28 3) routing lc_trk_g2_1 <X> input0_1 +(28 3) routing lc_trk_g2_3 <X> input0_1 +(28 3) routing lc_trk_g2_5 <X> input0_1 +(28 3) routing lc_trk_g2_7 <X> input0_1 +(28 3) routing lc_trk_g3_0 <X> input0_1 +(28 3) routing lc_trk_g3_2 <X> input0_1 +(28 3) routing lc_trk_g3_4 <X> input0_1 +(28 3) routing lc_trk_g3_6 <X> input0_1 +(28 4) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_13 +(28 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13 +(28 5) routing lc_trk_g2_0 <X> input0_2 +(28 5) routing lc_trk_g2_2 <X> input0_2 +(28 5) routing lc_trk_g2_4 <X> input0_2 +(28 5) routing lc_trk_g2_6 <X> input0_2 +(28 5) routing lc_trk_g3_1 <X> input0_2 +(28 5) routing lc_trk_g3_3 <X> input0_2 +(28 5) routing lc_trk_g3_5 <X> input0_2 +(28 5) routing lc_trk_g3_7 <X> input0_2 +(28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_12 +(28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12 +(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12 +(28 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 +(28 7) routing lc_trk_g2_1 <X> input0_3 +(28 7) routing lc_trk_g2_3 <X> input0_3 +(28 7) routing lc_trk_g2_5 <X> input0_3 +(28 7) routing lc_trk_g2_7 <X> input0_3 +(28 7) routing lc_trk_g3_0 <X> input0_3 +(28 7) routing lc_trk_g3_2 <X> input0_3 +(28 7) routing lc_trk_g3_4 <X> input0_3 +(28 7) routing lc_trk_g3_6 <X> input0_3 +(28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11 +(28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 +(28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 +(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 +(28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 +(28 9) routing lc_trk_g2_0 <X> input0_4 +(28 9) routing lc_trk_g2_2 <X> input0_4 +(28 9) routing lc_trk_g2_4 <X> input0_4 +(28 9) routing lc_trk_g2_6 <X> input0_4 +(28 9) routing lc_trk_g3_1 <X> input0_4 +(28 9) routing lc_trk_g3_3 <X> input0_4 +(28 9) routing lc_trk_g3_5 <X> input0_4 +(28 9) routing lc_trk_g3_7 <X> input0_4 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_9 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_9 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_13 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_13 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_12 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 +(30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 +(30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_9 +(30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_9 +(30 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_9 +(30 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_9 +(30 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_9 +(30 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_9 +(30 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_9 +(30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9 +(30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8 +(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 +(30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_13 +(30 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13 +(30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13 +(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 +(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11 +(30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 +(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 +(30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 +(31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 +(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 +(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 +(31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 +(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_14 +(31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14 +(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 +(31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 +(31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 +(31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 +(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 +(31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 +(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 +(33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 +(33 11) routing lc_trk_g2_1 <X> input2_5 +(33 11) routing lc_trk_g2_5 <X> input2_5 +(33 11) routing lc_trk_g3_0 <X> input2_5 +(33 11) routing lc_trk_g3_4 <X> input2_5 +(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 +(33 13) routing lc_trk_g2_0 <X> input2_6 +(33 13) routing lc_trk_g2_2 <X> input2_6 +(33 13) routing lc_trk_g2_4 <X> input2_6 +(33 13) routing lc_trk_g2_6 <X> input2_6 +(33 13) routing lc_trk_g3_1 <X> input2_6 +(33 13) routing lc_trk_g3_3 <X> input2_6 +(33 13) routing lc_trk_g3_5 <X> input2_6 +(33 13) routing lc_trk_g3_7 <X> input2_6 +(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 +(33 15) routing lc_trk_g2_1 <X> input2_7 +(33 15) routing lc_trk_g2_3 <X> input2_7 +(33 15) routing lc_trk_g2_5 <X> input2_7 +(33 15) routing lc_trk_g2_7 <X> input2_7 +(33 15) routing lc_trk_g3_0 <X> input2_7 +(33 15) routing lc_trk_g3_2 <X> input2_7 +(33 15) routing lc_trk_g3_4 <X> input2_7 +(33 15) routing lc_trk_g3_6 <X> input2_7 +(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_14 +(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_14 +(33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 +(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 +(33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 +(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 +(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 +(33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 +(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 +(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 +(34 11) routing lc_trk_g1_0 <X> input2_5 +(34 11) routing lc_trk_g1_6 <X> input2_5 +(34 11) routing lc_trk_g3_0 <X> input2_5 +(34 11) routing lc_trk_g3_4 <X> input2_5 +(34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 +(34 13) routing lc_trk_g1_1 <X> input2_6 +(34 13) routing lc_trk_g1_3 <X> input2_6 +(34 13) routing lc_trk_g1_5 <X> input2_6 +(34 13) routing lc_trk_g1_7 <X> input2_6 +(34 13) routing lc_trk_g3_1 <X> input2_6 +(34 13) routing lc_trk_g3_3 <X> input2_6 +(34 13) routing lc_trk_g3_5 <X> input2_6 +(34 13) routing lc_trk_g3_7 <X> input2_6 +(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 +(34 15) routing lc_trk_g1_0 <X> input2_7 +(34 15) routing lc_trk_g1_2 <X> input2_7 +(34 15) routing lc_trk_g1_4 <X> input2_7 +(34 15) routing lc_trk_g1_6 <X> input2_7 +(34 15) routing lc_trk_g3_0 <X> input2_7 +(34 15) routing lc_trk_g3_2 <X> input2_7 +(34 15) routing lc_trk_g3_4 <X> input2_7 +(34 15) routing lc_trk_g3_6 <X> input2_7 +(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 +(34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13 +(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 +(34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_13 +(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 +(34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 +(34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 +(34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 +(35 10) routing lc_trk_g1_6 <X> input2_5 +(35 10) routing lc_trk_g2_5 <X> input2_5 +(35 10) routing lc_trk_g3_4 <X> input2_5 +(35 11) routing lc_trk_g0_3 <X> input2_5 +(35 11) routing lc_trk_g1_6 <X> input2_5 +(35 12) routing lc_trk_g0_4 <X> input2_6 +(35 12) routing lc_trk_g0_6 <X> input2_6 +(35 12) routing lc_trk_g1_5 <X> input2_6 +(35 12) routing lc_trk_g1_7 <X> input2_6 +(35 12) routing lc_trk_g2_4 <X> input2_6 +(35 12) routing lc_trk_g2_6 <X> input2_6 +(35 12) routing lc_trk_g3_5 <X> input2_6 +(35 12) routing lc_trk_g3_7 <X> input2_6 +(35 13) routing lc_trk_g0_2 <X> input2_6 +(35 13) routing lc_trk_g0_6 <X> input2_6 +(35 13) routing lc_trk_g1_3 <X> input2_6 +(35 13) routing lc_trk_g1_7 <X> input2_6 +(35 13) routing lc_trk_g2_2 <X> input2_6 +(35 13) routing lc_trk_g2_6 <X> input2_6 +(35 13) routing lc_trk_g3_3 <X> input2_6 +(35 13) routing lc_trk_g3_7 <X> input2_6 +(35 14) routing lc_trk_g0_5 <X> input2_7 +(35 14) routing lc_trk_g0_7 <X> input2_7 +(35 14) routing lc_trk_g1_4 <X> input2_7 +(35 14) routing lc_trk_g1_6 <X> input2_7 +(35 14) routing lc_trk_g2_5 <X> input2_7 +(35 14) routing lc_trk_g2_7 <X> input2_7 +(35 14) routing lc_trk_g3_4 <X> input2_7 +(35 14) routing lc_trk_g3_6 <X> input2_7 +(35 15) routing lc_trk_g0_3 <X> input2_7 +(35 15) routing lc_trk_g0_7 <X> input2_7 +(35 15) routing lc_trk_g1_2 <X> input2_7 +(35 15) routing lc_trk_g1_6 <X> input2_7 +(35 15) routing lc_trk_g2_3 <X> input2_7 +(35 15) routing lc_trk_g2_7 <X> input2_7 +(35 15) routing lc_trk_g3_2 <X> input2_7 +(35 15) routing lc_trk_g3_6 <X> input2_7 +(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 +(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 +(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 +(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 +(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 +(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 +(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 +(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 +(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 +(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 +(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 +(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 +(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 +(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 +(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_10 sp4_h_l_15 +(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_9 sp12_h_l_3 +(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_9 sp4_h_r_28 +(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_8 sp12_h_l_5 +(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_8 sp4_h_l_19 +(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_14 sp12_h_l_9 +(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_14 sp4_h_r_18 +(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_13 sp12_h_r_12 +(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_13 sp4_h_l_9 +(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_12 sp12_h_r_14 +(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_11 sp12_h_r_0 +(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 +(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 +(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 +(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 +(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 +(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 +(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 +(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 +(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 +(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 +(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 +(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 +(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 +(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 +(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 +(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 +(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 +(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_10 sp4_v_b_10 +(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_9 sp4_v_b_44 +(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_9 sp4_v_b_12 +(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_8 sp4_v_b_46 +(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_8 sp4_v_b_14 +(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_14 sp12_v_t_1 +(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_14 sp4_v_t_7 +(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_13 sp12_v_b_4 +(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_13 sp4_v_b_20 +(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_12 sp12_v_t_5 +(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_12 sp4_v_t_11 +(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_11 sp4_v_b_40 +(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_11 sp4_v_b_8 +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 1) routing sp4_h_l_44 <X> sp4_h_r_0 +(4 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_h_r_6 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_3 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_0 <X> sp4_v_t_37 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(4 3) routing sp4_h_r_9 <X> sp4_h_l_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 5) routing sp4_v_t_47 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 +(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 +(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 +(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 +(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 +(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 +(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 +(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 +(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_21 +(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_13 sp12_v_b_20 +(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_12 sp12_v_b_22 +(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_11 sp12_v_t_7 +(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_33 +(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_11 +(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_45 +(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_13 +(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 +(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 +(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 +(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 +(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 +(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 +(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_7 +(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_41 +(5 0) routing sp4_h_l_44 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_0 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_6 <X> sp4_h_r_0 +(5 0) routing sp4_v_t_37 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_h_r_3 <X> sp4_h_l_43 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_6 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_h_r_9 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_44 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_h_r_9 <X> sp4_h_l_37 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_43 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_0 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 4) routing sp4_v_t_38 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_38 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_v_b_0 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 8) routing sp4_v_t_43 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_v_b_0 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_6 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_l_41 <X> sp4_v_t_44 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_44 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_h_r_3 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_38 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_h_r_1 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 1) Ram config bit: MEMB_Power_Up_Control +(7 10) Column buffer control bit: MEMB_colbuf_cntl_3 +(7 11) Column buffer control bit: MEMB_colbuf_cntl_2 +(7 12) Column buffer control bit: MEMB_colbuf_cntl_5 +(7 13) Column buffer control bit: MEMB_colbuf_cntl_4 +(7 14) Column buffer control bit: MEMB_colbuf_cntl_7 +(7 15) Column buffer control bit: MEMB_colbuf_cntl_6 +(7 8) Column buffer control bit: MEMB_colbuf_cntl_1 +(7 9) Column buffer control bit: MEMB_colbuf_cntl_0 +(8 0) routing sp4_h_l_36 <X> sp4_h_r_1 +(8 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_l_42 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_h_l_47 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_h_r_4 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_h_r_4 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(9 10) routing sp4_v_b_7 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_h_r_7 <X> sp4_h_l_47 +(9 14) routing sp4_v_b_10 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_h_l_36 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_v_t_42 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt new file mode 100644 index 0000000..488b30a --- /dev/null +++ b/icefuzz/cached_ramt_5k.txt @@ -0,0 +1,3007 @@ +(0 0) Negative Clock bit +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 14) routing glb_netwk_4 <X> wire_bram/ram/WE +(0 14) routing lc_trk_g2_4 <X> wire_bram/ram/WE +(0 14) routing lc_trk_g3_5 <X> wire_bram/ram/WE +(0 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE +(0 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE +(0 2) routing glb_netwk_2 <X> wire_bram/ram/WCLK +(0 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK +(0 2) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK +(0 2) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK +(0 3) routing glb_netwk_5 <X> wire_bram/ram/WCLK +(0 3) routing glb_netwk_7 <X> wire_bram/ram/WCLK +(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK +(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK +(0 4) routing glb_netwk_5 <X> wire_bram/ram/WCLKE +(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE +(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE +(0 5) routing glb_netwk_3 <X> wire_bram/ram/WCLKE +(0 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE +(0 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE +(1 15) routing lc_trk_g0_4 <X> wire_bram/ram/WE +(1 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE +(1 15) routing lc_trk_g2_4 <X> wire_bram/ram/WE +(1 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE +(1 2) routing glb_netwk_5 <X> wire_bram/ram/WCLK +(1 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 +(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/WCLKE +(1 5) routing lc_trk_g0_2 <X> wire_bram/ram/WCLKE +(1 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE +(1 5) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE +(1 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_h_r_8 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_11 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_h_r_1 <X> sp4_h_l_41 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(10 8) routing sp4_v_t_39 <X> sp4_h_r_7 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_h_l_38 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_46 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(12 0) routing sp4_v_b_8 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_h_r_5 <X> sp4_h_l_45 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_46 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_h_l_39 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_v_t_45 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_h_r_8 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_h_r_5 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_h_l_38 <X> sp4_h_r_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_h_l_39 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing bnr_op_0 <X> lc_trk_g0_0 +(14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_l_5 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing bnr_op_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_t_19 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing tnl_op_4 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_l_29 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing tnl_op_4 <X> lc_trk_g3_4 +(14 2) routing bnr_op_4 <X> lc_trk_g0_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 3) routing bnr_op_4 <X> lc_trk_g0_4 +(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 3) routing top_op_4 <X> lc_trk_g0_4 +(14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_l_5 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing lft_op_4 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_l_21 <X> lc_trk_g2_0 +(14 8) routing sp4_h_l_29 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(15 11) routing tnl_op_4 <X> lc_trk_g2_4 +(15 11) routing tnr_op_4 <X> lc_trk_g2_4 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_16 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(15 14) routing tnl_op_5 <X> lc_trk_g3_5 +(15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(15 3) routing top_op_4 <X> lc_trk_g0_4 +(15 4) routing lft_op_1 <X> lc_trk_g1_1 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 7) routing lft_op_4 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 8) routing tnr_op_1 <X> lc_trk_g2_1 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_21 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 9) routing tnr_op_0 <X> lc_trk_g2_0 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 +(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4 +(16 11) routing sp12_v_t_19 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_17 <X> lc_trk_g3_1 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_33 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_16 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 +(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(16 2) routing sp12_h_r_13 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(16 4) routing sp12_h_l_6 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_17 <X> lc_trk_g2_1 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_33 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_21 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp4_h_l_16 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 11) routing tnl_op_5 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_33 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_17 <X> lc_trk_g3_1 +(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_b_33 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp4_h_l_16 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 15) routing tnl_op_5 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_h_l_8 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing lft_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 7) routing sp4_h_l_8 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_33 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_17 <X> lc_trk_g2_1 +(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_b_33 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/WCLK +(2 3) routing lc_trk_g0_0 <X> wire_bram/ram/WCLK +(2 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK +(2 3) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK +(2 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_b_7 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_7 <X> lc_trk_g2_7 +(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_t_0 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(21 12) routing sp4_v_t_14 <X> lc_trk_g3_3 +(21 12) routing sp4_v_t_22 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_t_0 <X> lc_trk_g3_3 +(21 13) routing sp12_v_t_16 <X> lc_trk_g3_3 +(21 13) routing sp4_h_l_30 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_t_22 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_b_7 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_7 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 +(21 2) routing bnr_op_7 <X> lc_trk_g0_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 +(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_t_0 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(21 8) routing sp4_v_t_14 <X> lc_trk_g2_3 +(21 8) routing sp4_v_t_22 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_t_0 <X> lc_trk_g2_3 +(21 9) routing sp12_v_t_16 <X> lc_trk_g2_3 +(21 9) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_t_22 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 1) routing sp12_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2 +(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_47 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6 +(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_30 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(23 12) routing sp12_v_b_11 <X> lc_trk_g3_3 +(23 12) routing sp12_v_t_16 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_14 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_22 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(23 13) routing sp4_v_b_26 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 +(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_47 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6 +(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_30 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 5) routing sp12_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(23 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6 +(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 8) routing sp12_v_b_11 <X> lc_trk_g2_3 +(23 8) routing sp12_v_t_16 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_14 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_22 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(23 9) routing sp4_v_b_26 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(24 1) routing lft_op_2 <X> lc_trk_g0_2 +(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_b_7 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(24 10) routing sp4_v_b_47 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 +(24 11) routing rgt_op_6 <X> lc_trk_g2_6 +(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(24 11) routing tnr_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_t_0 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 +(24 14) routing sp12_v_b_7 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(24 14) routing sp4_v_b_47 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(24 15) routing tnl_op_6 <X> lc_trk_g3_6 +(24 15) routing tnr_op_6 <X> lc_trk_g3_6 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_22 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(24 3) routing top_op_6 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(24 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(24 8) routing sp12_v_t_0 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 8) routing tnr_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing lft_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing rgt_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_30 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 12) routing sp4_v_b_26 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_30 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing tnl_op_6 <X> lc_trk_g3_6 +(25 2) routing bnr_op_6 <X> lc_trk_g0_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 +(25 2) routing sp4_h_r_22 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 3) routing bnr_op_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 3) routing top_op_6 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_h_r_22 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 8) routing sp4_v_b_26 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> input0_0 +(26 0) routing lc_trk_g0_6 <X> input0_0 +(26 0) routing lc_trk_g1_5 <X> input0_0 +(26 0) routing lc_trk_g1_7 <X> input0_0 +(26 0) routing lc_trk_g2_4 <X> input0_0 +(26 0) routing lc_trk_g2_6 <X> input0_0 +(26 0) routing lc_trk_g3_5 <X> input0_0 +(26 0) routing lc_trk_g3_7 <X> input0_0 +(26 1) routing lc_trk_g0_2 <X> input0_0 +(26 1) routing lc_trk_g0_6 <X> input0_0 +(26 1) routing lc_trk_g1_3 <X> input0_0 +(26 1) routing lc_trk_g1_7 <X> input0_0 +(26 1) routing lc_trk_g2_2 <X> input0_0 +(26 1) routing lc_trk_g2_6 <X> input0_0 +(26 1) routing lc_trk_g3_3 <X> input0_0 +(26 1) routing lc_trk_g3_7 <X> input0_0 +(26 10) routing lc_trk_g0_5 <X> input0_5 +(26 10) routing lc_trk_g0_7 <X> input0_5 +(26 10) routing lc_trk_g1_4 <X> input0_5 +(26 10) routing lc_trk_g1_6 <X> input0_5 +(26 10) routing lc_trk_g2_5 <X> input0_5 +(26 10) routing lc_trk_g2_7 <X> input0_5 +(26 10) routing lc_trk_g3_4 <X> input0_5 +(26 10) routing lc_trk_g3_6 <X> input0_5 +(26 11) routing lc_trk_g0_3 <X> input0_5 +(26 11) routing lc_trk_g0_7 <X> input0_5 +(26 11) routing lc_trk_g1_2 <X> input0_5 +(26 11) routing lc_trk_g1_6 <X> input0_5 +(26 11) routing lc_trk_g2_3 <X> input0_5 +(26 11) routing lc_trk_g2_7 <X> input0_5 +(26 11) routing lc_trk_g3_2 <X> input0_5 +(26 11) routing lc_trk_g3_6 <X> input0_5 +(26 12) routing lc_trk_g0_4 <X> input0_6 +(26 12) routing lc_trk_g0_6 <X> input0_6 +(26 12) routing lc_trk_g1_5 <X> input0_6 +(26 12) routing lc_trk_g1_7 <X> input0_6 +(26 12) routing lc_trk_g2_4 <X> input0_6 +(26 12) routing lc_trk_g2_6 <X> input0_6 +(26 12) routing lc_trk_g3_5 <X> input0_6 +(26 12) routing lc_trk_g3_7 <X> input0_6 +(26 13) routing lc_trk_g0_2 <X> input0_6 +(26 13) routing lc_trk_g0_6 <X> input0_6 +(26 13) routing lc_trk_g1_3 <X> input0_6 +(26 13) routing lc_trk_g1_7 <X> input0_6 +(26 13) routing lc_trk_g2_2 <X> input0_6 +(26 13) routing lc_trk_g2_6 <X> input0_6 +(26 13) routing lc_trk_g3_3 <X> input0_6 +(26 13) routing lc_trk_g3_7 <X> input0_6 +(26 14) routing lc_trk_g0_5 <X> input0_7 +(26 14) routing lc_trk_g0_7 <X> input0_7 +(26 14) routing lc_trk_g1_4 <X> input0_7 +(26 14) routing lc_trk_g1_6 <X> input0_7 +(26 14) routing lc_trk_g2_5 <X> input0_7 +(26 14) routing lc_trk_g2_7 <X> input0_7 +(26 14) routing lc_trk_g3_4 <X> input0_7 +(26 14) routing lc_trk_g3_6 <X> input0_7 +(26 15) routing lc_trk_g0_3 <X> input0_7 +(26 15) routing lc_trk_g0_7 <X> input0_7 +(26 15) routing lc_trk_g1_2 <X> input0_7 +(26 15) routing lc_trk_g1_6 <X> input0_7 +(26 15) routing lc_trk_g2_3 <X> input0_7 +(26 15) routing lc_trk_g2_7 <X> input0_7 +(26 15) routing lc_trk_g3_2 <X> input0_7 +(26 15) routing lc_trk_g3_6 <X> input0_7 +(26 2) routing lc_trk_g0_5 <X> input0_1 +(26 2) routing lc_trk_g0_7 <X> input0_1 +(26 2) routing lc_trk_g1_4 <X> input0_1 +(26 2) routing lc_trk_g1_6 <X> input0_1 +(26 2) routing lc_trk_g2_5 <X> input0_1 +(26 2) routing lc_trk_g2_7 <X> input0_1 +(26 2) routing lc_trk_g3_4 <X> input0_1 +(26 2) routing lc_trk_g3_6 <X> input0_1 +(26 3) routing lc_trk_g0_3 <X> input0_1 +(26 3) routing lc_trk_g0_7 <X> input0_1 +(26 3) routing lc_trk_g1_2 <X> input0_1 +(26 3) routing lc_trk_g1_6 <X> input0_1 +(26 3) routing lc_trk_g2_3 <X> input0_1 +(26 3) routing lc_trk_g2_7 <X> input0_1 +(26 3) routing lc_trk_g3_2 <X> input0_1 +(26 3) routing lc_trk_g3_6 <X> input0_1 +(26 4) routing lc_trk_g0_4 <X> input0_2 +(26 4) routing lc_trk_g0_6 <X> input0_2 +(26 4) routing lc_trk_g1_5 <X> input0_2 +(26 4) routing lc_trk_g1_7 <X> input0_2 +(26 4) routing lc_trk_g2_4 <X> input0_2 +(26 4) routing lc_trk_g2_6 <X> input0_2 +(26 4) routing lc_trk_g3_5 <X> input0_2 +(26 4) routing lc_trk_g3_7 <X> input0_2 +(26 5) routing lc_trk_g0_2 <X> input0_2 +(26 5) routing lc_trk_g0_6 <X> input0_2 +(26 5) routing lc_trk_g1_3 <X> input0_2 +(26 5) routing lc_trk_g1_7 <X> input0_2 +(26 5) routing lc_trk_g2_2 <X> input0_2 +(26 5) routing lc_trk_g2_6 <X> input0_2 +(26 5) routing lc_trk_g3_3 <X> input0_2 +(26 5) routing lc_trk_g3_7 <X> input0_2 +(26 6) routing lc_trk_g0_5 <X> input0_3 +(26 6) routing lc_trk_g0_7 <X> input0_3 +(26 6) routing lc_trk_g1_4 <X> input0_3 +(26 6) routing lc_trk_g1_6 <X> input0_3 +(26 6) routing lc_trk_g2_5 <X> input0_3 +(26 6) routing lc_trk_g2_7 <X> input0_3 +(26 6) routing lc_trk_g3_4 <X> input0_3 +(26 6) routing lc_trk_g3_6 <X> input0_3 +(26 7) routing lc_trk_g0_3 <X> input0_3 +(26 7) routing lc_trk_g0_7 <X> input0_3 +(26 7) routing lc_trk_g1_2 <X> input0_3 +(26 7) routing lc_trk_g1_6 <X> input0_3 +(26 7) routing lc_trk_g2_3 <X> input0_3 +(26 7) routing lc_trk_g2_7 <X> input0_3 +(26 7) routing lc_trk_g3_2 <X> input0_3 +(26 7) routing lc_trk_g3_6 <X> input0_3 +(26 8) routing lc_trk_g0_4 <X> input0_4 +(26 8) routing lc_trk_g0_6 <X> input0_4 +(26 8) routing lc_trk_g1_5 <X> input0_4 +(26 8) routing lc_trk_g1_7 <X> input0_4 +(26 8) routing lc_trk_g2_4 <X> input0_4 +(26 8) routing lc_trk_g2_6 <X> input0_4 +(26 8) routing lc_trk_g3_5 <X> input0_4 +(26 8) routing lc_trk_g3_7 <X> input0_4 +(26 9) routing lc_trk_g0_2 <X> input0_4 +(26 9) routing lc_trk_g0_6 <X> input0_4 +(26 9) routing lc_trk_g1_3 <X> input0_4 +(26 9) routing lc_trk_g1_7 <X> input0_4 +(26 9) routing lc_trk_g2_2 <X> input0_4 +(26 9) routing lc_trk_g2_6 <X> input0_4 +(26 9) routing lc_trk_g3_3 <X> input0_4 +(26 9) routing lc_trk_g3_7 <X> input0_4 +(27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 +(27 1) routing lc_trk_g1_1 <X> input0_0 +(27 1) routing lc_trk_g1_3 <X> input0_0 +(27 1) routing lc_trk_g1_5 <X> input0_0 +(27 1) routing lc_trk_g1_7 <X> input0_0 +(27 1) routing lc_trk_g3_1 <X> input0_0 +(27 1) routing lc_trk_g3_3 <X> input0_0 +(27 1) routing lc_trk_g3_5 <X> input0_0 +(27 1) routing lc_trk_g3_7 <X> input0_0 +(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2 +(27 11) routing lc_trk_g1_0 <X> input0_5 +(27 11) routing lc_trk_g1_2 <X> input0_5 +(27 11) routing lc_trk_g1_4 <X> input0_5 +(27 11) routing lc_trk_g1_6 <X> input0_5 +(27 11) routing lc_trk_g3_0 <X> input0_5 +(27 11) routing lc_trk_g3_2 <X> input0_5 +(27 11) routing lc_trk_g3_4 <X> input0_5 +(27 11) routing lc_trk_g3_6 <X> input0_5 +(27 12) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_1 +(27 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1 +(27 13) routing lc_trk_g1_1 <X> input0_6 +(27 13) routing lc_trk_g1_3 <X> input0_6 +(27 13) routing lc_trk_g1_5 <X> input0_6 +(27 13) routing lc_trk_g1_7 <X> input0_6 +(27 13) routing lc_trk_g3_1 <X> input0_6 +(27 13) routing lc_trk_g3_3 <X> input0_6 +(27 13) routing lc_trk_g3_5 <X> input0_6 +(27 13) routing lc_trk_g3_7 <X> input0_6 +(27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_0 +(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_0 +(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_0 +(27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_0 +(27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0 +(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_0 +(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0 +(27 15) routing lc_trk_g1_0 <X> input0_7 +(27 15) routing lc_trk_g1_2 <X> input0_7 +(27 15) routing lc_trk_g1_4 <X> input0_7 +(27 15) routing lc_trk_g1_6 <X> input0_7 +(27 15) routing lc_trk_g3_0 <X> input0_7 +(27 15) routing lc_trk_g3_2 <X> input0_7 +(27 15) routing lc_trk_g3_4 <X> input0_7 +(27 15) routing lc_trk_g3_6 <X> input0_7 +(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6 +(27 3) routing lc_trk_g1_0 <X> input0_1 +(27 3) routing lc_trk_g1_2 <X> input0_1 +(27 3) routing lc_trk_g1_4 <X> input0_1 +(27 3) routing lc_trk_g1_6 <X> input0_1 +(27 3) routing lc_trk_g3_0 <X> input0_1 +(27 3) routing lc_trk_g3_2 <X> input0_1 +(27 3) routing lc_trk_g3_4 <X> input0_1 +(27 3) routing lc_trk_g3_6 <X> input0_1 +(27 4) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_5 +(27 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5 +(27 5) routing lc_trk_g1_1 <X> input0_2 +(27 5) routing lc_trk_g1_3 <X> input0_2 +(27 5) routing lc_trk_g1_5 <X> input0_2 +(27 5) routing lc_trk_g1_7 <X> input0_2 +(27 5) routing lc_trk_g3_1 <X> input0_2 +(27 5) routing lc_trk_g3_3 <X> input0_2 +(27 5) routing lc_trk_g3_5 <X> input0_2 +(27 5) routing lc_trk_g3_7 <X> input0_2 +(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 +(27 7) routing lc_trk_g1_0 <X> input0_3 +(27 7) routing lc_trk_g1_2 <X> input0_3 +(27 7) routing lc_trk_g1_4 <X> input0_3 +(27 7) routing lc_trk_g1_6 <X> input0_3 +(27 7) routing lc_trk_g3_0 <X> input0_3 +(27 7) routing lc_trk_g3_2 <X> input0_3 +(27 7) routing lc_trk_g3_4 <X> input0_3 +(27 7) routing lc_trk_g3_6 <X> input0_3 +(27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 +(27 9) routing lc_trk_g1_1 <X> input0_4 +(27 9) routing lc_trk_g1_3 <X> input0_4 +(27 9) routing lc_trk_g1_5 <X> input0_4 +(27 9) routing lc_trk_g1_7 <X> input0_4 +(27 9) routing lc_trk_g3_1 <X> input0_4 +(27 9) routing lc_trk_g3_3 <X> input0_4 +(27 9) routing lc_trk_g3_5 <X> input0_4 +(27 9) routing lc_trk_g3_7 <X> input0_4 +(28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 +(28 1) routing lc_trk_g2_0 <X> input0_0 +(28 1) routing lc_trk_g2_2 <X> input0_0 +(28 1) routing lc_trk_g2_4 <X> input0_0 +(28 1) routing lc_trk_g2_6 <X> input0_0 +(28 1) routing lc_trk_g3_1 <X> input0_0 +(28 1) routing lc_trk_g3_3 <X> input0_0 +(28 1) routing lc_trk_g3_5 <X> input0_0 +(28 1) routing lc_trk_g3_7 <X> input0_0 +(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 +(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2 +(28 11) routing lc_trk_g2_1 <X> input0_5 +(28 11) routing lc_trk_g2_3 <X> input0_5 +(28 11) routing lc_trk_g2_5 <X> input0_5 +(28 11) routing lc_trk_g2_7 <X> input0_5 +(28 11) routing lc_trk_g3_0 <X> input0_5 +(28 11) routing lc_trk_g3_2 <X> input0_5 +(28 11) routing lc_trk_g3_4 <X> input0_5 +(28 11) routing lc_trk_g3_6 <X> input0_5 +(28 12) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_1 +(28 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1 +(28 13) routing lc_trk_g2_0 <X> input0_6 +(28 13) routing lc_trk_g2_2 <X> input0_6 +(28 13) routing lc_trk_g2_4 <X> input0_6 +(28 13) routing lc_trk_g2_6 <X> input0_6 +(28 13) routing lc_trk_g3_1 <X> input0_6 +(28 13) routing lc_trk_g3_3 <X> input0_6 +(28 13) routing lc_trk_g3_5 <X> input0_6 +(28 13) routing lc_trk_g3_7 <X> input0_6 +(28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_0 +(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0 +(28 15) routing lc_trk_g2_1 <X> input0_7 +(28 15) routing lc_trk_g2_3 <X> input0_7 +(28 15) routing lc_trk_g2_5 <X> input0_7 +(28 15) routing lc_trk_g2_7 <X> input0_7 +(28 15) routing lc_trk_g3_0 <X> input0_7 +(28 15) routing lc_trk_g3_2 <X> input0_7 +(28 15) routing lc_trk_g3_4 <X> input0_7 +(28 15) routing lc_trk_g3_6 <X> input0_7 +(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 +(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6 +(28 3) routing lc_trk_g2_1 <X> input0_1 +(28 3) routing lc_trk_g2_3 <X> input0_1 +(28 3) routing lc_trk_g2_5 <X> input0_1 +(28 3) routing lc_trk_g2_7 <X> input0_1 +(28 3) routing lc_trk_g3_0 <X> input0_1 +(28 3) routing lc_trk_g3_2 <X> input0_1 +(28 3) routing lc_trk_g3_4 <X> input0_1 +(28 3) routing lc_trk_g3_6 <X> input0_1 +(28 4) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_5 +(28 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5 +(28 5) routing lc_trk_g2_0 <X> input0_2 +(28 5) routing lc_trk_g2_2 <X> input0_2 +(28 5) routing lc_trk_g2_4 <X> input0_2 +(28 5) routing lc_trk_g2_6 <X> input0_2 +(28 5) routing lc_trk_g3_1 <X> input0_2 +(28 5) routing lc_trk_g3_3 <X> input0_2 +(28 5) routing lc_trk_g3_5 <X> input0_2 +(28 5) routing lc_trk_g3_7 <X> input0_2 +(28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 +(28 7) routing lc_trk_g2_1 <X> input0_3 +(28 7) routing lc_trk_g2_3 <X> input0_3 +(28 7) routing lc_trk_g2_5 <X> input0_3 +(28 7) routing lc_trk_g2_7 <X> input0_3 +(28 7) routing lc_trk_g3_0 <X> input0_3 +(28 7) routing lc_trk_g3_2 <X> input0_3 +(28 7) routing lc_trk_g3_4 <X> input0_3 +(28 7) routing lc_trk_g3_6 <X> input0_3 +(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3 +(28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 +(28 9) routing lc_trk_g2_0 <X> input0_4 +(28 9) routing lc_trk_g2_2 <X> input0_4 +(28 9) routing lc_trk_g2_4 <X> input0_4 +(28 9) routing lc_trk_g2_6 <X> input0_4 +(28 9) routing lc_trk_g3_1 <X> input0_4 +(28 9) routing lc_trk_g3_3 <X> input0_4 +(28 9) routing lc_trk_g3_5 <X> input0_4 +(28 9) routing lc_trk_g3_7 <X> input0_4 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_2 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 +(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_1 +(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_1 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 +(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_0 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_0 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 +(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_6 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 +(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_5 +(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_5 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 +(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_4 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 +(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_3 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 +(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_h_l_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_h_l_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 +(30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2 +(30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_1 +(30 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_1 +(30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1 +(30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_0 +(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0 +(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0 +(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6 +(30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_5 +(30 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5 +(30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5 +(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 +(30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 +(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 +(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_7 +(31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7 +(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 +(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 +(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 +(31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 +(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 +(31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_3 +(31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_3 +(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 +(31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 +(31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 +(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_0 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_6 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 +(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 +(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_2 +(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2 +(33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 +(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 +(33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(33 11) routing lc_trk_g2_1 <X> input2_5 +(33 11) routing lc_trk_g2_5 <X> input2_5 +(33 11) routing lc_trk_g2_7 <X> input2_5 +(33 11) routing lc_trk_g3_0 <X> input2_5 +(33 11) routing lc_trk_g3_2 <X> input2_5 +(33 11) routing lc_trk_g3_4 <X> input2_5 +(33 11) routing lc_trk_g3_6 <X> input2_5 +(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 +(33 13) routing lc_trk_g2_0 <X> input2_6 +(33 13) routing lc_trk_g2_2 <X> input2_6 +(33 13) routing lc_trk_g2_4 <X> input2_6 +(33 13) routing lc_trk_g2_6 <X> input2_6 +(33 13) routing lc_trk_g3_1 <X> input2_6 +(33 13) routing lc_trk_g3_3 <X> input2_6 +(33 13) routing lc_trk_g3_5 <X> input2_6 +(33 13) routing lc_trk_g3_7 <X> input2_6 +(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_0 +(33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0 +(33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 +(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_0 +(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0 +(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0 +(33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 +(33 15) routing lc_trk_g2_1 <X> input2_7 +(33 15) routing lc_trk_g2_3 <X> input2_7 +(33 15) routing lc_trk_g2_5 <X> input2_7 +(33 15) routing lc_trk_g2_7 <X> input2_7 +(33 15) routing lc_trk_g3_0 <X> input2_7 +(33 15) routing lc_trk_g3_2 <X> input2_7 +(33 15) routing lc_trk_g3_4 <X> input2_7 +(33 15) routing lc_trk_g3_6 <X> input2_7 +(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 +(33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 +(33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_3 +(33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3 +(33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_3 +(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 +(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3 +(33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 +(33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 +(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 +(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 +(34 11) routing lc_trk_g1_4 <X> input2_5 +(34 11) routing lc_trk_g1_6 <X> input2_5 +(34 11) routing lc_trk_g3_0 <X> input2_5 +(34 11) routing lc_trk_g3_2 <X> input2_5 +(34 11) routing lc_trk_g3_4 <X> input2_5 +(34 11) routing lc_trk_g3_6 <X> input2_5 +(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 +(34 13) routing lc_trk_g1_1 <X> input2_6 +(34 13) routing lc_trk_g1_3 <X> input2_6 +(34 13) routing lc_trk_g1_5 <X> input2_6 +(34 13) routing lc_trk_g1_7 <X> input2_6 +(34 13) routing lc_trk_g3_1 <X> input2_6 +(34 13) routing lc_trk_g3_3 <X> input2_6 +(34 13) routing lc_trk_g3_5 <X> input2_6 +(34 13) routing lc_trk_g3_7 <X> input2_6 +(34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 +(34 15) routing lc_trk_g1_0 <X> input2_7 +(34 15) routing lc_trk_g1_2 <X> input2_7 +(34 15) routing lc_trk_g1_4 <X> input2_7 +(34 15) routing lc_trk_g1_6 <X> input2_7 +(34 15) routing lc_trk_g3_0 <X> input2_7 +(34 15) routing lc_trk_g3_2 <X> input2_7 +(34 15) routing lc_trk_g3_4 <X> input2_7 +(34 15) routing lc_trk_g3_6 <X> input2_7 +(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 +(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 +(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 +(34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_3 +(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3 +(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3 +(34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 +(34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 +(35 10) routing lc_trk_g1_4 <X> input2_5 +(35 10) routing lc_trk_g1_6 <X> input2_5 +(35 10) routing lc_trk_g2_5 <X> input2_5 +(35 10) routing lc_trk_g2_7 <X> input2_5 +(35 10) routing lc_trk_g3_4 <X> input2_5 +(35 10) routing lc_trk_g3_6 <X> input2_5 +(35 11) routing lc_trk_g0_3 <X> input2_5 +(35 11) routing lc_trk_g1_6 <X> input2_5 +(35 11) routing lc_trk_g2_7 <X> input2_5 +(35 11) routing lc_trk_g3_2 <X> input2_5 +(35 11) routing lc_trk_g3_6 <X> input2_5 +(35 12) routing lc_trk_g0_4 <X> input2_6 +(35 12) routing lc_trk_g0_6 <X> input2_6 +(35 12) routing lc_trk_g1_5 <X> input2_6 +(35 12) routing lc_trk_g1_7 <X> input2_6 +(35 12) routing lc_trk_g2_4 <X> input2_6 +(35 12) routing lc_trk_g2_6 <X> input2_6 +(35 12) routing lc_trk_g3_5 <X> input2_6 +(35 12) routing lc_trk_g3_7 <X> input2_6 +(35 13) routing lc_trk_g0_2 <X> input2_6 +(35 13) routing lc_trk_g0_6 <X> input2_6 +(35 13) routing lc_trk_g1_3 <X> input2_6 +(35 13) routing lc_trk_g1_7 <X> input2_6 +(35 13) routing lc_trk_g2_2 <X> input2_6 +(35 13) routing lc_trk_g2_6 <X> input2_6 +(35 13) routing lc_trk_g3_3 <X> input2_6 +(35 13) routing lc_trk_g3_7 <X> input2_6 +(35 14) routing lc_trk_g0_5 <X> input2_7 +(35 14) routing lc_trk_g0_7 <X> input2_7 +(35 14) routing lc_trk_g1_4 <X> input2_7 +(35 14) routing lc_trk_g1_6 <X> input2_7 +(35 14) routing lc_trk_g2_5 <X> input2_7 +(35 14) routing lc_trk_g2_7 <X> input2_7 +(35 14) routing lc_trk_g3_4 <X> input2_7 +(35 14) routing lc_trk_g3_6 <X> input2_7 +(35 15) routing lc_trk_g0_3 <X> input2_7 +(35 15) routing lc_trk_g0_7 <X> input2_7 +(35 15) routing lc_trk_g1_2 <X> input2_7 +(35 15) routing lc_trk_g1_6 <X> input2_7 +(35 15) routing lc_trk_g2_3 <X> input2_7 +(35 15) routing lc_trk_g2_7 <X> input2_7 +(35 15) routing lc_trk_g3_2 <X> input2_7 +(35 15) routing lc_trk_g3_6 <X> input2_7 +(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 +(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 +(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 +(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 +(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 +(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 +(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 +(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 +(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 +(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 +(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 +(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 +(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 +(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 +(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 +(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_2 sp4_h_l_15 +(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_1 sp12_h_l_3 +(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_1 sp4_h_l_17 +(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_0 sp12_h_l_5 +(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_0 sp4_h_r_30 +(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_6 sp12_h_r_10 +(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_6 sp4_h_l_7 +(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_5 sp12_h_r_12 +(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_5 sp4_h_r_20 +(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_4 sp12_h_l_13 +(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_4 sp4_h_r_22 +(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_3 sp12_h_r_0 +(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 +(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 +(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 +(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 +(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 +(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 +(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 +(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_0 sp4_v_b_30 +(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_0 sp12_h_l_21 +(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_6 sp4_v_t_23 +(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_6 sp4_v_b_2 +(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_5 sp4_v_t_25 +(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_5 sp4_v_b_4 +(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_4 sp4_v_b_38 +(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_4 sp4_v_b_6 +(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_3 sp12_h_r_16 +(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_7 sp12_v_b_0 +(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_7 sp4_v_b_16 +(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_2 sp4_v_t_31 +(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_2 sp4_v_b_10 +(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_1 sp4_v_t_33 +(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_1 sp4_v_t_1 +(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_0 sp4_v_b_46 +(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_0 sp4_v_b_14 +(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_6 sp12_v_b_2 +(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_6 sp4_v_t_7 +(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_5 sp12_v_t_3 +(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_5 sp4_v_b_20 +(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_4 sp12_v_b_6 +(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_4 sp4_v_b_22 +(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_3 sp4_v_b_40 +(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_3 sp4_v_b_8 +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_h_l_43 <X> sp4_h_r_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_h_r_0 <X> sp4_h_l_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 +(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 +(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 +(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 +(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_29 +(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 +(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 +(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 +(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 +(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 +(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 +(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 +(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_23 +(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_4 sp12_v_t_21 +(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 +(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 +(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 +(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 +(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 +(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 +(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 +(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_13 +(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_47 +(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_15 +(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_35 +(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_3 +(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_37 +(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_5 +(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_39 +(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_7 +(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_41 +(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_9 +(5 0) routing sp4_v_t_37 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_h_l_43 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 12) routing sp4_v_t_44 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_h_r_9 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_44 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_h_r_0 <X> sp4_h_l_38 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_h_l_37 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(6 11) routing sp4_h_r_6 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_h_r_9 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_44 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 0) Ram config bit: MEMT_bram_cbit_1 +(7 1) Ram config bit: MEMT_bram_cbit_0 +(7 10) Column buffer control bit: MEMT_colbuf_cntl_3 +(7 11) Column buffer control bit: MEMT_colbuf_cntl_2 +(7 12) Column buffer control bit: MEMT_colbuf_cntl_5 +(7 13) Column buffer control bit: MEMT_colbuf_cntl_4 +(7 14) Column buffer control bit: MEMT_colbuf_cntl_7 +(7 15) Column buffer control bit: MEMT_colbuf_cntl_6 +(7 2) Ram config bit: MEMT_bram_cbit_3 +(7 3) Ram config bit: MEMT_bram_cbit_2 +(7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 +(7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 +(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_7 +(7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC06_inmux02_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC07_inmux02_bram_cbit_6 +(7 8) Column buffer control bit: MEMT_colbuf_cntl_1 +(7 9) Column buffer control bit: MEMT_colbuf_cntl_0 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_h_r_11 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_10 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_41 <X> sp4_h_r_4 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_h_r_1 <X> sp4_h_l_41 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/database.py b/icefuzz/database.py index e32b771..8cb81d8 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -2,6 +2,8 @@ import re, sys, os +device_class = os.getenv("ICEDEVICE") + def sort_bits_key(a): if a[0] == "!": a = a[1:] return re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a) @@ -38,6 +40,9 @@ def read_database(filename, tile_type): if bit == "B9[3]" and line == ['IoCtrl', 'IE_1']: continue if bit == "B1[3]" and line == ['IoCtrl', 'REN_0']: continue if bit == "B6[2]" and line == ['IoCtrl', 'REN_1']: continue + # Ignore some additional configuration bits that sneaked in via ice5k fuzzing + if line[0] == "IoCtrl" and line[1].startswith("cf_bit_"): continue + if line[0] == "IoCtrl" and line[1].startswith("extra_padeb_test_"): continue raw_db.append((bit, (line[0], line[1]))) elif line[0] in ("IOB_0", "IOB_1"): if line[1] != "IO": @@ -136,11 +141,11 @@ with open("database_ramt.txt", "w") as f: for entry in read_database("bitdata_ramt.txt", "ramt"): print("\t".join(entry), file=f) -with open("database_ramb_8k.txt", "w") as f: - for entry in read_database("bitdata_ramb_8k.txt", "ramb_8k"): - print("\t".join(entry), file=f) - -with open("database_ramt_8k.txt", "w") as f: - for entry in read_database("bitdata_ramt_8k.txt", "ramt_8k"): - print("\t".join(entry), file=f) +for device_class in ["5k", "8k"]: + with open("database_ramb_%s.txt" % (device_class, ), "w") as f: + for entry in read_database("bitdata_ramb_%s.txt" % (device_class, ), "ramb_" + device_class): + print("\t".join(entry), file=f) + with open("database_ramt_%s.txt" % (device_class, ), "w") as f: + for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class): + print("\t".join(entry), file=f) diff --git a/icefuzz/export.py b/icefuzz/export.py index ae14997..52625f2 100644 --- a/icefuzz/export.py +++ b/icefuzz/export.py @@ -1,10 +1,16 @@ #!/usr/bin/env python3 +import os + +device_class = os.getenv("ICEDEVICE") with open("../icebox/iceboxdb.py", "w") as f: - for i in [ "database_io", "database_logic", "database_ramb", "database_ramt", "database_ramb_8k", "database_ramt_8k" ]: + files = [ "database_io", "database_logic", "database_ramb", "database_ramt"] + for device_class in ["5k", "8k"]: + files.append("database_ramb_" + device_class) + files.append("database_ramt_" + device_class) + for i in files: print('%s_txt = """' % i, file=f) with open("%s.txt" % i, "r") as fi: for line in fi: print(line, end="", file=f) print('"""', file=f) - diff --git a/icefuzz/extract.py b/icefuzz/extract.py index 1ffac8a..75be225 100644 --- a/icefuzz/extract.py +++ b/icefuzz/extract.py @@ -1,5 +1,5 @@ #!/usr/bin/env python3 - +import os import sys, re db = set() @@ -9,36 +9,38 @@ mode_384 = False cur_text_db = None max_x, max_y = 0, 0 -if sys.argv[1] == '-8': - sys.argv = sys.argv[1:] - mode_8k = True - -if sys.argv[1] == '-3': - sys.argv = sys.argv[1:] - mode_384 = True +device_class = os.getenv("ICEDEVICE") for filename in sys.argv[1:]: with open(filename, "r") as f: + ignore = False for line in f: if line == "\n": pass elif line.startswith("GlobalNetwork"): cur_text_db = set() + ignore = False elif line.startswith("IO"): match = re.match("IO_Tile_(\d+)_(\d+)", line) assert match max_x = max(max_x, int(match.group(1))) max_y = max(max_y, int(match.group(2))) cur_text_db = text_db.setdefault("io", set()) + ignore = False elif line.startswith("Logic"): cur_text_db = text_db.setdefault("logic", set()) + ignore = False elif line.startswith("RAM"): match = re.match(r"RAM_Tile_\d+_(\d+)", line) if int(match.group(1)) % 2 == 1: - cur_text_db = text_db.setdefault("ramb_8k" if mode_8k else "ramb", set()) + cur_text_db = text_db.setdefault("ramb_" + device_class if device_class in ["5k", "8k"] else "ramb", set()) else: - cur_text_db = text_db.setdefault("ramt_8k" if mode_8k else "ramt", set()) - else: + cur_text_db = text_db.setdefault("ramt_" + device_class if device_class in ["5k", "8k"] else "ramt", set()) + ignore = False + elif device_class == "5k" and line.startswith(("IpCon", "DSP")): + ignore = True + elif not ignore: + print("'" + line + "'") assert line.startswith(" ") cur_text_db.add(line) @@ -60,4 +62,3 @@ for tile_type in text_db: for line in sorted(db): print(line) - diff --git a/icefuzz/fuzzconfig.py b/icefuzz/fuzzconfig.py index 19cbec3..1af5834 100644 --- a/icefuzz/fuzzconfig.py +++ b/icefuzz/fuzzconfig.py @@ -2,8 +2,11 @@ import os num = 20 -if os.getenv('ICE8KPINS'): +device_class = os.getenv("ICEDEVICE") + +if device_class == "8k": num_ramb40 = 32 + num_iobanks = 4 pins=""" A1 A2 A5 A6 A7 A9 A10 A11 A15 A16 @@ -26,8 +29,9 @@ if os.getenv('ICE8KPINS'): gpins = "C8 F7 G1 H11 H16 I3 K9 R9".split() -elif os.getenv('ICE384PINS'): +elif device_class == "384": num_ramb40 = 0 + num_iobanks = 3 pins = """ A1 A2 A3 A4 A5 A6 A7 @@ -41,8 +45,9 @@ elif os.getenv('ICE384PINS'): gpins = "B4 C4 D2 D6 D7 E2 F3 F4".split() -else: +elif device_class == "1k": num_ramb40 = 16 + num_iobanks = 4 pins = """ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 @@ -52,4 +57,26 @@ else: """.split() gpins = "20 21 49 50 93 94 128 129".split() +elif device_class == "5k": + num_ramb40 = 30 + num_iobanks = 2 + + #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. + # Also add 14 15 16 17 which are constrained to SPI. + pins = """2 3 4 6 9 10 11 12 + 13 18 19 20 21 23 + 25 26 27 28 31 32 34 35 36 + 37 38 42 43 44 45 46 47 48 + """.split() + #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. + gpins = "20 35 37 44".split() + +def output_makefile(working_dir, fuzzname): + with open(working_dir + "/Makefile", "w") as f: + print("all: %s" % " ".join(["%s_%02d.bin" % (fuzzname, i) for i in range(num)]), file=f) + for i in range(num): + basename = "%s_%02d" % (fuzzname, i) + print("%s.bin:" % basename, file=f) + print("\t-bash ../icecube.sh %s > %s.log 2>&1 && rm -rf %s.tmp || tail %s.log" % (basename, basename, basename, basename), file=f) + print("\tpython3 ../glbcheck.py %s.asc %s.glb" % (basename, basename), file=f) diff --git a/icefuzz/glbcheck.py b/icefuzz/glbcheck.py index 4c86f0e..742c335 100644 --- a/icefuzz/glbcheck.py +++ b/icefuzz/glbcheck.py @@ -30,13 +30,13 @@ with open(argv[1]) as f: with open(argv[2]) as f: current_tile = None for line in f: - if line.find("Tile_") >= 0: + if line.startswith(("Tile", "IO_Tile", "RAM_Tile", "LogicTile")): f = line.replace("IO_", "").replace("RAM_", "").split("_") assert len(f) == 3 current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) continue - if line.find("GlobalNetwork") >= 0: + if line.find("GlobalNetwork") >= 0 or line.startswith(("IpCon", "DSP")): current_tile = None continue @@ -54,10 +54,15 @@ only_in_asc = asc_bits - glb_bits only_in_glb = glb_bits - asc_bits assert len(only_in_asc) != 0 or len(only_in_glb) != 0 -if len(only_in_asc) != 0: - print("Only in ASC: %s" % sorted(only_in_asc)) -if len(only_in_glb) != 0: - print("Only in GLB: %s" % sorted(only_in_glb)) +print("Only in ASC:") +for bit in sorted(only_in_asc): + print(bit) + +print() + +print("Only in GLB:") +for bit in sorted(only_in_glb): + print(bit) exit(1) diff --git a/icefuzz/icecube.sh b/icefuzz/icecube.sh index a13d440..422ded6 100644 --- a/icefuzz/icecube.sh +++ b/icefuzz/icecube.sh @@ -51,9 +51,15 @@ if [ "$1" == "-ul1k" ]; then shift fi +if [ "$1" == "-up5k" ]; then + ICEDEV=up5k-sg48 + shift +fi + set -ex set -- ${1%.v} icecubedir="${ICECUBEDIR:-/opt/lscc/iCEcube2.2015.08}" +if [ -d $icecubedir/LSE/bin/lin64 ]; then lin_lin64=lin64; else lin_lin64=lin; fi export FOUNDRY="$icecubedir/LSE" export SBT_DIR="$icecubedir/sbt_backend" export SYNPLIFY_PATH="$icecubedir/synpbase" @@ -62,7 +68,7 @@ export TCL_LIBRARY="$icecubedir/sbt_backend/bin/linux/lib/tcl8.4" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt/synpwrap" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/lib/linux/opt" -export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/LSE/bin/lin" +export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/LSE/bin/${lin_lin64}" case "${ICEDEV:-hx1k-tq144}" in hx1k-cb132) @@ -173,6 +179,10 @@ case "${ICEDEV:-hx1k-tq144}" in iCEPACKAGE="CM36A" iCE40DEV="iCE40UL1K" ;; + up5k-sg48) + iCEPACKAGE="SG48" + iCE40DEV="iCE40UP5K" + ;; *) echo "ERROR: Invalid \$ICEDEV device config '$ICEDEV'." exit 1 @@ -219,6 +229,11 @@ case "$iCE40DEV" in libfile="ice40BT1K.lib" devfile="ICE40T01.dev" ;; + iCE40UP5K) + icetech="SBTiCE40UP" + libfile="ice40UP5K.lib" + devfile="ICE40T05.dev" + ;; esac ( @@ -334,7 +349,7 @@ fi # synthesis (Lattice LSE) if true; then - "$icecubedir"/LSE/bin/lin/synthesis -f "impl_lse.prj" + "$icecubedir"/LSE/bin/${lin_lin64}/synthesis -f "impl_lse.prj" fi # convert netlist diff --git a/icefuzz/make_aig.py b/icefuzz/make_aig.py index 8dd5ef0..6880f21 100644 --- a/icefuzz/make_aig.py +++ b/icefuzz/make_aig.py @@ -4,14 +4,20 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_aig") -os.mkdir("work_aig") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_aig" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +w = len(pins) // 2 for idx in range(num): - with open("work_aig/aig_%02d.v" % idx, "w") as f: - print("module top(input [31:0] a, output [31:0] y);", file=f) + with open(working_dir + "/aig_%02d.v" % idx, "w") as f: + print("module top(input [%d:0] a, output [%d:0] y);" % (w-1, w-1), file=f) - sigs = ["a[%d]" % i for i in range(32)] + sigs = ["a[%d]" % i for i in range(w)] netidx = 0 for i in range(100 if num_ramb40 < 20 else 1000): @@ -24,7 +30,7 @@ for idx in range(num): sigs.append(newnet) - while len(sigs) > 32: + while len(sigs) > w: netidx += 1 newnet = "n_%d" % netidx @@ -40,20 +46,16 @@ for idx in range(num): sigs.append(newnet) - for i in range(32): + for i in range(w): print(" assign y[%d] = %s;" % (i, sigs[i]), file=f) print("endmodule", file=f) - with open("work_aig/aig_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/aig_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) - for i in range(32): + for i in range(w): print("set_io a[%d] %s" % (i, p[i]), file=f) - print("set_io y[%d] %s" % (i, p[i+32]), file=f) + print("set_io y[%d] %s" % (i, p[i+w]), file=f) -with open("work_aig/Makefile", "w") as f: - print("all: %s" % " ".join(["aig_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("aig_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh aig_%02d > aig_%02d.log 2>&1 && rm -rf aig_%02d.tmp || tail aig_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "aig") diff --git a/icefuzz/make_binop.py b/icefuzz/make_binop.py index b84ee7d..ada9d56 100644 --- a/icefuzz/make_binop.py +++ b/icefuzz/make_binop.py @@ -4,23 +4,24 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_binop") -os.mkdir("work_binop") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_binop" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_binop/binop_%02d.v" % idx, "w") as f: + with open(working_dir + "/binop_%02d.v" % idx, "w") as f: print("module top(input a, b, output y);", file=f) print(" assign y = a%sb;" % np.random.choice([" ^ ", " ^ ~", " & ", " & ~", " | ", " | ~"]), file=f) print("endmodule", file=f) - with open("work_binop/binop_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/binop_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) print("set_io a %s" % p[0], file=f) print("set_io b %s" % p[1], file=f) print("set_io y %s" % p[2], file=f) -with open("work_binop/Makefile", "w") as f: - print("all: %s" % " ".join(["binop_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("binop_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh binop_%02d > binop_%02d.log 2>&1 && rm -rf binop_%02d.tmp || tail binop_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "binop") diff --git a/icefuzz/make_cluster.py b/icefuzz/make_cluster.py index 0188de3..554d746 100644 --- a/icefuzz/make_cluster.py +++ b/icefuzz/make_cluster.py @@ -4,24 +4,23 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_cluster") -os.mkdir("work_cluster") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_cluster" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_cluster/cluster_%02d.v" % idx, "w") as f: + with open(working_dir + "/cluster_%02d.v" % idx, "w") as f: print("module top(input [3:0] a, output [3:0] y);", file=f) print(" assign y = {|a, &a, ^a, a[3:2] == a[1:0]};", file=f) print("endmodule", file=f) - with open("work_cluster/cluster_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/cluster_%02d.pcf" % idx, "w") as f: i = np.random.randint(len(pins)) netnames = np.random.permutation(["a[%d]" % i for i in range(4)] + ["y[%d]" % i for i in range(4)]) for net in netnames: print("set_io %s %s" % (net, pins[i]), file=f) i = (i + 1) % len(pins) -with open("work_cluster/Makefile", "w") as f: - print("all: %s" % " ".join(["cluster_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("cluster_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh cluster_%02d > cluster_%02d.log 2>&1 && rm -rf cluster_%02d.tmp || tail cluster_%02d.log" % (i, i, i, i), file=f) - +output_makefile(working_dir, "cluster") diff --git a/icefuzz/make_fanout.py b/icefuzz/make_fanout.py index 510fa00..95d61d5 100644 --- a/icefuzz/make_fanout.py +++ b/icefuzz/make_fanout.py @@ -4,29 +4,26 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_fanout") -os.mkdir("work_fanout") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_fanout" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + for idx in range(num): - with open("work_fanout/fanout_%02d.v" % idx, "w") as f: - if os.getenv('ICE384PINS'): - print("module top(input [1:0] a, output [33:0] y);", file=f) - print(" assign y = {8{a}};", file=f) - else: - print("module top(input [1:0] a, output [63:0] y);", file=f) - print(" assign y = {32{a}};", file=f) + output_count = len(pins) - 2 + with open(working_dir + "/fanout_%02d.v" % idx, "w") as f: + print("module top(input [1:0] a, output [%d:0] y);" % (output_count,), file=f) + print(" assign y = {%d{a}};" % (output_count,), file=f) print("endmodule", file=f) - with open("work_fanout/fanout_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/fanout_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) - r = 34 if os.getenv('ICE384PINS') else 64 - for i in range(r): + for i in range(output_count): print("set_io y[%d] %s" % (i, p[i]), file=f) - print("set_io a[0] %s" % p[r], file=f) - print("set_io a[1] %s" % p[r+1], file=f) + print("set_io a[0] %s" % p[output_count], file=f) + print("set_io a[1] %s" % p[output_count+1], file=f) -with open("work_fanout/Makefile", "w") as f: - print("all: %s" % " ".join(["fanout_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("fanout_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh fanout_%02d > fanout_%02d.log 2>&1 && rm -rf fanout_%02d.tmp || tail fanout_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "fanout") diff --git a/icefuzz/make_fflogic.py b/icefuzz/make_fflogic.py index 91a5d05..bac0569 100644 --- a/icefuzz/make_fflogic.py +++ b/icefuzz/make_fflogic.py @@ -4,8 +4,14 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_fflogic") -os.mkdir("work_fflogic") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_fflogic" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +w = (len(pins) - 4) // 5 def random_op(): return np.random.choice(["+", "-", "*", "^", "&", "|"]) @@ -36,22 +42,14 @@ def print_seq_op(dst, src1, src2, op, f): assert False for idx in range(num): - with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f: - if os.getenv('ICE384PINS'): - print("module top(input clk, rst, en, input [4:0] a, b, c, d, output [4:0] y, output z);", file=f) - print(" reg [4:0] p, q;", file=f) - else: - print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f) - print(" reg [15:0] p, q;", file=f) + with open(working_dir + "/fflogic_%02d.v" % idx, "w") as f: + print("module top(input clk, rst, en, input [%d:0] a, b, c, d, output [%d:0] y, output z);" % (w-1, w-1), file=f) + print(" reg [%d:0] p, q;" % (w-1,), file=f) print_seq_op("p", "a", "b", random_op(), f) print_seq_op("q", "c", "d", random_op(), f) print(" assign y = p %s q, z = clk ^ rst ^ en;" % random_op(), file=f) print("endmodule", file=f) -with open("work_fflogic/Makefile", "w") as f: - print("all: %s" % " ".join(["fflogic_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("fflogic_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh fflogic_%02d > fflogic_%02d.log 2>&1 && rm -rf fflogic_%02d.tmp || tail fflogic_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "fflogic") diff --git a/icefuzz/make_gbio.py b/icefuzz/make_gbio.py index 555d37d..b9b2f12 100644 --- a/icefuzz/make_gbio.py +++ b/icefuzz/make_gbio.py @@ -4,17 +4,31 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_gbio") -os.mkdir("work_gbio") +device_class = os.getenv("ICEDEVICE") -w = 4 if os.getenv('ICE384PINS') else 8 +working_dir = "work_%s_gbio" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for p in gpins: if p in pins: pins.remove(p) +# We can either tickle every global buffer or we don't have enough pins to do +# the full logic for each one. +w = min(min((len(pins) - 8) // 4, len(gpins)), 8) + for idx in range(num): - with open("work_gbio/gbio_%02d.v" % idx, "w") as f: + with open(working_dir + "/gbio_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) + + if w <= 4: + din_0 = (w - 2, w) + else: + din_0 = (3, "%d:4" % (w - 1,)) + din_0 = np.random.choice(["din_0", "{din_0[%d:0], din_0[%s]}" % din_0]) + din_1 = np.random.choice(["din_1", "{din_1[1:0], din_1[%d:2]}" % (w - 1,)]) + globals_0 = np.random.choice(["globals", "{globals[0], globals[%d:1]}" % (w - 1, )]) print(""" module top ( inout [%s:0] pin, @@ -64,15 +78,12 @@ for idx in range(num): np.random.choice(["oen", "globals", "din_0+din_1", "din_0^din_1"]), np.random.choice(["dout_1", "globals", "globals^dout_0", "din_0+din_1", "~din_0"]), np.random.choice(["dout_0", "globals", "globals^dout_1", "din_0+din_1", "~din_1"]), - np.random.choice(["din_0", "{din_0[2:0], din_0[3]}"]) if os.getenv('ICE384PINS') - else np.random.choice(["din_0", "{din_0[3:0], din_0[7:4]}"]) , - np.random.choice(["din_1", "{din_1[1:0], din_1[3:2]}"]) if os.getenv('ICE384PINS') - else np.random.choice(["din_1", "{din_1[1:0], din_1[7:2]}"]), - np.random.choice(["globals", "{globals[0], globals[3:1]}"]) if os.getenv('ICE384PINS') - else np.random.choice(["globals", "{globals[0], globals[7:1]}"]), + din_0, + din_1, + globals_0, glbs[0], glbs[1], glbs[1], glbs[2], glbs[3] ), file=f) - with open("work_gbio/gbio_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/gbio_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) g = np.random.permutation(gpins) for i in range(w): @@ -84,9 +95,5 @@ for idx in range(num): print("set_io %s %s" % (n, p[4*w+i]), file=f) print("set_io q %s" % (p[-1]), file=f) -with open("work_gbio/Makefile", "w") as f: - print("all: %s" % " ".join(["gbio_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("gbio_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh gbio_%02d > gbio_%02d.log 2>&1 && rm -rf gbio_%02d.tmp || tail gbio_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "gbio") diff --git a/icefuzz/make_gbio2.py b/icefuzz/make_gbio2.py index 2b62ba4..fedc8c8 100644 --- a/icefuzz/make_gbio2.py +++ b/icefuzz/make_gbio2.py @@ -4,16 +4,22 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_gbio2") -os.mkdir("work_gbio2") +device_class = os.getenv("ICEDEVICE") -w = 4 if os.getenv('ICE384PINS') else 8 +working_dir = "work_%s_gbio2" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for p in gpins: if p in pins: pins.remove(p) +# We can either tickle every global buffer or we don't have enough pins to do +# the full logic for each one. +w = min(min((len(pins) - 8) // 4, len(gpins)), 8) + for idx in range(num): - with open("work_gbio2/gbio2_%02d.v" % idx, "w") as f: + with open(working_dir + "/gbio2_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( @@ -69,7 +75,7 @@ for idx in range(num): """ % ( glbs[0], glbs[1], glbs[1], glbs[2], glbs[3] ), file=f) - with open("work_gbio2/gbio2_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/gbio2_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) g = np.random.permutation(gpins) for i in range(w): @@ -81,9 +87,5 @@ for idx in range(num): print("set_io %s %s" % (n, p[4*w+i]), file=f) print("set_io q %s" % (p[-1]), file=f) -with open("work_gbio2/Makefile", "w") as f: - print("all: %s" % " ".join(["gbio2_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("gbio2_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh gbio2_%02d > gbio2_%02d.log 2>&1 && rm -rf gbio2_%02d.tmp || tail gbio2_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "gbio2") diff --git a/icefuzz/make_io.py b/icefuzz/make_io.py index 9fe5bb0..7e931f6 100644 --- a/icefuzz/make_io.py +++ b/icefuzz/make_io.py @@ -4,14 +4,17 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_io") -os.mkdir("work_io") +device_class = os.getenv("ICEDEVICE") -if os.getenv('ICE384PINS'): w = 3 -else: w = 4 +working_dir = "work_%s_io" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +w = num_iobanks for idx in range(num): - with open("work_io/io_%02d.v" % idx, "w") as f: + with open(working_dir + "/io_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( @@ -49,15 +52,11 @@ for idx in range(num): np.random.choice(["0000", "0110", "1010", "1110", "0101", "1001", "1101", "0100", "1000", "1100", "0111", "1111"]), np.random.choice(["00", "01", "10", "11"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"]), w-1 ), file=f) - with open("work_io/io_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/io_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for k in ["pin", "latch_in", "clk_en", "clk_in", "clk_out", "oen", "dout_0", "dout_1", "din_0", "din_1"]: for i in range(w): print("set_io %s[%d] %s" % (k, i, p.pop()), file=f) -with open("work_io/Makefile", "w") as f: - print("all: %s" % " ".join(["io_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("io_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh io_%02d > io_%02d.log 2>&1 && rm -rf io_%02d.tmp || tail io_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "io") diff --git a/icefuzz/make_iopack.py b/icefuzz/make_iopack.py index bc13416..e062004 100644 --- a/icefuzz/make_iopack.py +++ b/icefuzz/make_iopack.py @@ -10,8 +10,12 @@ num_xor = 8 num_luts = 8 num_outputs_range = (5, 20) -os.system("rm -rf work_iopack") -os.mkdir("work_iopack") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_iopack" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) def get_pin_directions(): pindirs = ["i" for i in range(len(pins))] @@ -32,7 +36,7 @@ def get_nearby_inputs(p, n, r): return [choice(ipins) for i in range(n)] for idx in range(num): - with open("work_iopack/iopack_%02d.v" % idx, "w") as f: + with open(working_dir + "/iopack_%02d.v" % idx, "w") as f: pindirs = get_pin_directions() print("module top(%s);" % ", ".join(["%sput p%d" % ("in" if pindirs[i] == "i" else "out", i) for i in range(len(pins))]), file=f) for outp in range(len(pins)): @@ -45,13 +49,9 @@ for idx in range(num): xor_nets.add("%sp%d_in%d" % (choice(["~", ""]), outp, i)) print(" assign p%d = ^{%s};" % (outp, ", ".join(sorted(xor_nets))), file=f) print("endmodule", file=f) - with open("work_iopack/iopack_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/iopack_%02d.pcf" % idx, "w") as f: for i in range(len(pins)): print("set_io p%d %s" % (i, pins[i]), file=f) -with open("work_iopack/Makefile", "w") as f: - print("all: %s" % " ".join(["iopack_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("iopack_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh iopack_%02d > iopack_%02d.log 2>&1 && rm -rf iopack_%02d.tmp || tail iopack_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "iopack") diff --git a/icefuzz/make_logic.py b/icefuzz/make_logic.py index 0d45a03..9a83b21 100644 --- a/icefuzz/make_logic.py +++ b/icefuzz/make_logic.py @@ -4,33 +4,29 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_logic") -os.mkdir("work_logic") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_logic" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) def random_op(): return np.random.choice(["+", "-", "^", "&", "|", "&~", "|~"]) for idx in range(num): - with open("work_logic/logic_%02d.v" % idx, "w") as f: - if os.getenv('ICE384PINS'): - print("module top(input [5:0] a, b, c, d, output [5:0] y);", file=f) - else: - print("module top(input [15:0] a, b, c, d, output [15:0] y);", file=f) + bus_width = len(pins) // 5 + with open(working_dir + "/logic_%02d.v" % idx, "w") as f: + print("module top(input [%d:0] a, b, c, d, output [%d:0] y);" % (bus_width, bus_width), file=f) print(" assign y = (a %s b) %s (c %s d);" % (random_op(), random_op(), random_op()), file=f) print("endmodule", file=f) - with open("work_logic/logic_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/logic_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) - r = 6 if os.getenv('ICE384PINS') else 16 - for i in range(r): + for i in range(bus_width): print("set_io a[%d] %s" % (i, p[i]), file=f) - print("set_io b[%d] %s" % (i, p[i+r]), file=f) - print("set_io c[%d] %s" % (i, p[i+r*2]), file=f) - print("set_io d[%d] %s" % (i, p[i+r*3]), file=f) - print("set_io y[%d] %s" % (i, p[i+r*4]), file=f) - -with open("work_logic/Makefile", "w") as f: - print("all: %s" % " ".join(["logic_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("logic_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh logic_%02d > logic_%02d.log 2>&1 && rm -rf logic_%02d.tmp || tail logic_%02d.log" % (i, i, i, i), file=f) + print("set_io b[%d] %s" % (i, p[i+bus_width]), file=f) + print("set_io c[%d] %s" % (i, p[i+bus_width*2]), file=f) + print("set_io d[%d] %s" % (i, p[i+bus_width*3]), file=f) + print("set_io y[%d] %s" % (i, p[i+bus_width*4]), file=f) +output_makefile(working_dir, "logic") diff --git a/icefuzz/make_mem.py b/icefuzz/make_mem.py index ab38849..0fe5aa4 100644 --- a/icefuzz/make_mem.py +++ b/icefuzz/make_mem.py @@ -4,11 +4,15 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_mem") -os.mkdir("work_mem") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_mem" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_mem/mem_%02d.v" % idx, "w") as f: + with open(working_dir + "/mem_%02d.v" % idx, "w") as f: print(""" module top(input clk, i0, i1, i2, i3, output reg o0, o1, o2, o3, o4); reg [9:0] raddr, waddr, rdata, wdata; @@ -27,14 +31,11 @@ for idx in range(num): end endmodule """, file=f) - with open("work_mem/mem_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/mem_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for port in [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3", "o4" ]: print("set_io %s %s" % (port, p.pop()), file=f) -with open("work_mem/Makefile", "w") as f: - print("all: %s" % " ".join(["mem_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("mem_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh mem_%02d > mem_%02d.log 2>&1 && rm -rf mem_%02d.tmp || tail mem_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "mem") diff --git a/icefuzz/make_mesh.py b/icefuzz/make_mesh.py index a2a7d55..2b50bdf 100644 --- a/icefuzz/make_mesh.py +++ b/icefuzz/make_mesh.py @@ -4,29 +4,30 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_mesh") -os.mkdir("work_mesh") + +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_mesh" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +# This test maps a random set of pins to another random set of outputs. + +device_class = os.getenv("ICEDEVICE") for idx in range(num): - with open("work_mesh/mesh_%02d.v" % idx, "w") as f: - if os.getenv('ICE384PINS'): - print("module top(input [13:0] a, output [13:0] y);", file=f) - else: - print("module top(input [39:0] a, output [39:0] y);", file=f) + io_count = len(pins) // 2 + with open(working_dir + "/mesh_%02d.v" % idx, "w") as f: + print("module top(input [%d:0] a, output [%d:0] y);" % (io_count, io_count), file=f) print(" assign y = a;", file=f) print("endmodule", file=f) - with open("work_mesh/mesh_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/mesh_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) - if os.getenv('ICE384PINS'): r = 14 - else: r = 40 - for i in range(r): + for i in range(io_count): print("set_io a[%d] %s" % (i, p[i]), file=f) - for i in range(r): - print("set_io y[%d] %s" % (i, p[r+i]), file=f) + for i in range(io_count): + print("set_io y[%d] %s" % (i, p[io_count+i]), file=f) -with open("work_mesh/Makefile", "w") as f: - print("all: %s" % " ".join(["mesh_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("mesh_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh mesh_%02d > mesh_%02d.log 2>&1 && rm -rf mesh_%02d.tmp || tail mesh_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "mesh") diff --git a/icefuzz/make_pin2pin.py b/icefuzz/make_pin2pin.py index 1dfe60e..c2e13e6 100644 --- a/icefuzz/make_pin2pin.py +++ b/icefuzz/make_pin2pin.py @@ -4,22 +4,23 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_pin2pin") -os.mkdir("work_pin2pin") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_pin2pin" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_pin2pin/pin2pin_%02d.v" % idx, "w") as f: + with open(working_dir + "/pin2pin_%02d.v" % idx, "w") as f: print("module top(input a, output y);", file=f) print(" assign y = a;", file=f) print("endmodule", file=f) - with open("work_pin2pin/pin2pin_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/pin2pin_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) print("set_io a %s" % p[0], file=f) print("set_io y %s" % p[1], file=f) -with open("work_pin2pin/Makefile", "w") as f: - print("all: %s" % " ".join(["pin2pin_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("pin2pin_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh pin2pin_%02d > pin2pin_%02d.log 2>&1 && rm -rf pin2pin_%02d.tmp || tail pin2pin_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "pin2pin") diff --git a/icefuzz/make_pll.py b/icefuzz/make_pll.py index d438b5e..757a222 100644 --- a/icefuzz/make_pll.py +++ b/icefuzz/make_pll.py @@ -11,9 +11,14 @@ def randbin(n): for p in gpins: if p in pins: pins.remove(p) + -os.system("rm -rf work_pll") -os.mkdir("work_pll") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_pll" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): pin_names = list() @@ -110,20 +115,17 @@ for idx in range(num): pll_inst.append("defparam uut.TEST_MODE = 1'b0;") - with open("work_pll/pll_%02d.v" % idx, "w") as f: + with open(working_dir + "/pll_%02d.v" % idx, "w") as f: print("module top(%s);" % ", ".join(pin_names), file=f) print("\n".join(vlog_body), file=f) print("\n".join(pll_inst), file=f) print("endmodule", file=f) - with open("work_pll/pll_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/pll_%02d.pcf" % idx, "w") as f: for pll_pin, package_pin in zip(pin_names, list(permutation(pins))[0:len(pin_names)]): if pll_pin == "packagepin": package_pin = "49" print("set_io %s %s" % (pll_pin, package_pin), file=f) -with open("work_pll/Makefile", "w") as f: - print("all: %s" % " ".join(["pll_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("pll_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh pll_%02d > pll_%02d.log 2>&1 && rm -rf pll_%02d.tmp || tail pll_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "pll") diff --git a/icefuzz/make_prim.py b/icefuzz/make_prim.py index 8ced57e..b96a100 100644 --- a/icefuzz/make_prim.py +++ b/icefuzz/make_prim.py @@ -4,13 +4,17 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_prim") -os.mkdir("work_prim") +device_class = os.getenv("ICEDEVICE") -w = 10 if os.getenv('ICE384PINS') else 24 +working_dir = "work_%s_prim" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +w = len(pins) // 4 for idx in range(num): - with open("work_prim/prim_%02d.v" % idx, "w") as f: + with open(working_dir + "/prim_%02d.v" % idx, "w") as f: clkedge = np.random.choice(["pos", "neg"]) print("module top(input clk, input [%s:0] a, b, output reg x, output reg [%s:0] y);""" % ( w-1, w-1 ), file=f) print(" reg [%s:0] aa, bb;""" % ( w-1 ), file=f) @@ -25,7 +29,7 @@ for idx in range(num): else: print(" always @(%sedge clk) y <= %s%s;" % (clkedge, np.random.choice(["~", "-", ""]), np.random.choice(["a", "b"])), file=f) print("endmodule", file=f) - with open("work_prim/prim_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/prim_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) if np.random.choice([True, False]): for i in range(w): @@ -43,9 +47,5 @@ for idx in range(num): if np.random.choice([True, False]): print("set_io clk %s" % p[3*w+2], file=f) -with open("work_prim/Makefile", "w") as f: - print("all: %s" % " ".join(["prim_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("prim_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh prim_%02d > prim_%02d.log 2>&1 && rm -rf prim_%02d.tmp || tail prim_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "prim") diff --git a/icefuzz/make_ram40.py b/icefuzz/make_ram40.py index a97d0bc..f4acb4e 100644 --- a/icefuzz/make_ram40.py +++ b/icefuzz/make_ram40.py @@ -4,17 +4,21 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_ram40") -os.mkdir("work_ram40") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_ram40" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_ram40/ram40_%02d.v" % idx, "w") as f: - glbs = ["glb[%d]" % i for i in range(np.random.randint(9))] + with open(working_dir + "/ram40_%02d.v" % idx, "w") as f: + glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)] glbs_choice = ["wa", "ra", "msk", "wd", "we", "wce", "wc", "re", "rce", "rc"] print(""" module top ( input [%d:0] glb_pins, - input [59:0] in_pins, + input [%d:0] in_pins, output [15:0] out_pins ); wire [%d:0] glb, glb_pins; @@ -22,7 +26,7 @@ for idx in range(num): .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins), .GLOBAL_BUFFER_OUTPUT(glb) ); - """ % (len(glbs)-1, len(glbs)-1, len(glbs)-1), file=f) + """ % (len(glbs)-1, len(pins) - 16 - 1, len(glbs)-1, len(glbs)-1), file=f) bits = ["in_pins[%d]" % i for i in range(60)] bits = list(np.random.permutation(bits)) for i in range(num_ramb40): @@ -96,16 +100,12 @@ for idx in range(num): bits[k] = "rdata_%d[%d] ^ %s" % (i, k, bits[k]) print("assign out_pins = rdata_%d;" % i, file=f) print("endmodule", file=f) - with open("work_ram40/ram40_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/ram40_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) - for i in range(60): + for i in range(len(pins) - 16): print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) for i in range(16): print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) -with open("work_ram40/Makefile", "w") as f: - print("all: %s" % " ".join(["ram40_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("ram40_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh ram40_%02d > ram40_%02d.log 2>&1 && rm -rf ram40_%02d.tmp || tail ram40_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "ram40") diff --git a/icefuzz/tests/io_latched_5k.sh b/icefuzz/tests/io_latched_5k.sh new file mode 100644 index 0000000..a43c77f --- /dev/null +++ b/icefuzz/tests/io_latched_5k.sh @@ -0,0 +1,27 @@ +#!/bin/bash + +set -ex + +mkdir -p io_latched_5k.work +cd io_latched_5k.work + +pins=" +2 3 4 6 9 10 11 12 +13 18 19 20 21 23 +25 26 27 28 31 32 34 35 36 +37 38 42 43 44 45 46 47 48 +" +pins="$( echo $pins )" + +for pin in $pins ; do + pf="io_latched_$pin" + cp ../io_latched.v ${pf}.v + read pin_latch pin_data < <( echo $pins | tr ' ' '\n' | grep -v $pin | sort -R; ) + { + echo "set_io pin $pin" + echo "set_io latch_in $pin_latch" + echo "set_io data_out $pin_data" + } > ${pf}.pcf + ICEDEV=up5k-sg48 bash ../../icecube.sh ${pf}.v + ../../../icebox/icebox_vlog.py -SP ${pf}.psb ${pf}.asc > ${pf}.ve +done diff --git a/icepack/icepack.cc b/icepack/icepack.cc index 3230d06..4374452 100644 --- a/icepack/icepack.cc +++ b/icepack/icepack.cc @@ -249,7 +249,7 @@ void FpgaConfig::read_bits(std::istream &ifs) { // one command byte. the lower 4 bits of the command byte specify // the length of the command payload. - + uint8_t command = read_byte(ifs, crc_value, file_offset); uint32_t payload = 0; @@ -396,9 +396,11 @@ void FpgaConfig::read_bits(std::istream &ifs) this->device = "1k"; else if (this->cram_width == 872 && this->cram_height == 272) this->device = "8k"; + else if (this->cram_width == 692 && this->cram_height == 336) + this->device = "5k"; else error("Failed to detect chip type.\n"); - + info("Chip type is '%s'.\n", this->device.c_str()); } @@ -621,6 +623,12 @@ void FpgaConfig::read_ascii(std::istream &ifs) this->bram_width = 128; this->bram_height = 2 * 128; } else + if (this->device == "5k") { + this->cram_width = 692; + this->cram_height = 336; + this->bram_width = 160; + this->bram_height = 2 * 128; + } else error("Unsupported chip type '%s'.\n", this->device.c_str()); this->cram.resize(4); @@ -725,10 +733,10 @@ void FpgaConfig::read_ascii(std::istream &ifs) continue; } - + if (command == ".sym") continue; - + if (command.substr(0, 1) == ".") error("Unknown statement: %s\n", command.c_str()); error("Unexpected data line: %s\n", line.c_str()); @@ -765,7 +773,7 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const { CramIndexConverter cic(this, x, y); - if (cic.tile_type == "corner") + if (cic.tile_type == "corner" || cic.tile_type == "unsupported") continue; ofs << stringf(".%s_tile %d %d\n", cic.tile_type.c_str(), x, y); @@ -775,6 +783,12 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const int cram_bank, cram_x, cram_y; cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); tile_bits.insert(tile_bit_t(cram_bank, cram_x, cram_y)); + if (cram_x > int(this->cram[cram_bank].size())) { + error("cram_x %d (bit %d, %d) larger than bank size %lu\n", cram_x, bit_x, bit_y, this->cram[cram_bank].size()); + } + if (cram_y > int(this->cram[cram_bank][cram_x].size())) { + error("cram_y %d larger than bank size %lu\n", cram_y, this->cram[cram_bank][cram_x].size()); + } ofs << (this->cram[cram_bank][cram_x][cram_y] ? '1' : '0'); } ofs << '\n'; @@ -791,6 +805,14 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const for (int i = 0; i < 4; i++) { int bram_bank, bram_x, bram_y; bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y); + if (bram_x >= int(this->bram[bram_bank].size())) { + error("%d %d bram_x %d higher than loaded bram size %lu\n",bit_x+i, bit_y, bram_x, this->bram[bram_bank].size()); + break; + } + if (bram_y >= int(this->bram[bram_bank][bram_x].size())) { + error("bram_y %d higher than loaded bram size %lu\n", bram_y, this->bram[bram_bank][bram_x].size()); + break; + } if (this->bram[bram_bank][bram_x][bram_y]) value += 1 << i; } @@ -825,8 +847,47 @@ void FpgaConfig::write_cram_pbm(std::ostream &ofs, int bank_num) const debug("## %s\n", __PRETTY_FUNCTION__); info("Writing cram pbm file..\n"); - ofs << "P1\n"; + ofs << "P3\n"; ofs << stringf("%d %d\n", 2*this->cram_width, 2*this->cram_height); + ofs << "255\n"; + uint32_t tile_type[4][this->cram_width][this->cram_height]; + for (int y = 0; y <= this->chip_height()+1; y++) + for (int x = 0; x <= this->chip_width()+1; x++) + { + CramIndexConverter cic(this, x, y); + + uint32_t color = 0x000000; + if (cic.tile_type == "io") { + color = 0x00aa00; + } else if (cic.tile_type == "logic") { + if ((x + y) % 2 == 0) { + color = 0x0000ff; + } else { + color = 0x0000aa; + } + if (x == 12 && y == 25) { + color = 0xaa00aa; + } + if (x == 12 && y == 24) { + color = 0x888888; + } + } else if (cic.tile_type == "ramt") { + color = 0xff0000; + } else if (cic.tile_type == "ramb") { + color = 0xaa0000; + } else if (cic.tile_type == "unsupported") { + color = 0x333333; + } else { + info("%s\n", cic.tile_type.c_str()); + } + + for (int bit_y = 0; bit_y < 16; bit_y++) + for (int bit_x = 0; bit_x < cic.tile_width; bit_x++) { + int cram_bank, cram_x, cram_y; + cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); + tile_type[cram_bank][cram_x][cram_y] = color; + } + } for (int y = 2*this->cram_height-1; y >= 0; y--) { for (int x = 0; x < 2*this->cram_width; x++) { int bank = 0, bank_x = x, bank_y = y; @@ -835,9 +896,16 @@ void FpgaConfig::write_cram_pbm(std::ostream &ofs, int bank_num) const if (bank_y >= this->cram_height) bank |= 2, bank_y = 2*this->cram_height - bank_y - 1; if (bank_num >= 0 && bank != bank_num) - ofs << " 0"; - else - ofs << (this->cram[bank][bank_x][bank_y] ? " 1" : " 0"); + ofs << " 255 255 255"; + else if (this->cram[bank][bank_x][bank_y]) { + ofs << " 255 255 255"; + } else { + uint32_t color = tile_type[bank][bank_x][bank_y]; + uint8_t r = color >> 16; + uint8_t g = color >> 8; + uint8_t b = color & 0xff; + ofs << stringf(" %d %d %d", r, g, b); + } } ofs << '\n'; } @@ -857,6 +925,7 @@ void FpgaConfig::write_bram_pbm(std::ostream &ofs, int bank_num) const bank |= 1, bank_x = 2*this->bram_width - bank_x - 1; if (bank_y >= this->bram_height) bank |= 2, bank_y = 2*this->bram_height - bank_y - 1; + info("%d %d %d\n", bank, bank_x, bank_y); if (bank_num >= 0 && bank != bank_num) ofs << " 0"; else @@ -870,6 +939,7 @@ int FpgaConfig::chip_width() const { if (this->device == "384") return 6; if (this->device == "1k") return 12; + if (this->device == "5k") return 24; if (this->device == "8k") return 32; panic("Unknown chip type '%s'.\n", this->device.c_str()); } @@ -878,6 +948,7 @@ int FpgaConfig::chip_height() const { if (this->device == "384") return 8; if (this->device == "1k") return 16; + if (this->device == "5k") return 30; if (this->device == "8k") return 32; panic("Unknown chip type '%s'.\n", this->device.c_str()); } @@ -886,6 +957,8 @@ vector<int> FpgaConfig::chip_cols() const { if (this->device == "384") return vector<int>({18, 54, 54, 54, 54}); if (this->device == "1k") return vector<int>({18, 54, 54, 42, 54, 54, 54}); + // Its IPConnect or Mutiplier block, five logic, ram, six logic. + if (this->device == "5k") return vector<int>({54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54}); if (this->device == "8k") return vector<int>({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54}); panic("Unknown chip type '%s'.\n", this->device.c_str()); } @@ -893,6 +966,8 @@ vector<int> FpgaConfig::chip_cols() const string FpgaConfig::tile_type(int x, int y) const { if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner"; + // The sides on the 5k devices are unsupported tile types. + if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) return "unsupported"; if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io"; if (this->device == "384") return "logic"; @@ -902,6 +977,11 @@ string FpgaConfig::tile_type(int x, int y) const return "logic"; } + if (this->device == "5k") { + if (x == 6 || x == 19) return y % 2 == 1 ? "ramb" : "ramt"; + return "logic"; + } + if (this->device == "8k") { if (x == 8 || x == 25) return y % 2 == 1 ? "ramb" : "ramt"; return "logic"; @@ -912,11 +992,12 @@ string FpgaConfig::tile_type(int x, int y) const int FpgaConfig::tile_width(const string &type) const { - if (type == "corner") return 0; - if (type == "logic") return 54; - if (type == "ramb") return 42; - if (type == "ramt") return 42; - if (type == "io") return 18; + if (type == "corner") return 0; + if (type == "logic") return 54; + if (type == "ramb") return 42; + if (type == "ramt") return 42; + if (type == "io") return 18; + if (type == "unsupported") return 76; panic("Unknown tile type '%s'.\n", type.c_str()); } @@ -951,7 +1032,7 @@ void FpgaConfig::cram_checkerboard(int m) { if ((x+y) % 2 == m) continue; - + CramIndexConverter cic(this, x, y); for (int bit_y = 0; bit_y < 16; bit_y++) @@ -979,7 +1060,11 @@ CramIndexConverter::CramIndexConverter(const FpgaConfig *fpga, int tile_x, int t this->left_right_io = this->tile_x == 0 || this->tile_x == chip_width+1; this->right_half = this->tile_x > chip_width / 2; - this->top_half = this->tile_y > chip_height / 2; + if (this->fpga->device == "5k") { + this->top_half = this->tile_y > (chip_height * 2 / 3); + } else { + this->top_half = this->tile_y > chip_height / 2; + } this->bank_num = 0; if (this->top_half) this->bank_num |= 1; @@ -1031,7 +1116,7 @@ void CramIndexConverter::get_cram_index(int bit_x, int bit_y, int &cram_bank, in cram_x = bank_xoff + column_width - 1 - bit_x; else cram_x = bank_xoff + bit_x; - + if (top_half) cram_y = bank_yoff + (15 - bit_y); else @@ -1050,12 +1135,28 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t bool right_half = this->tile_x > chip_width / 2; bool top_half = this->tile_y > chip_height / 2; + // The UltraPlus 5k line is special because the top quarter of the chip is + // used for SRAM instead of logic. Therefore the bitstream for the top two + // quadrants are half the height of the bottom. + if (this->fpga->device == "5k") { + top_half = this->tile_y > (chip_height / 3); + } this->bank_num = 0; - if (top_half) this->bank_num |= 1; + int y_offset = this->tile_y - 1; + if (this->fpga->device == "5k") { + if (!top_half) { + this->bank_num |= 1; + } else { + y_offset = this->tile_y - (chip_height / 3); + } + } else if (top_half) { + this->bank_num |= 1; + y_offset = this->tile_y - chip_height / 2; + } if (right_half) this->bank_num |= 2; - this->bank_off = 16 * ((top_half ? this->tile_y - chip_height / 2 : this->tile_y - 1) / 2); + this->bank_off = 16 * (y_offset / 2); } void BramIndexConverter::get_bram_index(int bit_x, int bit_y, int &bram_bank, int &bram_x, int &bram_y) const @@ -1192,9 +1293,13 @@ int main(int argc, char **argv) fpga_config.cram_checkerboard(checkerboard_m); } + info("netpbm\n"); + if (netpbm_fill_tiles) fpga_config.cram_fill_tiles(); + info("fill done\n"); + if (netpbm_mode) { if (netpbm_bram) fpga_config.write_bram_pbm(*osp, netpbm_banknum); @@ -1205,4 +1310,3 @@ int main(int argc, char **argv) info("Done.\n"); return 0; } - diff --git a/icepll/icepll.cc b/icepll/icepll.cc index 744b9b1..6b6cedb 100644 --- a/icepll/icepll.cc +++ b/icepll/icepll.cc @@ -108,14 +108,10 @@ int main(int argc, char **argv) int best_divf = 0; int best_divq = 0; - //The documentation in the iCE40 PLL Usage Guide incorrectly lists the - //maximum value of DIVF as 63, when it is only limited to 63 when using - //feedback modes other that SIMPLE. - int divf_max = 63; - if(simple_feedback) - { - divf_max = 127; - } + // The documentation in the iCE40 PLL Usage Guide incorrectly lists the + // maximum value of DIVF as 63, when it is only limited to 63 when using + // feedback modes other that SIMPLE. + int divf_max = simple_feedback ? 127 : 63; if (f_pllin < 10 || f_pllin > 133) { fprintf(stderr, "Error: PLL input frequency %.3f MHz is outside range 10 MHz - 133 MHz!\n", f_pllin); |