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| author | Sylvain Munaut <tnt@246tNt.com> | 2020-06-02 10:33:21 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-06-03 10:45:31 +0200 |
| commit | ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0 (patch) | |
| tree | 58286dd485e9500c4e12e9a995aaf265555d8c34 | |
| parent | cd2610e0fa1c6a90e8e4e4cfe06db1b474e752bb (diff) | |
| download | icestorm-ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0.tar.gz icestorm-ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0.tar.bz2 icestorm-ce1d811d21fa40acbe7a772b3b53dafe3a7dfae0.zip | |
icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k
This allows selection of the div-by-5 mode of the PLL.
This bit can't be fuzzed because it's not supported by the lattice
tools at all ...
This only works for sure on the UP5k.
I tested HX8k and it didn't support it, so I'm only adding this on
the known working FPGA.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| -rw-r--r-- | icebox/icebox.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/icebox/icebox.py b/icebox/icebox.py index 0422f13..ab83fd0 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -1954,7 +1954,8 @@ pllinfo_db = { "PLLOUT_SELECT_B_1": (12, 31, "PLLCONFIG_3"), # Numeric Parameters - "SHIFTREG_DIV_MODE": (12, 31, "PLLCONFIG_4"), + "SHIFTREG_DIV_MODE_0": (12, 31, "PLLCONFIG_4"), + "SHIFTREG_DIV_MODE_1": (14, 31, "PLLCONFIG_6"), "FDA_FEEDBACK_0": (12, 31, "PLLCONFIG_9"), "FDA_FEEDBACK_1": (13, 31, "PLLCONFIG_1"), "FDA_FEEDBACK_2": (13, 31, "PLLCONFIG_2"), |