Fix whitespace and a couple of typos

11 files changed, 14 insertions, 14 deletions

diff --git a/examples/up5k_mac16/mac16.pcf b/examples/up5k_mac16/mac16.pcf
index 24b9b45..5e21181 100644
--- a/examples/up5k_mac16/mac16.pcf
+++ b/examples/up5k_mac16/mac16.pcf
@@ -1,4 +1,4 @@
 set_io clk 44
 set_io rstn 27
 set_io LED1 12
-set_io LED2 13
\ No newline at end of file
+set_io LED2 13
diff --git a/examples/up5k_mac16/mac16.v b/examples/up5k_mac16/mac16.v
index 73740e3..0323fc3 100644
--- a/examples/up5k_mac16/mac16.v
+++ b/examples/up5k_mac16/mac16.v
@@ -68,4 +68,4 @@ assign LED2 = 1'b0;
 
 
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/examples/up5k_rgb/rgb.pcf b/examples/up5k_rgb/rgb.pcf
index cfdb874..0954260 100644
--- a/examples/up5k_rgb/rgb.pcf
+++ b/examples/up5k_rgb/rgb.pcf
@@ -1,3 +1,3 @@
 set_io RGB0 39
 set_io RGB1 40
-set_io RGB2 41
\ No newline at end of file
+set_io RGB2 41
diff --git a/examples/up5k_rgb/rgb.v b/examples/up5k_rgb/rgb.v
index c83b943..81920cb 100644
--- a/examples/up5k_rgb/rgb.v
+++ b/examples/up5k_rgb/rgb.v
@@ -78,4 +78,4 @@ defparam RGBA_DRIVER.RGB1_CURRENT = "0b000011";
 defparam RGBA_DRIVER.RGB2_CURRENT = "0b000011";
 
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/icebox/icebox.py b/icebox/icebox.py
index 6b0dfd8..5e94f31 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -642,7 +642,7 @@ class iceconfig:
                         if s[0] == 0 and s[1] == 0:
                             if direction == "l": s = (0, 1, vert_net)
                             if direction == "b": s = (1, 0, horz_net)
-                            
+
                         if s[0] == self.max_x and s[1] == self.max_y:
                             if direction == "r": s = (self.max_x, self.max_y-1, vert_net)
                             if direction == "t": s = (self.max_x-1, self.max_y, horz_net)
@@ -677,11 +677,11 @@ class iceconfig:
                         if s[0] == 0 and s[1] == self.max_y:
                             if direction == "l": s = (0, self.max_y-1, vert_net)
                             if direction == "t": s = (1, self.max_y, horz_net)
-                            
+
                         if s[0] == self.max_x and s[1] == 0:
                             if direction == "r": s = (self.max_x, 1, vert_net)
                             if direction == "b": s = (self.max_x-1, 0, horz_net)
-                            
+
                 if self.tile_has_net(s[0], s[1], s[2]):
                     neighbours.add((s[0], s[1], s[2]))
 
diff --git a/icefuzz/tests/dsp_cbit/.gitignore b/icefuzz/tests/dsp_cbit/.gitignore
index 83d459d..95ff890 100644
--- a/icefuzz/tests/dsp_cbit/.gitignore
+++ b/icefuzz/tests/dsp_cbit/.gitignore
@@ -1 +1 @@
-work_dsp_cbit/
\ No newline at end of file
+work_dsp_cbit/
diff --git a/icefuzz/tests/rgba_drv_cbit/.gitignore b/icefuzz/tests/rgba_drv_cbit/.gitignore
index 68b6394..a0beeed 100644
--- a/icefuzz/tests/rgba_drv_cbit/.gitignore
+++ b/icefuzz/tests/rgba_drv_cbit/.gitignore
@@ -1 +1 @@
-work_rgba_drv/
\ No newline at end of file
+work_rgba_drv/
diff --git a/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py b/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py
index a7e2006..3d43ba4 100755
--- a/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py
+++ b/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py
@@ -171,4 +171,4 @@ set_io b_led 41
                     dat.write(("\"RGBA_DRV_EN\":").ljust(24) + bit_to_str(rgba_drv_en_bit[device]) + ",\n")
                 print(("\"" + fuzz_bit + "\":").ljust(24) + bit_to_str(new_bits[0]) + ",")
                 dat.write(("\"" + fuzz_bit + "\":").ljust(24) + bit_to_str(new_bits[0]) + ",\n")
-do_fuzz()
\ No newline at end of file
+do_fuzz()
diff --git a/icefuzz/tests/spram/.gitignore b/icefuzz/tests/spram/.gitignore
index c6ebe02..7ce4577 100644
--- a/icefuzz/tests/spram/.gitignore
+++ b/icefuzz/tests/spram/.gitignore
@@ -1 +1 @@
-work_spram/
\ No newline at end of file
+work_spram/
diff --git a/icefuzz/tests/spram/fuzz_spram.py b/icefuzz/tests/spram/fuzz_spram.py
index a92a361..05fd828 100755
--- a/icefuzz/tests/spram/fuzz_spram.py
+++ b/icefuzz/tests/spram/fuzz_spram.py
@@ -171,4 +171,4 @@ with open(device + "_spram_data.txt", "w") as f:
             for cnet in data[net]:
                 cnets.append("(%d, %d, \"%s\")" % cnet)
             print("\t\t%s %s, " % (("\"" + net.replace("[","_").replace("]","") + "\":").ljust(24), " ".join(cnets)), file=f)
-        print("\t},", file=f)
\ No newline at end of file
+        print("\t},", file=f)
diff --git a/icepack/icepack.cc b/icepack/icepack.cc
index fd3050e..b67241f 100644
--- a/icepack/icepack.cc
+++ b/icepack/icepack.cc
@@ -1013,7 +1013,7 @@ vector<int> FpgaConfig::chip_cols() const
 {
 	if (this->device == "384") return vector<int>({18, 54, 54, 54, 54});
 	if (this->device == "1k") return vector<int>({18, 54, 54, 42, 54, 54, 54});
-	// Its ipconect or Mutiplier block, five logic, ram, six logic.
+	// Its IPConnect or Mutiplier block, five logic, ram, six logic.
 	if (this->device == "5k") return vector<int>({54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54});
 	if (this->device == "8k") return vector<int>({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54});
 	panic("Unknown chip type '%s'.\n", this->device.c_str());
@@ -1022,7 +1022,7 @@ vector<int> FpgaConfig::chip_cols() const
 string FpgaConfig::tile_type(int x, int y) const
 {
 	if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner";
-	// The sides on the 5k devices are ipconect or DSP tiles
+	// The sides on the 5k devices are IPConnect or DSP tiles
 	if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) {
 		if( (y == 5) || (y == 10) || (y == 15) || (y == 23)) //check ordering here, tile 23-26 might be reversed
 			return "dsp0";