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| author | Clifford Wolf <clifford@clifford.at> | 2015-11-12 00:47:26 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-11-12 00:47:26 +0100 |
| commit | 39337b7bf9f66fdeec471c5718f1bb1e7548654e (patch) | |
| tree | 1f9a0ce85544cc9e0d5012c0c1a1b1a98fd700f0 /docs | |
| parent | 406c2ad88f46bc5774fad55e90b45bbb02eed187 (diff) | |
| download | icestorm-39337b7bf9f66fdeec471c5718f1bb1e7548654e.tar.gz icestorm-39337b7bf9f66fdeec471c5718f1bb1e7548654e.tar.bz2 icestorm-39337b7bf9f66fdeec471c5718f1bb1e7548654e.zip | |
Webpage updates
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/index.html | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/docs/index.html b/docs/index.html index 54dc489..6e344fb 100644 --- a/docs/index.html +++ b/docs/index.html @@ -14,10 +14,11 @@ <h2>What is Project IceStorm?</h2> <p> -Project IceStorm aims at documenting the bitstream format of Lattice iCE40 -FPGAs and providing simple tools for analyzing and creating bitstream files. -At the moment the focus of the project is on the HX1K-TQ144 and HX8K-CT256 -devices, but most of the information is device-independent. +Project IceStorm aims at reverse engineering and documenting the bitstream +format of Lattice iCE40 FPGAs and providing simple tools for analyzing and +creating bitstream files. At the moment the focus of the project is on the +HX1K-TQ144 and HX8K-CT256 devices, but most of the information is +device-independent. </p> <h2>Why the Lattice iCE40?</h2> @@ -37,8 +38,15 @@ for all kinds of projects. <h2>What is the Status of the Project?</h2> <p> -We have enough bits mapped that we can create a functional Verilog model for almost all -bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256. +We have enough bits mapped that we can create a functional Verilog model for +almost all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 +and the iCE40 HX8K-CT256, and can create bitstreams for this parts using our +own tool-chain. +</p> + +<p> +The next milestones for the project are timing analysis and support for more +parts from the iCE40 family. </p> <h2>What is the Status of the Fully Open Source iCE40 Flow?</h2> @@ -355,6 +363,7 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int <li><a href="http://www.excamera.com/sphinx/article-j1a-swapforth.html">J1a SwapForth built with IceStorm</a> <li><a href="https://hackaday.io/project/6636-iced-an-arduino-style-board-with-ice-fpga">ICEd = an Arduino Style Board, with ICE FPGA</a> <li><a href="https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki">A Spanish FPGA Tutorial using IceStorm</a> +<li><a href="https://hackaday.io/project/7982-cat-board">CAT Board</a> </ul> <hr> |