Imported full dev sources

author: Clifford Wolf <clifford@clifford.at> 2015-07-18 13:10:40 +0200
committer: Clifford Wolf <clifford@clifford.at> 2015-07-18 13:10:40 +0200
commit: 48154cb6f452d3bdb4da36cc267b4b6c45588dc9 (patch)
tree: 3ec3be9ef7e8db1fb7c764ed8202e0215a8eb7c7 /docs
parent: 13e63e6b65e044e348356731b55610d02cb308b9 (diff)
download: icestorm-48154cb6f452d3bdb4da36cc267b4b6c45588dc9.tar.gz
icestorm-48154cb6f452d3bdb4da36cc267b4b6c45588dc9.tar.bz2
icestorm-48154cb6f452d3bdb4da36cc267b4b6c45588dc9.zip
11 files changed, 9047 insertions, 0 deletions
diff --git a/docs/checkerboard.png b/docs/checkerboard.png
new file mode 100644
index 0000000..72478de
--- /dev/null
+++ b/docs/checkerboard.png
diff --git a/docs/checkerboard.sh b/docs/checkerboard.sh
new file mode 100644
index 0000000..dd045ee
--- /dev/null
+++ b/docs/checkerboard.sh
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+#!/bin/bash
+
+pbm_to_ppm() {
+	read line; echo "P3"
+	read line; echo "$line"; echo "2"
+	sed "s,0,x,g; s,1,y,g; s,x,$1,g; s,y,$2,g;"
+
+}
+
+../icepack/icepack -uc  -B0 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 0 2" > checkerboard_0.ppm
+../icepack/icepack -ucc -B0 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 0" > checkerboard_1.ppm
+../icepack/icepack -uc  -B1 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 1" > checkerboard_2.ppm
+../icepack/icepack -ucc -B1 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 0 0" > checkerboard_3.ppm
+../icepack/icepack -uc  -B2 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 0 1" > checkerboard_4.ppm
+../icepack/icepack -ucc -B2 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 1 0" > checkerboard_5.ppm
+../icepack/icepack -uc  -B3 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 1 1" > checkerboard_6.ppm
+../icepack/icepack -ucc -B3 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 0" > checkerboard_7.ppm
+
+convert -evaluate-sequence add checkerboard_[01234567].ppm checkerboard.png
+rm -f checkerboard_[01234567].ppm
+
diff --git a/docs/colbuf.svg b/docs/colbuf.svg
new file mode 100644
index 0000000..e903e19
--- /dev/null
+++ b/docs/colbuf.svg
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diff --git a/docs/format.html b/docs/format.html
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--- /dev/null
+++ b/docs/format.html
@@ -0,0 +1,151 @@
+<title>Project IceStorm &ndash; Bitstream File Format Documentation</title>
+<h1>Project IceStorm &ndash; Bitstream File Format Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>General Description of the File Format</h2>
+
+<p>
+The bitstream file starts with the bytes 0xFF 0x00, followed by a sequence of
+zero-terminated comment strings, followed by 0x00 0xFF. However, there seems to be
+a bug in the Lattice "bitstream" tool that moves the terminating 0x00 0xFF a few
+bytes into the comment string in some cases.
+</p>
+
+<p>
+After the comment sections the token 0x7EAA997E (MSB first) starts the actual
+bit stream. The bitstream consists of one-byte commands, followed by a payload
+word, followed by an optional block of data. The MSB nibble of the command byte
+is the command opcode, the LSB nibble is the length of the command payload in
+bytes. The commands that do not require a payload are using the opcode 0, with
+the command encoded in the payload field. Note that this "payload" in this
+context refers to a single integer argument, not the blocks of data that
+follows the command in case of the CRAM and BRAM commands.
+</p>
+
+<p>
+The following commands are known:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Opcode</th><th>Description</th></tr>
+<tr><td>0</td><td>payload=0: CRAM Data<br/>
+                  payload=3: BRAM Data<br/>
+		  payload=5: Reset CRC<br/>
+		  payload=6: Wakeup</td></tr>
+<tr><td>1</td><td>Set bank number</td></tr>
+<tr><td>2</td><td>CRC check</td></tr>
+<tr><td>5</td><td>Set internal oscillator frequency range<br/>
+                  payload=0: low<br/>
+                  payload=1: medium<br/>
+                  payload=2: high</td></tr>
+<tr><td>6</td><td>Set bank width</td></tr>
+<tr><td>7</td><td>Set bank height</td></tr>
+<tr><td>8</td><td>Set bank offset</td></tr>
+<tr><td>9</td><td>payload=0: Disable warm boot<br/>
+                  payload=32: Enable warm boot</td></tr>
+</table>
+</p>
+
+<p>
+Use <tt>iceunpack -vv</tt> to display the commands as they are interpreted by the tool.
+</p>
+
+<p>
+Note: The format itself seems to be very flexible. At the moment it is unclear what the FPGA
+devices will do when presented with a bitstream that use the commands in a different way
+than the bitstreams generated by the lattice tools.
+</p>
+
+<h2>Writing SRAM content</h2>
+
+<p>
+Most bytes in the bitstream are SRAM data bytes that should be written to the various SRAM banks
+in the FPGA. The following sequence is used to program an SRAM cell:
+</p>
+
+<p><ul>
+<li>Set bank width (opcode 6)</li>
+<li>Set bank height (opcode 7)</li>
+<li>Set bank offset (opcode 8)</li>
+<li>Set bank number (opcode 1)</li>
+<li>CRAM or BRAM Data Command</li>
+<li>(width * height / 8) data bytes</li>
+<li>two zero bytes</li>
+</ul></p>
+
+<p>
+The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can
+be written in smaller junks. In this case height parameter may be smaller and the offset parameter
+reflects the vertical start position.
+</p>
+
+<p>
+There are four CRAM and four BRAM banks in an iCE40 FPGA. The different devices from the family
+use different widths and heights, but the same number of banks.
+</p>
+
+<p>
+The CRAM banks hold the configuration bits for the FPGA fabric and hard IP blocks, the BRAM
+corresponds to the contents of the block ram resources.
+</p>
+
+<p>
+The ordering of the data bits is in MSB first row-major order.
+</p>
+
+<h2>Organization of the CRAM</h2>
+
+<p><a href="checkerboard.png"><img style="float:right; padding:1em; padding-top:0" height="200" src="checkerboard.png" border="0"></a></p>
+
+<p>
+The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant.
+The address 0 is always the corner of the quadrant, i.e. in one quadrant the bit addresses increase with the tile x/y
+coordinates, in another they increase with the tile x coordinate but decrease with the tile y coordinate, and so on.
+</p>
+
+<p>
+For an iCE40 1k device, that has 12 x 16 tiles (not counting the io tiles), the CRAM bank 0 is the one containing the corner tile (1 1),
+the CRAM bank 1 contains the corner tile (1 16), the CRAM bank 2 contains the corner tile (12 1) and the CRAM bank 3 contains the
+corner tile (12 16). The entire CRAM of such a device is depicted on the right (bank 0 is in the lower left corner in blue/green).
+</p>
+
+<p>
+The checkerboard pattern in the picture visualizes which bits are assoziated
+with which tile. The height of the configuration block is 16 for all tile
+types, but the width is different for each tile type. IO tiles have
+configurations that are 18 bits wide, LOGIC tiles are 54 bits wide, and
+RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM tiles.)
+</p>
+
+<p>
+The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that
+their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit
+positions are vertically permutated as well. The <tt>CramIndexConverter</tt> class in <tt>icepack.cc</tt> encapsulates the calculations
+that are neccessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses.
+</p>
+
+<p>
+The black pixels in the image correspond to CRAM bits that are not assoziated with any IO, LOGIC or RAM tile.
+Some of them are unused, others are used by hard IPs or other global resources. The <tt>iceunpack</tt> tool reports
+such bits, when set, with the "<tt>.extra_bit <i>bank x y</i></tt>" statement in the ASCII output format.
+</p>
+
+<h2>Organization of the BRAM</h2>
+
+<p>
+This part of the documentation has not been written yet.
+</p>
+
+<h2>CRC Check</h2>
+
+<p>
+The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). The "Reset CRC" command sets
+the CRC to 0xFFFF. No zero padding is performed.
+</p>
+
diff --git a/docs/index.html b/docs/index.html
new file mode 100644
index 0000000..dbd8ba6
--- /dev/null
+++ b/docs/index.html
@@ -0,0 +1,321 @@
+<title>Project IceStorm</title>
+<h1>Project IceStorm</h1>
+
+<p>
+<b>2015-05-27:</b> We have a working fully Open Source flow with <a href="http://www.clifford.at/yosys/">Yosys</a> and <a href="https://github.com/cseed/arachne-pnr">Arachne-pnr</a>! Video: <a href="http://youtu.be/yUiNlmvVOq8">http://youtu.be/yUiNlmvVOq8</a><br/>
+<b>2015-04-13:</b> Complete rewrite of IceUnpack, added IcePack, some major documentation updates<br/>
+<b>2015-03-22:</b> First public release and short YouTube video demonstrating our work: <a href="http://youtu.be/u1ZHcSNDQMM">http://youtu.be/u1ZHcSNDQMM</a>
+</p>
+
+<h2>What is Project IceStorm?</h2>
+
+<p>
+Project IceStorm aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+At the moment the focus of the project is on the HX1K-TQ144 device, but
+most of the information is device-independent.
+</p>
+
+<h2>Why the Lattice iCE40?</h2>
+
+<p>
+It has a very minimalistic architecture with a very regular structure. There are not many
+different kinds of tiles or special function units. This makes it both ideal for
+reverse engineering and as a reference platform for general purpose FPGA tool development.
+</p>
+
+<p>
+Also, with the <a href="http://www.latticesemi.com/icestick">iCEstick</a> there is
+a cheap and easy to use development platform available, which makes the part interesting
+for all kinds of projects.
+</p>
+
+<h2>What is the Status of the Project?</h2>
+
+<p>
+We have enough bits mapped that we can create a functional verilog model for almost all 
+bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144, as long as no
+block memories or PLLs are used. (Both are fully documented, but the
+<tt>icebox_vlog.py</tt> script does not create verilog models for them yet.)
+</p>
+
+<p>
+Next on the TODO list: PLLs, Timing Analysis, support for HX8K chips.
+</p>
+
+<h2>What is the Status of the Fully Open Source iCE40 Flow?</h2>
+
+<p>
+Synthesis for iCE40 FPGAs can be done with <a href="http://www.clifford.at/yosys/">Yosys</a>.
+Place-and-route can be done with <a href="https://github.com/cseed/arachne-pnr">arachne-pnr</a>.
+Here is an example script for implementing and programming the <a
+href="https://github.com/cseed/arachne-pnr/tree/master/examples/rot">rot example from
+arachne-pnr</a> (this example targets the iCEstick development board):
+</p>
+
+<pre style="padding-left: 3em">yosys -p "synth_ice40 -blif rot.blif" rot.v
+arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.txt
+icepack rot.txt rot.bin
+iceprog rot.bin</pre>
+
+<h2>Where are the Tools?</h2>
+
+<p>
+Here is the current snapshot of our toolchain: <a href="icestorm-snapshot-150526.zip">icestorm-snapshot-150526.zip</a><br/>
+<i>This is work under construction and highly experimental! Use at your own risk!</i>
+</p>
+
+<p style="margin-bottom: 0.5em;">
+All snapshots in reverse chronological order:
+</p>
+
+<ul style="margin-top: 0.5em;">
+<li><a href="icestorm-snapshot-150526.zip">icestorm-snapshot-150526.zip</a></li>
+<li><a href="icestorm-snapshot-150413.zip">icestorm-snapshot-150413.zip</a></li>
+<li><a href="icestorm-snapshot-150401.zip">icestorm-snapshot-150401.zip</a></li>
+<li><a href="icestorm-snapshot-150322.zip">icestorm-snapshot-150322.zip</a></li>
+</ul>
+
+<h3>IcePack/IceUnpack</h3>
+
+<p>
+The <tt>iceunpack</tt> program converts an iCE40 <tt>.bin</tt> file into the IceBox ASCII format
+that has blocks of <tt>0</tt> and <tt>1</tt> for the config bits for each tile in the chip. The
+<tt>icepack</tt> program converts such an ASCII file back to an iCE40 <tt>.bin</tt> file.
+</p>
+
+<h3>IceBox</h3>
+
+<p>
+A python library and various tools for working with IceBox ASCII files and accessing
+the device database. For example <tt>icebox_vlog.py</tt> converts our ASCII file
+dump of a bitstream into a verilog file that implements an equivalent circuit.
+</p>
+
+<h3>IceProg</h3>
+
+<p>
+A small driver programm for the FTDI-based programmer used on the iCEstick and HX8K development boards.
+</p>
+
+<p>
+<i>The tools are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser.</i>
+</p>
+
+<h2>Where is the Documentation?</h2>
+
+<p>
+Recommended reading:
+<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf">Lattice iCE40 LP/HX Family Datasheet</a>,
+<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201412.pdf">Lattice iCE Technology Library</a>
+(Especially the three pages on "Architecture Overview", "PLB Blocks", "Routing", and "Clock/Control Distribution Network" in
+the Lattice iCE40 LP/HX Family Datasheet. Read that first, then come back here.)
+</p>
+
+<p>
+The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
+</p>
+
+<ul>
+<li><a href="logic_tile.html">LOGIC Tile Documentation</a></li>
+<li><a href="io_tile.html">IO Tile Documentation</a></li>
+<li><a href="ram_tile.html">RAM Tile Documentation</a></li>
+<li><a href="format.html">The Bitstream File Format</a></li>
+<li><a href="bitdocs/">Tile Bits Reference Docs</a></li>
+</ul>
+
+<p>
+The <tt>iceunpack</tt> program can be used to convert the bitstream into an ASCII file
+that has a block of <tt>0</tt> and <tt>1</tt> characters for each tile. For example:
+</p>
+
+<pre style="padding-left: 3em">.logic_tile 12 12
+000000000000000000000000000000000000000000000000000000
+000000000000000000000011010000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000001011000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000001000001000010101010000000000
+000000000000000000000000000101010000101010100000000000</pre>
+
+<p>
+This bits are referred to as <tt>B<i>y</i>[<i>x</i>]</tt> in the documentation. For example, <tt>B0</tt> is the first
+line, <tt>B0[0]</tt> the first bit in the first line, and <tt>B15[53]</tt> the last bit in the last line.
+</p>
+
+<p>
+The <tt>icebox_explain.py</tt> program can be used to turn this block of config bits into a description of the cell
+configuration:
+</p>
+
+<pre style="padding-left: 3em">.logic_tile 12 12
+LC_7 0101010110101010 0000
+buffer local_g0_2 lutff_7/in_3
+buffer local_g1_4 lutff_7/in_0
+buffer sp12_h_r_18 local_g0_2
+buffer sp12_h_r_20 local_g1_4</pre>
+
+<p>
+IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed
+via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API
+to export this database into a format that fits the target application. See <tt>icebox_chipdb.py</tt> for
+an example program that does that.
+</p>
+
+<p>
+The recommended approach for learning how to use this documentation is to synthesize very simple circuits using
+Lattice iCEcube2, run our toolchain on the resulting bitstream files, and analyze the results using the HTML export of the database
+mentioned above. <tt>icebox_vlog.py</tt> can be used to convert the bitstream to verilog. The output file of
+this tool will also outline the signal paths in comments added to the generated verilog.
+</p>
+
+<p>
+For example, using the <tt>top_bitmap.bin</tt> from the following Verilog and PCF files:
+</p>
+
+<pre style="padding-left: 3em">module top (input a, b, output y);
+  assign y = a &amp; b;
+endmodule
+
+set_io a 1
+set_io b 10
+set_io y 11</pre>
+
+<p>
+We would get something like the following <tt>icebox_explain.py</tt> output:
+</p>
+
+<pre style="padding-left: 3em">$ iceunpack top_bitmap.bin top_bitmap.txt
+$ icebox_explain top_bitmap.txt
+Reading file 'top_bitmap.txt'..
+Fabric size (without IO tiles): 12 x 16
+
+.io_tile 0 10
+IOB_1 PINTYPE_0
+IOB_1 PINTYPE_3
+IOB_1 PINTYPE_4
+IoCtrl IE_0
+IoCtrl IE_1
+IoCtrl REN_0
+buffer local_g1_2 io_1/D_OUT_0
+buffer logic_op_tnr_2 local_g1_2
+
+.io_tile 0 14
+IOB_1 PINTYPE_0
+IoCtrl IE_1
+IoCtrl REN_0
+buffer io_1/D_IN_0 span4_horz_28
+
+.io_tile 0 11
+IOB_0 PINTYPE_0
+IoCtrl IE_0
+IoCtrl REN_1
+
+.logic_tile 1 11
+LC_2 0000000001010101 0000
+buffer local_g1_4 lutff_2/in_3
+buffer local_g3_1 lutff_2/in_0
+buffer neigh_op_lft_4 local_g1_4
+buffer sp4_r_v_b_41 local_g3_1
+
+.logic_tile 2 14
+routing sp4_h_l_41 sp4_v_b_4</pre>
+
+<p>
+And something like the following <tt>icebox_vlog.py</tt> output:
+</p>
+
+<pre style="padding-left: 3em">$ icebox_vlog top_bitmap.txt
+// Reading file 'top_bitmap.txt'..
+
+module chip (output io_0_10_1, input io_0_11_0, input io_0_14_1);
+
+wire io_0_10_1;
+// io_0_10_1
+// (0, 10, 'io_1/D_OUT_0')
+// (0, 10, 'io_1/PAD')
+// (0, 10, 'local_g1_2')
+// (0, 10, 'logic_op_tnr_2')
+// (0, 11, 'logic_op_rgt_2')
+// (0, 12, 'logic_op_bnr_2')
+// (1, 10, 'neigh_op_top_2')
+// (1, 11, 'lutff_2/out')
+// (1, 12, 'neigh_op_bot_2')
+// (2, 10, 'neigh_op_tnl_2')
+// (2, 11, 'neigh_op_lft_2')
+// (2, 12, 'neigh_op_bnl_2')
+
+wire io_0_11_0;
+// io_0_11_0
+// (0, 11, 'io_0/D_IN_0')
+// (0, 11, 'io_0/PAD')
+// (1, 10, 'neigh_op_tnl_0')
+// (1, 10, 'neigh_op_tnl_4')
+// (1, 11, 'local_g1_4')
+// (1, 11, 'lutff_2/in_3')
+// (1, 11, 'neigh_op_lft_0')
+// (1, 11, 'neigh_op_lft_4')
+// (1, 12, 'neigh_op_bnl_0')
+// (1, 12, 'neigh_op_bnl_4')
+
+wire io_0_14_1;
+// io_0_14_1
+// (0, 14, 'io_1/D_IN_0')
+// (0, 14, 'io_1/PAD')
+// (0, 14, 'span4_horz_28')
+// (1, 11, 'local_g3_1')
+// (1, 11, 'lutff_2/in_0')
+// (1, 11, 'sp4_r_v_b_41')
+// (1, 12, 'sp4_r_v_b_28')
+// (1, 13, 'neigh_op_tnl_2')
+// (1, 13, 'neigh_op_tnl_6')
+// (1, 13, 'sp4_r_v_b_17')
+// (1, 14, 'neigh_op_lft_2')
+// (1, 14, 'neigh_op_lft_6')
+// (1, 14, 'sp4_h_r_41')
+// (1, 14, 'sp4_r_v_b_4')
+// (1, 15, 'neigh_op_bnl_2')
+// (1, 15, 'neigh_op_bnl_6')
+// (2, 10, 'sp4_v_t_41')
+// (2, 11, 'sp4_v_b_41')
+// (2, 12, 'sp4_v_b_28')
+// (2, 13, 'sp4_v_b_17')
+// (2, 14, 'sp4_h_l_41')
+// (2, 14, 'sp4_v_b_4')
+
+assign io_0_10_1 = /* LUT    1 11  2 */ io_0_11_0 ? io_0_14_1 : 0;
+
+endmodule</pre>
+
+<p>
+<hr>
+</p>
+
+<p>
+In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/,
+e.g. using the following BibTeX code:
+</p>
+
+<pre>@MISC{IceStorm,
+	author = {Clifford Wolf and Mathias Lasser},
+	title = {Project IceStorm},
+	howpublished = "\url{http://www.clifford.at/icestorm/}"
+}</pre>
+
+<p>
+<hr>
+</p>
+
+<p>
+<i>Documentation mostly by Clifford Wolf &lt;clifford@clifford.at&gt; in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
+Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> from Lattice and see what you can do with the information provided here. Buy a few because you might break some..</i>
+</p>
diff --git a/docs/io_tile.html b/docs/io_tile.html
new file mode 100644
index 0000000..0324ac8
--- /dev/null
+++ b/docs/io_tile.html
@@ -0,0 +1,496 @@
+<title>Project IceStorm &ndash; IO Tile Documentation</title>
+<h1>Project IceStorm &ndash; IO Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p><a href="iosp.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="iosp.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the span-wires of a left (or right) io cell (click to enlarge).
+</p>
+
+<p>
+A left/right io cell has 16 connections named <tt>span4_vert_t_0</tt> to <tt>span4_vert_t_15</tt> on its top edge and
+16 connections named <tt>span4_vert_b_0</tt> to <tt>span4_vert_b_15</tt> on its bottom edge. The nets <tt>span4_vert_t_0</tt>
+to <tt>span4_vert_t_11</tt> are connected to <tt>span4_vert_b_4</tt> to <tt>span4_vert_b_15</tt>. The span-4 and span-12 wires
+of the adjacent logic cell are connected to the nets <tt>span4_horz_0</tt> to <tt>span4_horz_47</tt> and <tt>span12_horz_0</tt>
+to <tt>span12_horz_23</tt>.
+</p>
+
+<p>
+A top/bottom io cell has 16 connections named <tt>span4_vert_l_0</tt> to <tt>span4_vert_l_15</tt> on its top edge and
+16 connections named <tt>span4_vert_r_0</tt> to <tt>span4_vert_r_15</tt> on its bottom edge. The nets <tt>span4_vert_l_0</tt>
+to <tt>span4_vert_l_11</tt> are connected to <tt>span4_vert_r_4</tt> to <tt>span4_vert_r_15</tt>. The span-4 and span-12 wires
+of the adjacent logic cell are connected to the nets <tt>span4_vert_0</tt> to <tt>span4_vert_47</tt> and <tt>span12_vert_0</tt>
+to <tt>span12_vert_23</tt>.
+</p>
+
+<p>
+The vertical span4 wires of left/right io cells are connected "around the corner" to the horizontal span4 wires of the top/bottom
+io cells. For example <tt>span4_vert_b_0</tt> of IO cell (0 1) is connected to <tt>span4_horz_l_0</tt> (<tt>span4_horz_r_4</tt>)
+of IO cell (1 0).
+</p>
+
+<p>
+Note that unlike the span-wires connection LOGIC and RAM tiles, the span-wires
+connecting IO tiles to each other are not pairwised crossed out.
+</p>
+
+<h2>IO Blocks</h2>
+
+<p>
+Each IO tile contains two IO blocks. Each IO block essentially implements the <tt>SB_IO</tt>
+primitive from the <a href="http://www.latticesemi.com/~/media/Documents/TechnicalBriefs/iCETechnologyLibrary.PDF">Lattice iCE Technology Library</a>.
+Some inputs are shared between the two IO blocks. The following table lists how the
+wires in the logic tile map to the <tt>SB_IO</tt> primitive ports:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>SB_IO Port</th><th>IO Block 0</th><th>IO Block 1</th></tr>
+<tr><td>D_IN_0</td><td><tt>io_0/D_IN_0</tt></td><td><tt>io_1/D_IN_0</tt></td></tr>
+<tr><td>D_IN_1</td><td><tt>io_0/D_IN_1</tt></td><td><tt>io_1/D_IN_1</tt></td></tr>
+<tr><td>D_OUT_0</td><td><tt>io_0/D_OUT_0</tt></td><td><tt>io_1/D_OUT_0</tt></td></tr>
+<tr><td>D_OUT_1</td><td><tt>io_0/D_OUT_1</tt></td><td><tt>io_1/D_OUT_1</tt></td></tr>
+<tr><td>OUTPUT_ENABLE</td><td><tt>io_0/OUT_ENB</tt></td><td><tt>io_1/OUT_ENB</tt></td></tr>
+<tr><td>CLOCK_ENABLE</td><td colspan="2"><tt>io_global/cen</tt></td></tr>
+<tr><td>INPUT_CLK</td><td colspan="2"><tt>io_global/inclk</tt></td></tr>
+<tr><td>OUTPUT_CLK</td><td colspan="2"><tt>io_global/outclk</tt></td></tr>
+<tr><td>LATCH_INPUT_VALUE</td><td colspan="2"><tt>io_global/latch</tt></td></tr>
+</table>
+</p>
+
+<p>
+Like the inputs to logic cells, the inputs to IO blocks are routed to the IO block via a two-stage process. A signal
+is first routed to one of 16 local tracks in the IO tile and then from the local track to the IO block.
+</p>
+
+<p>
+The <tt>io_global/latch</tt> signal is shared among all IO tiles on an edge of the chip and is driven by <tt>wire_gbuf/in</tt>
+from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <tt>io_global/latch</tt> signal are:
+(0, 7), (13, 10), (5, 0), and (8, 17)
+</p>
+
+<p>
+A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four <tt>D_IN</tt>
+signals created by its two IO blocks. The <tt>D_IN</tt> signals map to logic function indices as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Function Index</th><th>D_IN Wire</th></tr>
+<tr><td>0</td><td><tt>io_0/D_IN_0</tt></td></tr>
+<tr><td>1</td><td><tt>io_0/D_IN_1</tt></td></tr>
+<tr><td>2</td><td><tt>io_1/D_IN_0</tt></td></tr>
+<tr><td>3</td><td><tt>io_1/D_IN_1</tt></td></tr>
+<tr><td>4</td><td><tt>io_0/D_IN_0</tt></td></tr>
+<tr><td>5</td><td><tt>io_0/D_IN_1</tt></td></tr>
+<tr><td>6</td><td><tt>io_1/D_IN_0</tt></td></tr>
+<tr><td>7</td><td><tt>io_1/D_IN_1</tt></td></tr>
+</table>
+</p>
+
+<p>
+For example the signal <tt>io_1/D_IN_0</tt> in IO tile (0, 5) can be seen as <tt>neigh_op_lft_2</tt> and <tt>neigh_op_lft_6</tt> in LOGIC tile (1, 5).
+</p>
+
+<p>
+Each IO Tile has 2 <tt>NegClk</tt> configuration bits, suggesting that the
+clock signals can be inverted independently for the the two IO blocks in the
+tile. However, the Lattice tools refuse to pack to IO blocks with different block
+polarity into the same IO tile. In our tests we only managed to either set or clear
+both NegClk bits.
+</p>
+
+<p>
+Each IO block has two <tt>IoCtrl IE</tt> bits that enable the input buffers and 
+two <tt>IoCtrl REN</tt> bits that enable the pull up resistors. Both bits are active
+low, i.e. an unused IO tile will have both IE bits set and both REN bits cleared (the
+default behavior is to enable pullup resistors on all unused pins). Note that
+<tt>icebox_explain.py</tt> will ignore all IO tiles that only have the two <tt>IoCtrl
+IE</tt> bits set.
+</p>
+
+<p>
+However, the <tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> do not
+necessarily configure the IO PIN that are connected to the IO block in the same tile,
+and if they do the numbers (0/1) do not necessarily match. As a general rule, the pins
+on the right and bottom side of the chips match up with the IO blocks and for the pins
+on the left and top side the numbers must be swapped. But in some cases the IO block
+and the set of <tt>IE/REN</tt> are not even located in the same tile. The following
+table lists the correlation between IO blocks and <tt>IE/REN</tt> bits for the
+1K chip:
+</p>
+
+<p align="center">
+<table cellpadding="10">
+<tr><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 1</td><td align="center">0 14 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 0</td><td align="center">0 14 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 1</td><td align="center">0 13 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 0</td><td align="center">0 13 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 1</td><td align="center">0 12 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 0</td><td align="center">0 12 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 1</td><td align="center">0 11 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 0</td><td align="center">0 11 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 1</td><td align="center">0 10 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 0</td><td align="center">0 10 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  9 1</td><td align="center">0  9 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  9 0</td><td align="center">0  9 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  8 1</td><td align="center">0  8 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  8 0</td><td align="center">0  8 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  6 1</td><td align="center">0  6 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  6 0</td><td align="center">0  6 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  5 1</td><td align="center">0  5 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  5 0</td><td align="center">0  5 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  4 1</td><td align="center">0  4 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  4 0</td><td align="center">0  4 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  3 1</td><td align="center">0  3 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  3 0</td><td align="center">0  3 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  2 1</td><td align="center">0  2 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0  2 0</td><td align="center">0  2 1</td></tr>
+</table>
+
+</td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 0</td><td align="center"> 1 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 1</td><td align="center"> 1 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 0</td><td align="center"> 2 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 1</td><td align="center"> 2 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 0</td><td align="center"> 3 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 1</td><td align="center"> 3 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 0</td><td align="center"> 4 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 1</td><td align="center"> 4 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 0</td><td align="center"> 5 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 1</td><td align="center"> 5 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 1</td><td align="center"> 6 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 0</td><td align="center"> 6 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 0</td><td align="center"> 7 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 1</td><td align="center"> 7 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 0</td><td align="center"> 8 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 1</td><td align="center"> 8 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 0</td><td align="center"> 9 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 1</td><td align="center"> 9 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 0</td><td align="center">10 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 1</td><td align="center">10 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 0</td><td align="center">11 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 1</td><td align="center">11 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 0</td><td align="center">12 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 1</td><td align="center">12 0 1</td></tr>
+</table>
+
+</td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  1 0</td><td align="center">13  1 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  1 1</td><td align="center">13  1 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  2 0</td><td align="center">13  2 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  2 1</td><td align="center">13  2 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  3 1</td><td align="center">13  3 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  4 0</td><td align="center">13  4 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  4 1</td><td align="center">13  4 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  6 0</td><td align="center">13  6 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  6 1</td><td align="center">13  6 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  7 0</td><td align="center">13  7 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  7 1</td><td align="center">13  7 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  8 0</td><td align="center">13  8 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  8 1</td><td align="center">13  8 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  9 0</td><td align="center">13  9 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13  9 1</td><td align="center">13  9 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 0</td><td align="center">13 10 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 1</td><td align="center">13 10 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 0</td><td align="center">13 11 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 1</td><td align="center">13 11 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 0</td><td align="center">13 13 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 1</td><td align="center">13 13 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 0</td><td align="center">13 14 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 1</td><td align="center">13 14 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 0</td><td align="center">13 15 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 1</td><td align="center">13 15 1</td></tr>
+</table>
+
+</td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 1</td><td align="center">12 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 0</td><td align="center">12 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 1</td><td align="center">11 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 0</td><td align="center">11 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 1</td><td align="center"> 9 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 0</td><td align="center"> 9 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 1</td><td align="center">10 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 0</td><td align="center">10 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 1</td><td align="center"> 8 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 0</td><td align="center"> 8 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 1</td><td align="center"> 7 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 0</td><td align="center"> 7 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 17 1</td><td align="center"> 6 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 1</td><td align="center"> 5 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 0</td><td align="center"> 5 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 1</td><td align="center"> 4 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 0</td><td align="center"> 4 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 1</td><td align="center"> 3 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 0</td><td align="center"> 3 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 1</td><td align="center"> 2 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 0</td><td align="center"> 2 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 1</td><td align="center"> 1 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 0</td><td align="center"> 1 17 0</td></tr>
+</table>
+
+</table>
+</p>
+
+<p>
+When an input pin pair is used as LVDS pair (IO standard
+<tt>SB_LVDS_INPUT</tt>, bank 3 / left edge only), then the four bits
+<tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> are all set, as well
+as the <tt>IoCtrl LVDS</tt> bit.
+</p>
+
+<p>
+In the iCE 8k devices the <tt>IoCtrl IE</tt> bits are active high. So an unused
+IO tile on an 8k chip has all bits cleared.
+</p>
+
+<h2>Global Nets</h2>
+
+<p>
+iCE40 FPGAs have 8 global nets. Each global net can be driven directly from an
+IO pin.  In the FPGA bitstream, routing of external signals to global nets is
+not controlled by bits in the IO tile. Instead bits that do not belong to any
+tile are used. In IceBox nomenclature such bits are called "extra bits".
+</p>
+
+<p>
+The following table lists which pins / IO blocks may be used to drive
+which global net, and what <tt>.extra</tt> statements in the IceBox ASCII file
+format to represent the corresponding configuration bits:
+</p>
+
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Glb Net</th><th>Pin<br/>(HX1K-TQ144)</th><th>IO Tile +<br/>Block #</th><th>IceBox Statement</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0</td><td align="center"> 93</td><td align="center">13  8  1</td><td align="center">.extra_bit 0 330 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">1</td><td align="center"> 21</td><td align="center"> 0  8  1</td><td align="center">.extra_bit 0 331 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">2</td><td align="center">128</td><td align="center"> 7 17  0</td><td align="center">.extra_bit 1 330 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">3</td><td align="center"> 50</td><td align="center"> 7  0  0</td><td align="center">.extra_bit 1 331 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">4</td><td align="center"> 20</td><td align="center"> 0  9  0</td><td align="center">.extra_bit 1 330 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">5</td><td align="center"> 94</td><td align="center">13  9  0</td><td align="center">.extra_bit 1 331 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">6</td><td align="center"> 49</td><td align="center"> 6  0  1</td><td align="center">.extra_bit 0 330 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">7</td><td align="center">129</td><td align="center"> 6 17  1</td><td align="center">.extra_bit 0 331 143</td></tr>
+</table>
+</p>
+
+<p>
+Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal
+to the <tt>wire_gbuf/in</tt> net on an IO tile. The same set of I/O tiles is used for this, but in this
+case each of the I/O tiles corresponds to a different global net:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Glb Net</th>
+<td align="center">0</td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center">4</td>
+<td align="center">5</td>
+<td align="center">6</td>
+<td align="center">7</td></tr>
+<tr><th>IO Tile</th>
+<td style="white-space: pre; font-family: monospace" align="center"> 7  0</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 7 17</td>
+<td style="white-space: pre; font-family: monospace" align="center">13  9</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 0  9</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 6 17</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 6  0</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 0  8</td>
+<td style="white-space: pre; font-family: monospace" align="center">13  8</td></tr>
+</table>
+</p>
+
+<p><a href="colbuf.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="colbuf.svg" border="0"></a></p>
+
+<h3>Column Buffer Control Bits</h3>
+
+<p>
+Each LOGIC, IO, and RAMB tile has 8 ColBufCtrl bits, one for each global net. In most tiles this
+bits have no function, but in tiles in rows 4, 5, 12, and 13 (for RAM columns: rows 3, 5, 11, and 13) this bits
+control which global nets are driven to the column of tiles below and/or above that tile (including that tile),
+as illustrated in the image to the right (click to enlarge).
+</p>
+
+<p>
+In 8k chips the rows 8, 9, 24, and 25 contain the column buffers. 8k RAMB and
+RAMT tiles can control column buffers, so the pattern looks the same for RAM, LOGIC, and
+IO columns.
+</p>
+
+<h2>Warmboot</h2>
+
+<p>
+The <tt>SB_WARMBOOT</tt> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell
+are driven by the <tt>wire_gbuf/in</tt> signal from three IO tiles. In HX1K chips the tiles connected to the
+<tt>SB_WARMBOOT</tt> primitive are:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Warmboot Pin</th><th>IO Tile</th></tr>
+<tr><td>BOOT</td><td><tt>12 0</tt></td></tr>
+<tr><td>S0</td><td><tt>13 1</tt></td></tr>
+<tr><td>S1</td><td><tt>13 2</tt></td></tr>
+</table>
+</p>
+
+<h2>PLL Cores</h2>
+
+<p>
+The PLL primitives in iCE40 FPGAs are configured using the <tt>PLLCONFIG_*</tt>
+bits in the IO tiles. The configuration for a single PLL cell is spread out
+over many IO tiles. For example, the PLL cell in the 1K chip are configured as
+follows (bits listed from LSB to MSB):
+</p>
+
+<p align="center">
+<table cellpadding="10"><tr><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3">Select PLL Type:<br/>
+000 = DISABLED<br/>
+010 = SB_PLL40_PAD<br/>
+100 = SB_PLL40_2_PAD<br/>
+110 = SB_PLL40_2F_PAD<br/>
+011 = SB_PLL40_CORE<br/>
+111 = SB_PLL40_2F_CORE</td></tr>
+<tr><td>0 5</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 5</td><td><tt>PLLCONFIG_3</tt></td></tr>
+
+<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3"><tt>FEEDBACK_PATH</tt><br/>
+000 = "DELAY"<br/>
+001 = "SIMPLE"<br/>
+010 = "PHASE_AND_DELAY"<br/>
+110 = "EXTERNAL"</td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_9</tt></td></tr>
+<tr><td>0 3</td><td><tt>PLLCONFIG_1</tt></td></tr>
+
+<tr><td>0 4</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_FEEDBACK</tt><br/>
+0 = "FIXED"<br/>
+1 = "DYNAMIC"</td></tr>
+
+<tr><td>0 4</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_RELATIVE</tt><br/>
+0 = "FIXED"<br/>
+1 = "DYNAMIC"</td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="2"><tt>PLLOUT_SELECT<br/>PLLOUT_SELECT_PORTA</tt><br/>
+00 = "GENCLK"<br/>
+01 = "GENCLK_HALF"<br/>
+10 = "SHIFTREG_90deg"<br/>
+11 = "SHIFTREG_0deg"</td></tr>
+<tr><td>0 3</td><td><tt>PLLCONFIG_7</tt></td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_2</tt></td><td rowspan="2"><tt>PLLOUT_SELECT_PORTB</tt><br/>
+00 = "GENCLK"<br/>
+01 = "GENCLK_HALF"<br/>
+10 = "SHIFTREG_90deg"<br/>
+11 = "SHIFTREG_0deg"</td></tr>
+<tr><td>0 3</td><td><tt>PLLCONFIG_3</tt></td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>SHIFTREG_DIV_MODE</tt></td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_8</tt></td><td rowspan="1"><tt>TEST_MODE</tt></td></tr>
+
+</table></td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="4"><tt>FDA_FEEDBACK</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_2</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_3</tt></td></tr>
+
+<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="4"><tt>FDA_RELATIVE</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_6</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_8</tt></td></tr>
+
+<tr><td>0 1</td><td><tt>PLLCONFIG_1</tt></td><td rowspan="4"><tt>DIVR</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_2</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_3</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_4</tt></td></tr>
+
+<tr><td>0 1</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="7"><tt>DIVF</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_6</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_8</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_9</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_2</tt></td></tr>
+
+<tr><td>0 2</td><td><tt>PLLCONFIG_3</tt></td><td rowspan="3"><tt>DIVQ</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_4</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_5</tt></td></tr>
+
+<tr><td>0 2</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="3"><tt>FILTER_RANGE</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_8</tt></td></tr>
+
+</table>
+</table>
+</p>
+
+<p>
+The PLL inputs are routed to the PLL via the <tt>wire_gbuf/in</tt> signal from various IO tiles. The non-clock
+PLL outputs are routed via otherwise unused <tt>neigh_op_*</tt> signals in fabric corners. For example in case
+of the 1k chip:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Tile</th><th>Net-Segment</th><th>SB_PLL40_* Port Name</th></tr>
+<tr><td>0 1</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>REFERENCECLK</tt></td></tr>
+<tr><td>0 2</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>EXTFEEDBACK</tt></td></tr>
+<tr><td>0 4</td><td><tt>wire_gbuf/in</tt></td><td rowspan="8"><tt>DYNAMICDELAY</tt></td></tr>
+<tr><td>0 5</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 6</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 10</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 11</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 12</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 13</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 14</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>1 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>LOCK</tt></td></tr>
+<tr><td>1 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>BYPASS</tt></td></tr>
+<tr><td>2 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>RESETB</tt></td></tr>
+<tr><td>5 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>LATCHINPUTVALUE</tt></td></tr>
+<tr><td>12 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>SDO</tt></td></tr>
+<tr><td>4 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>SDI</tt></td></tr>
+<tr><td>5 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>SCLK</tt></td></tr>
+</table>
+</p>
+
+<p>
+The PLL clock outputs are fed directly into the input path of certain IO tiles.
+In case of the 1k chip the PORTA clock is fed into PIO 1 of IO Tile (6 0) and
+the PORTB clock is fed into PIO 0 of IO Tile (7 0). Because of this, those two
+PIOs can only be used as output Pins by the FPGA fabric when the PLL ports
+are being used.
+</p>
+
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diff --git a/docs/logic_tile.html b/docs/logic_tile.html
new file mode 100644
index 0000000..8e3dcad
--- /dev/null
+++ b/docs/logic_tile.html
@@ -0,0 +1,327 @@
+<title>Project IceStorm &ndash; LOGIC Tile Documentation</title>
+<h1>Project IceStorm &ndash; LOGIC Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p>
+The <i>span-4</i> and <i>span-12</i> wires are the main interconnect resource in iCE40 FPGAs. They "span" (have a length of)
+4 or 12 cells in horizontal or vertical direction.
+</p>
+
+<p>
+The bits marked <tt>routing</tt> in the bitstream do enable switches (transfer gates) that can
+be used to connect wire segments bidirectionally to each other in order to create larger
+segments. The bits marked <tt>buffer</tt> in the bitstream enable tristate buffers that drive
+the signal in one direction from one wire to another. Both types of bits exist for routing between
+span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.
+</p>
+
+<p>
+Only directional tristate buffers are used to route signals between the span-wires and the logic cells.
+</p>
+
+<h3 style="clear:both">Span-4 Horizontal</h3>
+
+<p><a href="sp4h.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4h.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the <i>horizontal span-4</i> wires of a logic or ram cell (click to enlarge).
+</p>
+
+<p>
+On the left side of the cell there are 48 connections named <tt>sp4_h_l_0</tt> to <tt>sp4_h_l_47</tt>. The lower 36 of those
+wires are connected to <tt>sp4_h_r_12</tt> to <tt>sp4_h_r_47</tt> on the right side of the cell. (IceStorm normalizes this
+wire names to <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_35</tt>. Note: the Lattice tools use a different normalization scheme
+for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out.
+</p>
+
+<p>
+The wires <tt>sp4_h_l_36</tt> to <tt>sp4_h_l_47</tt> terminate in the cell, so do the wires <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_11</tt>.
+</p>
+
+<p>
+This wires "span" 4 cells, i.e. they connect 5 cells if you count the cells on
+both ends of the wire.
+</p>
+
+<p>
+For example, the wire <tt>sp4_h_r_0</tt> in cell (x, y) has the following names:
+</p>
+
+<p align="center">
+<table border>
+<tr><th>Cell Coordinates</th><th>sp4_h_l_* wire name</th><th>sp4_h_r_* wire name</th></tr>
+<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_h_r_0</tt></td></tr>
+<tr><td>x+1, y</td><td><tt>sp4_h_l_0</tt></td><td><tt>sp4_h_r_13</tt></td></tr>
+<tr><td>x+2, y</td><td><tt>sp4_h_l_13</tt></td><td><tt>sp4_h_r_24</tt></td></tr>
+<tr><td>x+3, y</td><td><tt>sp4_h_l_24</tt></td><td><tt>sp4_h_r_37</tt></td></tr>
+<tr><td>x+4, y</td><td><tt>sp4_h_l_37</tt></td><td><tt>-</tt></td></tr>
+</table>
+</p>
+
+<h3 style="clear:both">Span-4 Vertical</h3>
+
+<p><a href="sp4v.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4v.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the <i>veritical span-4</i> wires of a logic or ram cell (click to enlarge).
+</p>
+
+<p>
+Similar to the horizontal span-4 wires there are 48 connections on the top (<tt>sp4_v_t_0</tt> to <tt>sp4_v_t_47</tt>) and
+48 connections on the bottom (<tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt>). The wires <tt>sp4_v_t_0</tt> to <tt>sp4_v_t_35</tt>
+are connected to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt> (with pairwise crossing out). Wire names are normalized
+to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt>.
+</p>
+
+<p>
+But in addition to that, each cell also has access to <tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt> of its right neighbour.
+This are the wires <tt>sp4_r_v_b_0</tt> to <tt>sp4_r_v_b_47</tt>. So over all a single veritical span-4 wire
+connects 9 cells. For example, the wire <tt>sp4_v_b_0</tt> in cell (x, y) has the following names:
+</p>
+
+<p align="center">
+<table border>
+<tr><th>Cell Coordinates</th><th>sp4_v_t_* wire name</th><th>sp4_v_b_* wire name</th><th>sp4_r_v_b_* wire name</th></tr>
+<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_v_b_0</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-1</td><td><tt>sp4_v_t_0</tt></td><td><tt>sp4_v_b_13</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-2</td><td><tt>sp4_v_t_13</tt></td><td><tt>sp4_v_b_24</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-3</td><td><tt>sp4_v_t_24</tt></td><td><tt>sp4_v_b_37</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-4</td><td><tt>sp4_v_t_37</tt></td><td><tt>-</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x-1, y</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_0</tt></td></tr>
+<tr><td>x-1, y-1</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_13</tt></td></tr>
+<tr><td>x-1, y-2</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_24</tt></td></tr>
+<tr><td>x-1, y-3</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_37</tt></td></tr>
+</table>
+</p>
+
+<h3 style="clear:both">Span-12 Horizontal and Vertical</h3>
+
+<p>
+Similar to the span-4 wires there are also longer horizontal and vertical span-12 wires.
+</p>
+
+<p>
+There are 24 connections <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_23</tt> on the top of the
+cell and 24 connections <tt>sp12_v_b_0</tt> to <tt>sp12_v_b_23</tt> on the bottom of the
+cell. The wires <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_21</tt> are connected to
+<tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt> (with pairwise crossing out). The connections
+<tt>sp12_v_b_0</tt>, <tt>sp12_v_b_1</tt>, <tt>sp12_v_t_22</tt>, and <tt>sp12_v_t_23</tt>
+terminate in the cell. Wire names are normalized to <tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt>.
+</p>
+
+<p>
+There are also 24 connections <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_23</tt> on the left of the
+cell and 24 connections <tt>sp12_h_r_0</tt> to <tt>sp12_h_r_23</tt> on the right of the
+cell. The wires <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_21</tt> are connected to
+<tt>sp12_h_r_2</tt> to <tt>sp12_h_r_23</tt> (with pairwise crossing out). The connections
+<tt>sp12_h_r_0</tt>, <tt>sp12_h_r_1</tt>, <tt>sp12_h_l_22</tt>, and <tt>sp12_h_l_23</tt>
+terminate in the cell. Wire names are normalized to <tt>sp12_v_r_2</tt> to <tt>sp12_h_r_23</tt>.
+</p>
+
+<h2>Local Tracks</h2>
+
+<p>
+The <i>local tracks</i> are the gateway to the logic cell inputs. Signals from the span-wires
+and the logic cell ouputs of the eight neighbour cells can be routed to the local tracks and
+signals from the local tracks can be routed to the logic cell inputs.
+</p>
+
+<p>
+Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each:
+<tt>local_g0_0</tt> to <tt>local_g3_7</tt>.
+</p>
+
+<p>
+The span wires, global signals, and neighbour outputs can be routed to the local tracks. But not
+every of those signals can be routed to every of the local tracks. Instead there is a different
+mix of 16 signals for each local track.
+</p>
+
+<p>
+The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select
+the input wire. For example for <tt>local_g0_0</tt> (copy&amp;paste from the bitstream doku):
+</p>
+
+<p align="center">
+<table border=""><tbody><tr>
+<th style="width:5em"><a name="B.0.14">B0[14]</a></th>
+<th style="width:5em"><a name="B.1.14">B1[14]</a></th>
+<th style="width:5em"><a name="B.1.15">B1[15]</a></th>
+<th style="width:5em"><a name="B.1.16">B1[16]</a></th>
+<th style="width:5em"><a name="B.1.17">B1[17]</a></th>
+<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_24</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bot_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_35</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_top_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>lutff_0/out</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_lft_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bnr_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+</tbody></table>
+</p>
+
+<p>
+Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before,
+not every local track can be routed to every logic cell input pin. Instead there is a different mix
+of 16 local track for each logic cell input. For example for <tt>lutff_0/in_0</tt>:
+</p>
+
+<p align="center">
+<table border=""><tbody><tr>
+<th style="width:5em"><a name="B.0.26">B0[26]</a></th>
+<th style="width:5em"><a name="B.1.26">B1[26]</a></th>
+<th style="width:5em"><a name="B.1.27">B1[27]</a></th>
+<th style="width:5em"><a name="B.1.28">B1[28]</a></th>
+<th style="width:5em"><a name="B.1.29">B1[29]</a></th>
+<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+</tbody></table>
+</p>
+
+<p>
+The 8 global nets on the iCE40 can be routed to the local track via the <tt>glb2local_0</tt> to <tt>glb2local_3</tt>
+nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven
+directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven
+from any of the global nets and from a few local tracks. See the bitstream documentation for details.
+</p>
+
+<h2>Logic Block</h2>
+
+<p>
+Each logic tile has a logic block containing 8 logic cells. Each logic cell contains a 4-input LUT, a carry
+unit and a flip-flop. Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the
+bit that configures positive/negative edge for the flip flops. But the three configuration bits that specify if
+the flip flop should be used, if it is set or reset by the set/reset input, and if the set/reset is synchronous
+or asynchrouns exist for each logic cell individually.
+</p>
+
+<p>
+Each LUT <i>i</i> has four input wires <tt>lutff_<i>i</i>/in_0</tt> to <tt>lutff_<i>i</i>/in_3</tt>. Input
+<tt>lutff_<i>i</i>/in_3</tt> can be configured to be driven by the carry output of the previous logic cell,
+or by <tt>carry_in_mux</tt> in case of <i>i</i>=0. Input <tt>lutff_<i>i</i>/in_2</tt> can be configured to
+be driven by the output of the previous LUT for <i>i</i>&gt;0. The LUT uses its 4 input signals to
+calculate <tt>lutff_<i>i</i>/out</tt>.
+</p>
+
+<p>
+The carry unit calculates <tt>lutff_<i>i</i>/cout</tt> = <tt>lutff_<i>i</i>/in_1</tt> + <tt>lutff_<i>i</i>/in_2</tt> + <tt>lutff_<i>(i-1)</i>/cout</tt> &gt; 1</tt>. In case of <i>i</i>=0, <tt>carry_in_mux</tt> is used as third input. <tt>carry_in_mux</tt> can be configured to be constant 0, 1 or the <tt>lutff_7/cout</tt> signal from the logic tile below.
+</p>
+
+<p>
+Part of the functionality described above is documented as part of the routing
+bitstream documentation (see the buffers for <tt>luttff_</tt> inputs). The <tt>NegClk</tt>
+bit switches all 8 FFs in the tile to negative edge mode. The <tt>CarryInSet</tt>
+bit drives the <tt>carry_in_mux</tt> high (it defaults to low when not driven via the buffer from
+<tt>carry_in</tt>).
+</p>
+
+<p>
+The remaining functions of the logic cell are configured via the <tt>LC_<i>i</i></tt> bits. This
+are 20 bit per logic cell. We have arbitrarily labeld those bits as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Label</th><th>LC_0</th><th>LC_1</th><th>LC_2</th><th>LC_3</th><th>LC_4</th><th>LC_5</th><th>LC_6</th><th>LC_7</th></tr>
+<tr><td>LC_<i>i</i>[0]</tt></td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr>
+<tr><td>LC_<i>i</i>[1]</tt></td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr>
+<tr><td>LC_<i>i</i>[2]</tt></td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr>
+<tr><td>LC_<i>i</i>[3]</tt></td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr>
+<tr><td>LC_<i>i</i>[4]</tt></td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr>
+<tr><td>LC_<i>i</i>[5]</tt></td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr>
+<tr><td>LC_<i>i</i>[6]</tt></td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr>
+<tr><td>LC_<i>i</i>[7]</tt></td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr>
+<tr><td>LC_<i>i</i>[8]</tt></td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr>
+<tr><td>LC_<i>i</i>[9]</tt></td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr>
+<tr><td>LC_<i>i</i>[10]</tt></td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr>
+<tr><td>LC_<i>i</i>[11]</tt></td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr>
+<tr><td>LC_<i>i</i>[12]</tt></td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr>
+<tr><td>LC_<i>i</i>[13]</tt></td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr>
+<tr><td>LC_<i>i</i>[14]</tt></td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr>
+<tr><td>LC_<i>i</i>[15]</tt></td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr>
+<tr><td>LC_<i>i</i>[16]</tt></td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr>
+<tr><td>LC_<i>i</i>[17]</tt></td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr>
+<tr><td>LC_<i>i</i>[18]</tt></td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr>
+<tr><td>LC_<i>i</i>[19]</tt></td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr>
+</table>
+</p>
+
+<p>
+<tt>LC_<i>i</i>[8]</tt> is the <tt>CarryEnable</tt> bit. This bit must be set if the carry logic is used.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[9]</tt> is the <tt>DffEnable</tt> bit. It enables the output flip-flop for the LUT.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[18]</tt> is the <tt>Set_NoReset</tt> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[19]</tt> is the <tt>AsyncSetReset</tt> bit. When this bit is set then the set/reset signal is asynchronous to the clock.
+</p>
+
+<p>
+The LUT implements the following truth table:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>in_3</th><th>in_2</th><th>in_1</th><th>in_0</th><th>out</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[4]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[14]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[15]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[5]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[6]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[16]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[17]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[7]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[3]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[13]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[12]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[2]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[1]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[11]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[10]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[0]</tt></td></tr>
+</table>
+</p>
+
+<p>
+LUT inputs that are not connected to anything are driven low. The set/reset
+signal is also driven low if not connected to any other driver, and the clock
+enable signal is driven high when left unconnected.
+</p>
+
diff --git a/docs/ram_tile.html b/docs/ram_tile.html
new file mode 100644
index 0000000..3121f57
--- /dev/null
+++ b/docs/ram_tile.html
@@ -0,0 +1,95 @@
+<title>Project IceStorm &ndash; RAM Tile Documentation</title>
+<h1>Project IceStorm &ndash; RAM Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p>
+Regarding the Span-4 and Span-12 Wires a RAM tile behaves exactly like a LOGIC tile. So for simple
+applications that do not need the block ram resources, the RAM tiles can be handled like a LOGIC
+tiles without logic cells in them.
+</p>
+
+<h2>Block RAM Resources</h2>
+
+<p>
+A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with
+LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram
+inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates
+are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a <tt>SB_RAM40_4K</tt> cell. The
+cell ports are spread out over the two tiles as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>SB_RAM40_4K</th><th>RAMB Tile</th><th>RAMT Tile</th></tr>
+<tr><td><tt>RDATA[15:0]</tt></td><td><tt>RDATA[7:0]</tt></td><td><tt>RDATA[15:8]</tt></td></tr>
+<tr><td><tt>RADDR[10:0]</tt></td><td><tt>-</tt></td><td><tt>RADDR[10:0]</tt></td></tr>
+<tr><td><tt>WADDR[10:0]</tt></td><td><tt>WADDR[10:0]</tt></td><td><tt>-</tt></td></tr>
+<tr><td><tt>MASK[15:0]</tt></td><td><tt>MASK[7:0]</tt></td><td><tt>MASK[15:8]</tt></td></tr>
+<tr><td><tt>WDATA[15:0]</tt></td><td><tt>WDATA[7:0]</tt></td><td><tt>WDATA[15:8]</tt></td></tr>
+<tr><td><tt>RCLKE</tt></td><td><tt>-</tt></td><td><tt>RCLKE</tt></td></tr>
+<tr><td><tt>RCLK</tt></td><td><tt>-</tt></td><td><tt>RCLK</tt></td></tr>
+<tr><td><tt>RE</tt></td><td><tt>-</tt></td><td><tt>RE</tt></td></tr>
+<tr><td><tt>WCLKE</tt></td><td><tt>WCLKE</tt></td><td><tt>-</tt></td></tr>
+<tr><td><tt>WCLK</tt></td><td><tt>WCLK</tt></td><td><tt>-</tt></td></tr>
+<tr><td><tt>WE</tt></td><td><tt>WE</tt></td><td><tt>-</tt></td></tr>
+</table>
+</p>
+
+<p>
+The configuration bit <tt>RamConfig PowerUp</tt> in the RAMB tile enables the memory. This bit
+is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that <tt>icebox_explain.py</tt>
+will ignore all RAMB tiles that only have the <tt>RamConfig PowerUp</tt> bit set.
+</p>
+
+<p>
+In 8k chips the <tt>RamConfig PowerUp</tt> bit is active-high. So an unused RAM block has all bits cleared
+in the 8k config bitstream.
+</p>
+
+<p>
+The <tt>RamConfig CBIT_*</tt> bits in the RAMT tile configure the read/write width of the
+memory. Those bits map to the <tt>SB_RAM40_4K</tt> cell parameters as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>SB_RAM40_4K</th><th>RAMT Config Bit</th></tr>
+<tr><td><tt>WRITE_MODE[0]</tt></td><td><tt>RamConfig CBIT_0</tt></td></tr>
+<tr><td><tt>WRITE_MODE[1]</tt></td><td><tt>RamConfig CBIT_1</tt></td></tr>
+<tr><td><tt>READ_MODE[0]</tt></td><td><tt>RamConfig CBIT_2</tt></td></tr>
+<tr><td><tt>READ_MODE[1]</tt></td><td><tt>RamConfig CBIT_3</tt></td></tr>
+</table>
+</p>
+
+<p>
+The read/write mode selects the width of the read/write port:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>MODE</th><th>DATA Width</th><th>Used WDATA/RDATA Bits</th></tr>
+<tr><td>0</td><td>16</td><td>15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0</td></tr>
+<tr><td>1</td><td>8</td><td>14, 12, 10, 8, 6, 4, 2, 0</td></tr>
+<tr><td>2</td><td>4</td><td>13, 9, 5, 1</td></tr>
+<tr><td>3</td><td>2</td><td>11, 3</td></tr>
+</table>
+</p>
+
+<p>
+The <tt>NegClk</tt> bit in the RAMB tile negates the polarity of the <tt>WCLK</tt> port,
+and the <tt>NegClk</tt> bit in the RAMT  tile negates the polarity of the <tt>RCLK</tt> port.
+</p>
+
+<p>
+A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing
+with the <tt>RDATA</tt> outputs. Each RAMB tile exports its <tt>RDATA[7:0]</tt> outputs and each RAMT tile
+exports its <tt>RDATA[15:8]</tt> outputs via this mechanism.
+</p>
+
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author	Clifford Wolf <clifford@clifford.at>	2015-07-18 13:10:40 +0200
committer	Clifford Wolf <clifford@clifford.at>	2015-07-18 13:10:40 +0200
commit	48154cb6f452d3bdb4da36cc267b4b6c45588dc9 (patch)
tree	3ec3be9ef7e8db1fb7c764ed8202e0215a8eb7c7 /docs
parent	13e63e6b65e044e348356731b55610d02cb308b9 (diff)
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