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| author | Clifford Wolf <clifford@clifford.at> | 2016-12-30 14:29:44 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-12-30 14:29:44 +0100 |
| commit | cd0e6cfa8e594255b9640f644a97d9d549e62093 (patch) | |
| tree | bb89d327db309ab5c82eedbba3420dda01bf32fd /examples | |
| parent | 47d28bff1206fb007238b16fe4ad9fea76970002 (diff) | |
| download | icestorm-cd0e6cfa8e594255b9640f644a97d9d549e62093.tar.gz icestorm-cd0e6cfa8e594255b9640f644a97d9d549e62093.tar.bz2 icestorm-cd0e6cfa8e594255b9640f644a97d9d549e62093.zip | |
Added icestick rs232 demo
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/icestick/.gitignore | 4 | ||||
| -rw-r--r-- | examples/icestick/icestick.pcf | 2 | ||||
| -rw-r--r-- | examples/icestick/rs232demo.v | 59 |
3 files changed, 65 insertions, 0 deletions
diff --git a/examples/icestick/.gitignore b/examples/icestick/.gitignore index c1fa30b..539898f 100644 --- a/examples/icestick/.gitignore +++ b/examples/icestick/.gitignore @@ -2,3 +2,7 @@ example.bin example.blif example.asc example.rpt +rs232demo.bin +rs232demo.blif +rs232demo.asc +rs232demo.rpt diff --git a/examples/icestick/icestick.pcf b/examples/icestick/icestick.pcf index a1693eb..49cb382 100644 --- a/examples/icestick/icestick.pcf +++ b/examples/icestick/icestick.pcf @@ -1,3 +1,5 @@ +set_io --warn-no-port RX 9
+set_io --warn-no-port TX 8
set_io LED1 99
set_io LED2 98
set_io LED3 97
diff --git a/examples/icestick/rs232demo.v b/examples/icestick/rs232demo.v new file mode 100644 index 0000000..fc7a770 --- /dev/null +++ b/examples/icestick/rs232demo.v @@ -0,0 +1,59 @@ +module top ( + input clk, + input RX, + output TX, + output reg LED1, + output reg LED2, + output reg LED3, + output reg LED4, + output reg LED5 +); + parameter integer BAUD_RATE = 9600; + parameter integer CLOCK_FREQ_HZ = 12000000; + localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE); + + reg [9:0] buffer; + reg buffer_valid; + + reg [$clog2(3*HALF_PERIOD):0] cycle_cnt; + reg [3:0] bit_cnt = 0; + reg [0:0] state = 0; + + always @(posedge clk) begin + buffer_valid <= 0; + case (state) + 0: begin + if (!RX) begin + cycle_cnt <= HALF_PERIOD; + bit_cnt <= 0; + state <= 1; + end + end + 1: begin + if (cycle_cnt == 2*HALF_PERIOD) begin + cycle_cnt <= 0; + buffer[bit_cnt] <= RX; + bit_cnt <= bit_cnt + 1; + if (bit_cnt == 9) begin + buffer_valid <= 1; + state <= 0; + end + end else begin + cycle_cnt <= cycle_cnt + 1; + end + end + endcase + end + + always @(posedge clk) begin + if (buffer_valid) begin + if (buffer[8:1] == "1") LED1 <= !LED1; + if (buffer[8:1] == "2") LED2 <= !LED2; + if (buffer[8:1] == "3") LED3 <= !LED3; + if (buffer[8:1] == "4") LED4 <= !LED4; + if (buffer[8:1] == "5") LED5 <= !LED5; + end + end + + assign TX = RX; +endmodule |