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author | Clifford Wolf <clifford@clifford.at> | 2017-11-21 18:19:47 +0100 |
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committer | GitHub <noreply@github.com> | 2017-11-21 18:19:47 +0100 |
commit | 6e9a2da5c46edf00f1dc87c86053b5edbc17d5d7 (patch) | |
tree | b94fdbf6f316b9758e8afd848d8c900343469f07 /icebox/icebox_chipdb.py | |
parent | 9a2a325acb846936431c4aa5843184034be25d5c (diff) | |
parent | 9184fbdf404c0e94326919c92a27d3292994cdf1 (diff) | |
download | icestorm-6e9a2da5c46edf00f1dc87c86053b5edbc17d5d7.tar.gz icestorm-6e9a2da5c46edf00f1dc87c86053b5edbc17d5d7.tar.bz2 icestorm-6e9a2da5c46edf00f1dc87c86053b5edbc17d5d7.zip |
Merge pull request #109 from daveshah1/up5k
Support for new UltraPlus features
Diffstat (limited to 'icebox/icebox_chipdb.py')
-rwxr-xr-x | icebox/icebox_chipdb.py | 53 |
1 files changed, 52 insertions, 1 deletions
diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py index ca7f483..520d884 100755 --- a/icebox/icebox_chipdb.py +++ b/icebox/icebox_chipdb.py @@ -129,7 +129,8 @@ print("""# # .logic_tile X Y # .ramb_tile X Y # .ramt_tile X Y -# +# .dsp[0..3]_tile X Y +# .ipcon_tile X Y # declares the existence of a IO/LOGIC/RAM tile with the given coordinates # # @@ -137,6 +138,8 @@ print("""# # .logic_tile_bits COLUMNS ROWS # .ramb_tile_bits COLUMNS ROWS # .ramt_tile_bits COLUMNS ROWS +# .dsp[0..3]_tile_bits X Y +# .ipcon_tile_bits X Y # FUNCTION_1 CONFIG_BITS_NAMES_1 # FUNCTION_2 CONFIG_BITS_NAMES_2 # ... @@ -145,6 +148,7 @@ print("""# # # # .extra_cell X Y <cell-type> +# .extra_cell X Y Z <cell-type> # KEY MULTI-FIELD-VALUE # .... # @@ -238,6 +242,16 @@ for idx in sorted(ic.ramt_tiles): print(".ramt_tile %d %d" % idx) print() +for dsp_idx in range(4): + for idx in sorted(ic.dsp_tiles[dsp_idx]): + x, y = idx + print(".dsp%d_tile %d %d" % (dsp_idx, x, y)) + print() + +for idx in sorted(ic.ipcon_tiles): + print(".ipcon_tile %d %d" % idx) +print() + def print_tile_nonrouting_bits(tile_type, idx): tx = idx[0] ty = idx[1] @@ -266,6 +280,11 @@ if not mode_384: print_tile_nonrouting_bits("ramb", list(ic.ramb_tiles.keys())[0]) print_tile_nonrouting_bits("ramt", list(ic.ramt_tiles.keys())[0]) +if ic.is_ultra(): + for dsp_idx in range(4): + print_tile_nonrouting_bits("dsp%d" % dsp_idx, list(ic.dsp_tiles[dsp_idx].keys())[0]) + print_tile_nonrouting_bits("ipcon", list(ic.ipcon_tiles.keys())[0]) + print(".extra_cell 0 0 WARMBOOT") for key in sorted(icebox.warmbootinfo_db[ic.device]): print("%s %s" % (key, " ".join([str(k) for k in icebox.warmbootinfo_db[ic.device][key]]))) @@ -285,6 +304,38 @@ for pllid in ic.pll_list(): print("%s %s" % (key, " ".join([str(k) for k in pllinfo[key]]))) print() +for dsploc in ic.dsp_tiles[0]: + x, y = dsploc + print(".extra_cell %d %d 0 MAC16" % dsploc) + nets = ic.get_dsp_nets_db(x, y) + for key in sorted(nets): + print("%s %s" % (key, " ".join([str(k) for k in nets[key]]))) + + cfg = ic.get_dsp_config_db(x, y) + for key in sorted(cfg): + print("%s %s" % (key, " ".join([str(k) for k in cfg[key]]))) + print() + +if ic.device in icebox.extra_cells_db: + for cell in icebox.extra_cells_db[ic.device]: + name, loc = cell + x, y, z = loc + print(".extra_cell %d %d %d %s" % (x, y, z, name)) + cellinfo = icebox.extra_cells_db[ic.device][cell] + for key in sorted(cellinfo): + print("%s %s" % (key, " ".join([str(k) for k in cellinfo[key]]))) + print() + +if ic.device in icebox.spram_db: + for cell in icebox.spram_db[ic.device]: + loc = cell + x, y, z = loc + print(".extra_cell %d %d %d SPRAM" % (x, y, z)) + cellinfo = icebox.spram_db[ic.device][cell] + for key in sorted(cellinfo): + print("%s %s" % (key, " ".join([str(k) for k in cellinfo[key]]))) + print() + print(".extra_bits") extra_bits = dict() for idx in sorted(ic.extra_bits_db()): |