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authorClifford Wolf <clifford@clifford.at>2018-07-20 15:05:46 +0200
committerGitHub <noreply@github.com>2018-07-20 15:05:46 +0200
commit4582202121ef1619105ab02d8b51eba1a6bada60 (patch)
treeddc7552e5c6ecd24dfa91aa24ea4e88fe7caf916 /icebox/icebox_hlc2asc.py
parentd992fc76ae8891b823a61ab0a9d80b109e642a0b (diff)
parent61aa5c5094021dc1e623812fd55c99ff0363b595 (diff)
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Merge pull request #176 from elmsfu/hlc2asc/lut_keyword_fix
icebox_hlc2asc: fix _lut_ keyword parsing
Diffstat (limited to 'icebox/icebox_hlc2asc.py')
-rwxr-xr-xicebox/icebox_hlc2asc.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py
index f80678f..92da928 100755
--- a/icebox/icebox_hlc2asc.py
+++ b/icebox/icebox_hlc2asc.py
@@ -865,7 +865,7 @@ class LogicCell:
self.seq_bits = ['0'] * 4
def read(self, fields):
- if fields[0] == 'lut' and len(fields) == 2 and self.lut_bits is None:
+ if fields[0] == 'lut' and len(fields) == 2:
self.lut_bits = fields[1]
elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=':
m = re.match("([0-9]+)'b([01]+)", fields[2])