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author | Clifford Wolf <clifford@clifford.at> | 2015-07-18 13:07:39 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-07-18 13:07:39 +0200 |
commit | 13e63e6b65e044e348356731b55610d02cb308b9 (patch) | |
tree | 00274273090bec68fc31022b6daef4115290efbb /icebox | |
parent | c41701ca3a2046e9cabe303cff0aa203215d70c1 (diff) | |
download | icestorm-13e63e6b65e044e348356731b55610d02cb308b9.tar.gz icestorm-13e63e6b65e044e348356731b55610d02cb308b9.tar.bz2 icestorm-13e63e6b65e044e348356731b55610d02cb308b9.zip |
Import of icestorm-snapshot-150526.zip
Diffstat (limited to 'icebox')
-rw-r--r-- | icebox/Makefile | 12 | ||||
-rw-r--r-- | icebox/icebox.py | 98 | ||||
-rwxr-xr-x | icebox/icebox_chipdb.py | 113 | ||||
-rwxr-xr-x | icebox/icebox_diff.py | 15 | ||||
-rwxr-xr-x | icebox/icebox_html.py | 2 | ||||
-rw-r--r-- | icebox/iceboxdb.py | 9 |
6 files changed, 225 insertions, 24 deletions
diff --git a/icebox/Makefile b/icebox/Makefile index 3f74e18..64549b3 100644 --- a/icebox/Makefile +++ b/icebox/Makefile @@ -1,7 +1,13 @@ -all: +chipdb: chipdb-1k.txt -install: +chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py + python icebox_chipdb.py > chipdb-1k.new + mv chipdb-1k.new chipdb-1k.txt + +install: chipdb + mkdir -p /usr/local/share/icebox + cp chipdb-1k.txt /usr/local/share/icebox/ cp icebox.py /usr/local/bin/icebox.py cp iceboxdb.py /usr/local/bin/iceboxdb.py cp icebox_chipdb.py /usr/local/bin/icebox_chipdb @@ -20,6 +26,8 @@ uninstall: rm -f /usr/local/bin/icebox_html rm -f /usr/local/bin/icebox_maps rm -f /usr/local/bin/icebox_vlog + rm -f /usr/local/share/icebox/chipdb-1k.txt + -rmdir /usr/local/share/icebox .PHONY: install uninstall diff --git a/icebox/icebox.py b/icebox/icebox.py index 60b5dc2..cad6831 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -32,6 +32,7 @@ class iceconfig: self.io_tiles = dict() self.ramb_tiles = dict() self.ramt_tiles = dict() + self.ram_data = dict() self.extra_bits = set() def setup_empty_1k(self): @@ -78,8 +79,8 @@ class iceconfig: def gbufin_db(self): return gbufin_db[self.device] - def icegate_db(self): - return icegate_db[self.device] + def iolatch_db(self): + return iolatch_db[self.device] def padin_pio_db(self): return padin_pio_db[self.device] @@ -90,6 +91,21 @@ class iceconfig: def ieren_db(self): return ieren_db[self.device] + def colbuf_db(self): + assert self.device == "1k" + entries = list() + for x in range(self.max_x+1): + for y in range(self.max_y+1): + src_y = None + if 0 <= y <= 4: src_y = 4 + if 5 <= y <= 8: src_y = 5 + if 9 <= y <= 12: src_y = 12 + if 13 <= y <= 17: src_y = 13 + if x in [3, 10] and src_y == 4: src_y = 3 + if x in [3, 10] and src_y == 12: src_y = 11 + entries.append((x, src_y, x, y)) + return entries + def tile_db(self, x, y): if x == 0: return iotile_l_db if y == 0: return iotile_b_db @@ -307,7 +323,7 @@ class iceconfig: neighbours.add((s[0], s[1], s[2])) return neighbours - def group_segments(self, all_from_tiles=set(), extra_connections=list(), extra_segments=list()): + def group_segments(self, all_from_tiles=set(), extra_connections=list(), extra_segments=list(), connect_gb=True): seed_segments = set() seen_segments = set() connected_segments = dict() @@ -373,7 +389,7 @@ class iceconfig: seed_segments.add(s1) seed_segments.add(s2) - for entry in self.icegate_db(): + for entry in self.iolatch_db(): if entry[0] == 0 or entry[0] == self.max_x: iocells = [(entry[0], i) for i in range(1, self.max_y)] if entry[1] == 0 or entry[1] == self.max_y: @@ -388,14 +404,15 @@ class iceconfig: seed_segments.add(s1) seed_segments.add(s2) - for entry in self.gbufin_db(): - s1 = (entry[0], entry[1], "wire_gbuf/in") - s2 = (entry[0], entry[1], "glb_netwk_%d" % entry[2]) - if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles: - connected_segments.setdefault(s1, set()).add(s2) - connected_segments.setdefault(s2, set()).add(s1) - seed_segments.add(s1) - seed_segments.add(s2) + if connect_gb: + for entry in self.gbufin_db(): + s1 = (entry[0], entry[1], "wire_gbuf/in") + s2 = (entry[0], entry[1], "glb_netwk_%d" % entry[2]) + if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles: + connected_segments.setdefault(s1, set()).add(s2) + connected_segments.setdefault(s2, set()).add(s1) + seed_segments.add(s1) + seed_segments.add(s2) while seed_segments: queue = set() @@ -444,7 +461,7 @@ class iceconfig: if line[0][0] != ".": if expected_data_lines == -1: continue - if line[0][0] != "0" and line[0][0] != "1": + if line[0][0] not in "0123456789abcdef": print("%sWarning: ignoring data block in line %d: %s" % (logprefix, linenum, linetext.strip())) expected_data_lines = 0 continue @@ -453,7 +470,7 @@ class iceconfig: expected_data_lines -= 1 continue assert expected_data_lines <= 0 - if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile"): + if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data"): current_data = list() expected_data_lines = 16 self.max_x = max(self.max_x, int(line[1])) @@ -470,6 +487,9 @@ class iceconfig: if line[0] == ".ramt_tile": self.ramt_tiles[(int(line[1]), int(line[2]))] = current_data continue + if line[0] == ".ram_data": + self.ram_data[(int(line[1]), int(line[2]))] = current_data + continue if line[0] == ".extra_bit": self.extra_bits.add((int(line[1]), int(line[2]), int(line[3]))) continue @@ -481,6 +501,7 @@ class iceconfig: expected_data_lines = -1 continue print("%sWarning: ignoring line %d: %s" % (logprefix, linenum, linetext.strip())) + expected_data_lines = -1 class tileconfig: def __init__(self, tile): @@ -905,7 +926,7 @@ gbufin_db = { ] } -icegate_db = { +iolatch_db = { "1k": [ ( 0, 7), (13, 10), @@ -914,6 +935,39 @@ icegate_db = { ] } +pllinfo_db = { + "1k": { + "SHIFTREG_DIV_MODE": (0, 3, "B2[2]"), + "FDA_FEEDBACK_0": (0, 3, "B7[3]"), + "FDA_FEEDBACK_1": (0, 4, "B0[2]"), + "FDA_FEEDBACK_2": (0, 4, "B0[3]"), + "FDA_FEEDBACK_3": (0, 4, "B3[3]"), + "FDA_RELATIVE_0": (0, 4, "B2[3]"), + "FDA_RELATIVE_1": (0, 4, "B5[3]"), + "FDA_RELATIVE_2": (0, 4, "B4[2]"), + "FDA_RELATIVE_3": (0, 4, "B4[3]"), + "DIVR_0": (0, 1, "B0[2]"), + "DIVR_1": (0, 1, "B0[3]"), + "DIVR_2": (0, 1, "B3[3]"), + "DIVR_3": (0, 1, "B2[2]"), + "DIVF_0": (0, 1, "B2[3]"), + "DIVF_1": (0, 1, "B5[3]"), + "DIVF_2": (0, 1, "B4[2]"), + "DIVF_3": (0, 1, "B4[3]"), + "DIVF_4": (0, 1, "B7[3]"), + "DIVF_5": (0, 2, "B0[2]"), + "DIVF_6": (0, 2, "B0[3]"), + "DIVQ_0": (0, 0, "?"), + "DIVQ_1": (0, 0, "?"), + "DIVQ_2": (0, 0, "?"), + "FILTER_RANGE_0": (0, 2, "B5[3]"), + "FILTER_RANGE_1": (0, 2, "B4[2]"), + "FILTER_RANGE_2": (0, 2, "B4[3]"), + "ENABLE_ICEGATE": (0, 0, "?"), + "TEST_MODE": (0, 3, "B4[3]"), + } +} + padin_pio_db = { "1k": [ (13, 8, 1), # glb_netwk_0 @@ -941,6 +995,8 @@ ieren_db = { ( 0, 10, 1, 0, 10, 0), ( 0, 10, 0, 0, 10, 1), ( 0, 9, 1, 0, 9, 0), + ( 0, 9, 0, 0, 9, 1), + ( 0, 8, 1, 0, 8, 0), ( 0, 8, 0, 0, 8, 1), ( 0, 6, 1, 0, 6, 0), ( 0, 6, 0, 0, 6, 1), @@ -954,6 +1010,7 @@ ieren_db = { ( 0, 2, 0, 0, 2, 1), ( 1, 0, 0, 1, 0, 0), ( 1, 0, 1, 1, 0, 1), + ( 2, 0, 0, 2, 0, 0), ( 2, 0, 1, 2, 0, 1), ( 3, 0, 0, 3, 0, 0), ( 3, 0, 1, 3, 0, 1), @@ -961,6 +1018,8 @@ ieren_db = { ( 4, 0, 1, 4, 0, 1), ( 5, 0, 0, 5, 0, 0), ( 5, 0, 1, 5, 0, 1), + ( 6, 0, 1, 6, 0, 0), + ( 7, 0, 0, 6, 0, 1), ( 6, 0, 0, 7, 0, 0), ( 7, 0, 1, 7, 0, 1), ( 8, 0, 0, 8, 0, 0), @@ -969,6 +1028,10 @@ ieren_db = { ( 9, 0, 1, 9, 0, 1), (10, 0, 0, 10, 0, 0), (10, 0, 1, 10, 0, 1), + (11, 0, 0, 11, 0, 0), + (11, 0, 1, 11, 0, 1), + (12, 0, 0, 12, 0, 0), + (12, 0, 1, 12, 0, 1), (13, 1, 0, 13, 1, 0), (13, 1, 1, 13, 1, 1), (13, 2, 0, 13, 2, 0), @@ -981,10 +1044,13 @@ ieren_db = { (13, 7, 0, 13, 7, 0), (13, 7, 1, 13, 7, 1), (13, 8, 0, 13, 8, 0), + (13, 8, 1, 13, 8, 1), + (13, 9, 0, 13, 9, 0), (13, 9, 1, 13, 9, 1), (13, 11, 0, 13, 10, 0), (13, 11, 1, 13, 10, 1), (13, 12, 0, 13, 11, 0), + (13, 12, 1, 13, 11, 1), (13, 13, 0, 13, 13, 0), (13, 13, 1, 13, 13, 1), (13, 14, 0, 13, 14, 0), @@ -1002,6 +1068,8 @@ ieren_db = { ( 8, 17, 1, 8, 17, 1), ( 8, 17, 0, 8, 17, 0), ( 7, 17, 1, 7, 17, 1), + ( 7, 17, 0, 7, 17, 0), + ( 6, 17, 1, 6, 17, 1), ( 5, 17, 1, 5, 17, 1), ( 5, 17, 0, 5, 17, 0), ( 4, 17, 1, 4, 17, 1), diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py index 12ccfa8..c673f54 100755 --- a/icebox/icebox_chipdb.py +++ b/icebox/icebox_chipdb.py @@ -40,16 +40,44 @@ print("""# # Quick File Format Reference: # ---------------------------- # -# .device DEVICE +# .device DEVICE WIDTH HEIGHT NUM_NETS # # declares the device type (e.g. "1k") # # # .pins PACKAGE -# PIN_NUM TILE_X TILE_Y PIO_NUM PADIN_NUM +# PIN_NUM TILE_X TILE_Y PIO_NUM GLB_NUM # ... # -# associates a package pin with an IO tile and block +# associates a package pin with an IO tile and block, and global network +# +# +# .gbufin +# TILE_X TILE_Y GLB_NUM +# ... +# +# associates an IO tile with the global network it drives via wire_gbuf/in +# +# +# .iolatch +# TILE_X TILE_Y +# ... +# +# specifies the IO tiles that drive the latch signal for the bank via wire_gbuf/in +# +# +# .ieren +# PIO_TILE_X PIO_TILE_Y PIO_NUM IEREN_TILE_X IEREN_TILE_Y IEREN_NUM +# ... +# +# associates an IO block with an IeRen-block +# +# +# .colbuf +# SOURCE_TILE_X SOURCE_TILE_Y DEST_TILE_X DEST_TILE_Y +# ... +# +# declares the positions of the column buffers # # # .io_tile X Y @@ -60,6 +88,24 @@ print("""# # declares the existence of a IO/LOGIC/RAM tile with the given coordinates # # +# .io_tile_bits COLUMNS ROWS +# .logic_tile_bits COLUMNS ROWS +# .ramb_tile_bits COLUMNS ROWS +# .ramt_tile_bits COLUMNS ROWS +# FUNCTION_1 CONFIG_BITS_NAMES_1 +# FUNCTION_2 CONFIG_BITS_NAMES_2 +# ... +# +# declares non-routing configuration bits of IO/LOGIC/RAM tiles +# +# +# .extra_bits +# FUNCTION BANK_NUM ADDR_X ADDR_Y +# ... +# +# declares non-routing global configuration bits +# +# # .net NET_INDEX # X1 Y1 name1 # X2 Y2 name2 @@ -85,7 +131,9 @@ print("""# # """) -print(".device 1k") +all_group_segments = ic.group_segments(all_tiles, connect_gb=False) + +print(".device 1k %d %d %d" % (ic.max_x+1, ic.max_y+1, len(all_group_segments))) print() print(".pins tq144") @@ -97,6 +145,26 @@ for entry in sorted(ic.pinloc_db()): print("%d %d %d %d %d" % tuple(entry + [pio_to_padin[pio] if pio in pio_to_padin else -1])) print() +print(".gbufin") +for entry in sorted(ic.gbufin_db()): + print(" ".join(["%d" % k for k in entry])) +print() + +print(".iolatch") +for entry in sorted(ic.iolatch_db()): + print(" ".join(["%d" % k for k in entry])) +print() + +print(".ieren") +for entry in sorted(ic.ieren_db()): + print(" ".join(["%d" % k for k in entry])) +print() + +print(".colbuf") +for entry in sorted(ic.colbuf_db()): + print(" ".join(["%d" % k for k in entry])) +print() + for idx in sorted(ic.io_tiles): print(".io_tile %d %d" % idx) print() @@ -113,7 +181,42 @@ for idx in sorted(ic.ramt_tiles): print(".ramt_tile %d %d" % idx) print() -for group in sorted(ic.group_segments(all_tiles)): +def print_tile_nonrouting_bits(tile_type, idx): + tx = idx[0] + ty = idx[1] + + tile = ic.tile(tx, ty) + + print(".%s_tile_bits %d %d" % (tile_type, len(tile[0]), len(tile))) + + function_bits = dict() + for entry in ic.tile_db(tx, ty): + if not ic.tile_has_entry(tx, ty, entry): + continue + if entry[1] in ("routing", "buffer"): + continue + + func = ".".join(entry[1:]) + function_bits[func] = entry[0] + + for x in sorted(function_bits): + print(" ".join([x] + function_bits[x])) + print() + +print_tile_nonrouting_bits("logic", ic.logic_tiles.keys()[0]) +print_tile_nonrouting_bits("io", ic.io_tiles.keys()[0]) +print_tile_nonrouting_bits("ramb", ic.ramb_tiles.keys()[0]) +print_tile_nonrouting_bits("ramt", ic.ramt_tiles.keys()[0]) + +print(".extra_bits") +extra_bits = dict() +for idx in sorted(ic.extra_bits_db()): + extra_bits[".".join(ic.extra_bits_db()[idx])] = " ".join(["%d" % k for k in idx]) +for idx in sorted(extra_bits): + print("%s %s" % (idx, extra_bits[idx])) +print() + +for group in sorted(all_group_segments): netidx = len(net_to_segs) net_to_segs.append(group) print(".net %d" % netidx) diff --git a/icebox/icebox_diff.py b/icebox/icebox_diff.py index da7962b..59fa0a8 100755 --- a/icebox/icebox_diff.py +++ b/icebox/icebox_diff.py @@ -29,6 +29,17 @@ print("Reading file '%s'.." % sys.argv[2]) ic2 = icebox.iceconfig() ic2.read_file(sys.argv[2]) +def format_bits(line_nr, this_line, other_line): + text = "" + for i in range(len(this_line)): + if this_line[i] != other_line[i]: + if this_line[i] == "1": + text += "%8s" % ("B%d[%d]" % (line_nr, i)) + else: + text += "%8s" % "" + return text + + def diff_tiles(stmt, tiles1, tiles2): for i in sorted(set(tiles1.keys() + tiles2.keys())): if not i in tiles1: @@ -48,8 +59,8 @@ def diff_tiles(stmt, tiles1, tiles2): if tiles1[i][c] == tiles2[i][c]: print(" %s" % tiles1[i][c]) else: - print("- %s" % tiles1[i][c]) - print("+ %s" % tiles2[i][c]) + print("- %s%s" % (tiles1[i][c], format_bits(c, tiles1[i][c], tiles2[i][c]))) + print("+ %s%s" % (tiles2[i][c], format_bits(c, tiles2[i][c], tiles1[i][c]))) diff_tiles(".io_tile", ic1.io_tiles, ic2.io_tiles) diff_tiles(".logic_tile", ic1.logic_tiles, ic2.logic_tiles) diff --git a/icebox/icebox_html.py b/icebox/icebox_html.py index 880714f..d3779ab 100755 --- a/icebox/icebox_html.py +++ b/icebox/icebox_html.py @@ -218,6 +218,8 @@ configuration bits it has and how it is connected to its neighbourhood.</p>""" % bitmap_cells[idx1][idx2]["label"] = "A" elif entry[1].startswith("RamConfig"): bitmap_cells[idx1][idx2]["label"] = "M" + elif entry[1].startswith("PLL"): + bitmap_cells[idx1][idx2]["label"] = "P" else: assert False bitmap_cells[idx1][idx2]["label"] = '<a style="color:#666; text-decoration:none" href="#B.%d.%d">%s</a>' % (idx1, idx2, bitmap_cells[idx1][idx2]["label"]) diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index 2159b8d..52aa3d0 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -26,6 +26,15 @@ B8[2] IoCtrl LVDS B6[2] IoCtrl REN_0 B1[3] IoCtrl REN_1 B9[13],B15[13] NegClk +B0[2] PLL pll_cf_bit_1 +B0[3] PLL pll_cf_bit_2 +B3[3] PLL pll_cf_bit_3 +B2[2] PLL pll_cf_bit_4 +B2[3] PLL pll_cf_bit_5 +B5[3] PLL pll_cf_bit_6 +B4[2] PLL pll_cf_bit_7 +B4[3] PLL pll_cf_bit_8 +B7[3] PLL pll_cf_bit_9 B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnl_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnl_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_B.logic_op_tnl_1 lc_trk_g0_1 |