Trace DSP routing

4 files changed, 6531 insertions, 349 deletions

diff --git a/icebox/icebox.py b/icebox/icebox.py
index fde97dc..f27d749 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -31,6 +31,8 @@ class iceconfig:
         self.io_tiles = dict()
         self.ramb_tiles = dict()
         self.ramt_tiles = dict()
+        self.dsp_tiles = [dict() for i in range(4)]
+        self.ipcon_tiles = dict()
         self.ram_data = dict()
         self.extra_bits = set()
         self.symbols = dict()
@@ -96,7 +98,18 @@ class iceconfig:
         for x in range(1, self.max_x):
             self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)]
             self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)]
-
+        for x in [0, self.max_x]:
+            for y in range(1, self.max_y):
+                if y in [5, 10, 15, 23]:
+                    self.dsp_tiles[0][(x, y)] = ["0" * 54 for i in range(16)]
+                elif y in [6, 11, 16, 24]:
+                    self.dsp_tiles[1][(x, y)] = ["0" * 54 for i in range(16)]
+                elif y in [7, 12, 17, 25]:
+                    self.dsp_tiles[2][(x, y)] = ["0" * 54 for i in range(16)]
+                elif y in [8, 13, 18, 26]:
+                    self.dsp_tiles[3][(x, y)] = ["0" * 54 for i in range(16)]
+                else:
+                    self.ipcon_tiles[(x, y)] = ["0" * 54 for i in range(16)]
     def setup_empty_8k(self):
         self.clear()
         self.device = "8k"
@@ -132,6 +145,9 @@ class iceconfig:
         if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)]
         if (x, y) in self.ramb_tiles: return self.ramb_tiles[(x, y)]
         if (x, y) in self.ramt_tiles: return self.ramt_tiles[(x, y)]
+        for i in range(4):
+            if (x, y) in self.dsp_tiles[i]: return self.dsp_tiles[i][(x, y)]
+        if (x, y) in self.ipcon_tiles: return self.ipcon_tiles[(x, y)]            
         return None
 
     def pinloc_db(self):
@@ -242,6 +258,12 @@ class iceconfig:
             if (x, y) in self.logic_tiles: return logictile_5k_db
             if (x, y) in self.ramb_tiles: return rambtile_5k_db
             if (x, y) in self.ramt_tiles: return ramttile_5k_db
+            if (x, y) in self.ipcon_tiles: return ipcon_5k_db
+            if (x, y) in self.dsp_tiles[0]: return dsp0_5k_db
+            if (x, y) in self.dsp_tiles[1]: return dsp1_5k_db
+            if (x, y) in self.dsp_tiles[2]: return dsp2_5k_db
+            if (x, y) in self.dsp_tiles[3]: return dsp3_5k_db
+
         elif self.device == "8k":
             if (x, y) in self.logic_tiles: return logictile_8k_db
             if (x, y) in self.ramb_tiles: return rambtile_8k_db
@@ -253,13 +275,24 @@ class iceconfig:
         assert False
 
     def tile_type(self, x, y):
-        if x == 0: return "IO"
+        if x == 0 and self.device != "5k": return "IO"
         if y == 0: return "IO"
-        if x == self.max_x: return "IO"
+        if x == self.max_x and self.device != "5k": return "IO"
         if y == self.max_y: return "IO"
         if (x, y) in self.ramb_tiles: return "RAMB"
         if (x, y) in self.ramt_tiles: return "RAMT"
         if (x, y) in self.logic_tiles: return "LOGIC"
+        if (x == 0 or x == self.max_x) and self.device == "5k":
+            if y in [5, 10, 15, 23]:
+                return "DSP0"
+            elif y in [6, 11, 16, 24]:
+                return "DSP1"
+            elif y in [7, 12, 17, 25]:
+                return "DSP2"
+            elif y in [8, 13, 18, 26]:
+                return "DSP3"
+            else:
+                return "IPCON"
         assert False
 
     def tile_pos(self, x, y):
@@ -307,11 +340,17 @@ class iceconfig:
         return pos_has_net(self.tile_pos(x, y), netname)
 
     def tile_follow_net(self, x, y, direction, netname):
-        if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname)
-        if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname)
-        if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname)
-        if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname)
-        return pos_follow_net(self.tile_pos(x, y), direction, netname)
+        if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname, self.device)
+        if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname, self.device)
+        if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname, self.device)
+        if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname, self.device)
+        if self.device == "5k":
+            if y == 1 and x in (0, self.max_x) and direction == 'b': return pos_follow_net(self.tile_pos(x, y), "B", netname, self.device)
+            if y == self.max_y-1 and x in (0, self.max_x) and direction == 't': return pos_follow_net(self.tile_pos(x, y), "T", netname, self.device)
+            if x == 1 and y in (0, self.max_y) and direction == 'l': return pos_follow_net(self.tile_pos(x, y), "L", netname, self.device)
+            if x == self.max_x-1 and y in (0, self.max_y) and direction == 'r': return pos_follow_net(self.tile_pos(x, y), "R", netname, self.device)
+
+        return pos_follow_net(self.tile_pos(x, y), direction, netname, self.device)
 
     def follow_funcnet(self, x, y, func):
         neighbours = set()
@@ -340,6 +379,9 @@ class iceconfig:
             if npos == "x":
                 if (nx, ny) in self.logic_tiles:
                     return (nx, ny, "lutff_%d/out" % func)
+                for i in range(4):
+                    if (nx, ny) in self.dsp_tiles[i]: #TODO: check this
+                        return (nx, ny, "mult/O_%d" % (i * 8 + func))
                 if (nx, ny) in self.ramb_tiles:
                     if self.device == "1k":
                         return (nx, ny, "ram/RDATA_%d" % func)
@@ -423,12 +465,12 @@ class iceconfig:
                         neighbours.add((nx, ny, netname))
 
         match = re.match(r"sp4_r_v_b_(\d+)", netname)
-        if match and 0 < x < self.max_x-1:
+        if match and ((0 < x < self.max_x-1) or (self.device == "5k")):
             neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1))))
         #print('\tafter r_v_b', neighbours)
 
         match = re.match(r"sp4_v_[bt]_(\d+)", netname)
-        if match and 1 < x < self.max_x:
+        if match and (1 < x < self.max_x or ((self.device == "5k") and (x > 0))):
             n = sp4v_normalize(netname, "b")
             if n is not None:
                 n = n.replace("sp4_", "sp4_r_")
@@ -459,9 +501,19 @@ class iceconfig:
 
                 if s[0] in (0, self.max_x) and s[1] in (0, self.max_y):
                     if re.match("span4_(vert|horz)_[lrtb]_\d+$", n):
+                        
                         vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_")
                         horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_")
-
+                        
+                        if self.device == "5k":
+                            m = re.match("span4_vert_([lrtb])_(\d+)$", vert_net)
+                            assert m
+                            vert_net = "sp4_v_%s_%d" % (m.group(1), int(m.group(2)) + 28)
+
+                            m = re.match("span4_horz_([lrtb])_(\d+)$", horz_net)
+                            assert m
+                            horz_net = "span4_horz_%s_%d" % (m.group(1), int(m.group(2)) - 28)
+                            
                         if s[0] == 0 and s[1] == 0:
                             if direction == "l": s = (0, 1, vert_net)
                             if direction == "b": s = (1, 0, horz_net)
@@ -470,9 +522,18 @@ class iceconfig:
                             if direction == "r": s = (self.max_x, self.max_y-1, vert_net)
                             if direction == "t": s = (self.max_x-1, self.max_y, horz_net)
 
-                        vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_")
-                        horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_")
-
+                        vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_").replace("_h_", "_v_")
+                        horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_").replace("_v_", "_h_")
+
+                        if self.device == "5k":
+                            m = re.match("(span4_vert|sp4_v)_([lrtb])_(\d+)$", vert_net)
+                            assert m
+                            vert_net = "sp4_v_%s_%d" % (m.group(2), int(m.group(3)) + 28)
+                            
+                            m = re.match("(span4_horz|sp4_h)_([lrtb])_(\d+)$", horz_net)
+                            assert m
+                            horz_net = "span4_horz_%s_%d" % (m.group(2), int(m.group(3)) - 28)
+                            
                         if s[0] == 0 and s[1] == self.max_y:
                             if direction == "l": s = (0, self.max_y-1, vert_net)
                             if direction == "t": s = (1, self.max_y, horz_net)
@@ -566,7 +627,22 @@ class iceconfig:
                 add_seed_segments(idx, tile, ramttile_8k_db)
             else:
                 assert False
-
+        
+        for idx, tile in self.dsp_tiles[0].items():
+            if self.device == "5k":
+                add_seed_segments(idx, tile, dsp0_5k_db)
+        for idx, tile in self.dsp_tiles[1].items():
+            if self.device == "5k":
+                add_seed_segments(idx, tile, dsp1_5k_db)        
+        for idx, tile in self.dsp_tiles[2].items():
+            if self.device == "5k":
+                add_seed_segments(idx, tile, dsp2_5k_db)    
+        for idx, tile in self.dsp_tiles[3].items():
+            if self.device == "5k":
+                add_seed_segments(idx, tile, dsp3_5k_db)    
+        for idx, tile in self.ipcon_tiles.items():
+            if self.device == "5k":
+                add_seed_segments(idx, tile, ipcon_5k_db)                            
         for padin, pio in enumerate(self.padin_pio_db()):
             s1 = (pio[0], pio[1], "padin_%d" % pio[2])
             s2 = (pio[0], pio[1], "glb_netwk_%d" % padin)
@@ -661,7 +737,7 @@ class iceconfig:
                     expected_data_lines -= 1
                     continue
                 assert expected_data_lines <= 0
-                if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data", ".ipconn_tile", ".dsp1_tile", ".dsp2_tile", ".dsp3_tile", ".dsp4_tile"):
+                if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data", ".ipcon_tile", ".dsp0_tile", ".dsp1_tile", ".dsp2_tile", ".dsp3_tile"):
                     current_data = list()
                     expected_data_lines = 16
                     self.max_x = max(self.max_x, int(line[1]))
@@ -678,6 +754,13 @@ class iceconfig:
                 if line[0] == ".ramt_tile":
                     self.ramt_tiles[(int(line[1]), int(line[2]))] = current_data
                     continue
+                if line[0] == ".ipcon_tile":
+                    self.ipcon_tiles[(int(line[1]), int(line[2]))] = current_data
+                    continue
+                match = re.match(r".dsp(\d)_tile", line[0])
+                if match:
+                    self.dsp_tiles[int(match.group(1))][(int(line[1]), int(line[2]))] = current_data
+                    continue
                 if line[0] == ".ram_data":
                     self.ram_data[(int(line[1]), int(line[2]))] = current_data
                     continue
@@ -862,6 +945,8 @@ def netname_normalize(netname, edge="", ramb=False, ramt=False, ramb_8k=False, r
     netname = netname.replace("lc_", "lutff_")
     netname = netname.replace("wire_logic_cluster/", "")
     netname = netname.replace("wire_io_cluster/", "")
+    netname = netname.replace("wire_mult/", "")
+    netname = netname.replace("wire_con_box/", "")
     netname = netname.replace("wire_bram/", "")
     if (ramb or ramt or ramb_8k or ramt_8k) and netname.startswith("input"):
         match = re.match(r"input(\d)_(\d)", netname)
@@ -890,13 +975,13 @@ def pos_has_net(pos, netname):
         if re.search(r"_vert_[bt]_\d+$", netname): return False
     return True
 
-def pos_follow_net(pos, direction, netname):
-    if pos == "x":
+def pos_follow_net(pos, direction, netname, device):
+    if pos == "x" or ((pos in ("l", "r")) and (device == "5k")):
             m = re.match("sp4_h_[lr]_(\d+)$", netname)
             if m and direction in ("l", "L"):
                 n = sp4h_normalize(netname, "l")
                 if n is not None:
-                    if direction == "l":
+                    if direction == "l" or device == "5k":
                         n = re.sub("_l_", "_r_", n)
                         n = sp4h_normalize(n)
                     else:
@@ -906,7 +991,7 @@ def pos_follow_net(pos, direction, netname):
             if m and direction in ("r", "R"):
                 n = sp4h_normalize(netname, "r")
                 if n is not None:
-                    if direction == "r":
+                    if direction == "r" or device == "5k":
                         n = re.sub("_r_", "_l_", n)
                         n = sp4h_normalize(n)
                     else:
@@ -916,6 +1001,8 @@ def pos_follow_net(pos, direction, netname):
 
             m = re.match("sp4_v_[tb]_(\d+)$", netname)
             if m and direction in ("t", "T"):
+                if device == "5k" and direction == "T" and pos in ("l", "r"):
+                    return re.sub("sp4_v_", "span4_vert_", netname)
                 n = sp4v_normalize(netname, "t")
                 if n is not None:
                     if direction == "t":
@@ -926,6 +1013,8 @@ def pos_follow_net(pos, direction, netname):
                         n = re.sub("sp4_v_", "span4_vert_", n)
                     return n
             if m and direction in ("b", "B"):
+                if device == "5k" and direction == "B" and pos in ("l", "r"):
+                    return re.sub("sp4_v_", "span4_vert_", netname)
                 n = sp4v_normalize(netname, "b")
                 if n is not None:
                     if direction == "b":
@@ -940,7 +1029,7 @@ def pos_follow_net(pos, direction, netname):
             if m and direction in ("l", "L"):
                 n = sp12h_normalize(netname, "l")
                 if n is not None:
-                    if direction == "l":
+                    if direction == "l" or device == "5k":
                         n = re.sub("_l_", "_r_", n)
                         n = sp12h_normalize(n)
                     else:
@@ -950,7 +1039,7 @@ def pos_follow_net(pos, direction, netname):
             if m and direction in ("r", "R"):
                 n = sp12h_normalize(netname, "r")
                 if n is not None:
-                    if direction == "r":
+                    if direction == "r" or device == "5k":
                         n = re.sub("_r_", "_l_", n)
                         n = sp12h_normalize(n)
                     else:
@@ -980,7 +1069,7 @@ def pos_follow_net(pos, direction, netname):
                         n = re.sub("sp12_v_", "span12_vert_", n)
                     return n
 
-    if pos in ("l", "r" ):
+    if (pos in ("l", "r" )) and (device != "5k"):
         m = re.match("span4_vert_([bt])_(\d+)$", netname)
         if m:
             case, idx = direction + m.group(1), int(m.group(2))
@@ -997,6 +1086,8 @@ def pos_follow_net(pos, direction, netname):
         m = re.match("span4_horz_([rl])_(\d+)$", netname)
         if m:
             case, idx = direction + m.group(1), int(m.group(2))
+            if direction == "L" or direction == "R":
+                return netname
             if case == "ll":
                 return "span4_horz_r_%d" % idx
             if case == "lr" and idx >= 4:
@@ -4179,6 +4270,13 @@ ramttile_5k_db = parse_db(iceboxdb.database_ramt_5k_txt, "5k")
 rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, "8k")
 ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, "8k")
 
+ipcon_5k_db = parse_db(iceboxdb.database_ipcon_5k_txt, "5k")
+dsp0_5k_db = parse_db(iceboxdb.database_dsp0_5k_txt, "5k")
+dsp1_5k_db = parse_db(iceboxdb.database_dsp1_5k_txt, "5k")
+dsp2_5k_db = parse_db(iceboxdb.database_dsp2_5k_txt, "5k")
+dsp3_5k_db = parse_db(iceboxdb.database_dsp3_5k_txt, "5k")
+
+
 iotile_l_db = list()
 iotile_r_db = list()
 iotile_t_db = list()
@@ -4232,7 +4330,7 @@ iotile_b_5k_db.append([["B15[14]"], "IoCtrl", "padeb_test_0"])
 iotile_b_5k_db.append([["B6[15]"], "IoCtrl", "cf_bit_35"])
 iotile_b_5k_db.append([["B12[15]"], "IoCtrl", "cf_bit_39"])
 
-for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db]:
+for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db, dsp0_5k_db, dsp1_5k_db, dsp2_5k_db, dsp3_5k_db, ipcon_5k_db]:
     for entry in db:
         if entry[1] in ("buffer", "routing"):
             entry[2] = netname_normalize(entry[2],
diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py
index 50cce09..3b9875f 100755
--- a/icebox/icebox_explain.py
+++ b/icebox/icebox_explain.py
@@ -166,6 +166,13 @@ for idx in ic.ramb_tiles:
 for idx in ic.ramt_tiles:
     print_tile(".ramt_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramt_tiles[idx], ic.tile_db(idx[0], idx[1]))
 
+for i in range(4):
+    for idx in ic.dsp_tiles[i]:
+        print_tile(".dsp%d_tile %d %d" % (i, idx[0], idx[1]), ic, idx[0], idx[1], ic.dsp_tiles[i][idx], ic.tile_db(idx[0], idx[1]))
+
+for idx in ic.ipcon_tiles:
+    print_tile(".ipcon_tile %d %d" % idx, ic, idx[0], idx[1], ic.ipcon_tiles[idx], ic.tile_db(idx[0], idx[1]))
+
 for bit in ic.extra_bits:
     print()
     print(".extra_bit %d %d %d" % bit)
diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py
index 1b19d10..8f6bf7c 100755
--- a/icebox/icebox_vlog.py
+++ b/icebox/icebox_vlog.py
@@ -136,6 +136,7 @@ text_wires = list()
 text_ports = list()
 
 luts_queue = set()
+special_5k_queue = set()
 text_func = list()
 failed_drivers_check = list()
 
@@ -315,7 +316,11 @@ for segs in sorted(ic.group_segments(extra_connections=extra_connections, extra_
 
         match =  re.match("lutff_(\d+)/", s[2])
         if match:
-            luts_queue.add((s[0], s[1], int(match.group(1))))
+            #IpCon and DSP tiles look like logic tiles, but aren't.
+            if ic.device == "5k" and (s[0] == 0 or s[0] == ic.max_x):
+                special_5k_queue.add((s[0], s[1]))
+            else:
+                luts_queue.add((s[0], s[1], int(match.group(1))))
 
     nets[n] = segs
 
@@ -752,6 +757,28 @@ for tile in ic.ramb_tiles:
         text_func.append(");")
         text_func.append("")
 
+for i in range(4):
+    for tile in ic.dsp_tiles[i]:
+        if tile in special_5k_queue:
+            #TODO: print config
+            x = tile[0]
+            y = tile[1]
+            net_clk = seg_to_net((x, y, "lutff_global/clk"), "1'b0")
+            net_sr  = seg_to_net((x, y, "lutff_global/s_r"), "1'b0")
+            #TEMP: for tracing only
+            text_func.append("/* DSP%d   %2d %2d */ assign dsp%d_%d_%d_clk = %s;" % (i, x, y, i, x, y, net_clk))
+            text_func.append("/* DSP%d   %2d %2d */ assign dsp%d_%d_%d_sr = %s;" % (i, x, y, i, x, y, net_sr))
+            for j in range(7):
+                net_in0 = seg_to_net((x, y, "lutff_%d/in_0" % j), "1'b0")
+                net_in1 = seg_to_net((x, y, "lutff_%d/in_1" % j), "1'b0")
+                net_in2 = seg_to_net((x, y, "lutff_%d/in_2" % j), "1'b0")
+                net_in3 = seg_to_net((x, y, "lutff_%d/in_3" % j), "1'b0")
+                #TODO: cin, cout
+                text_func.append("/* DSP%d   %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_0 = %s;" % (i, x, y, j, i, x, y, j, net_in0))
+                text_func.append("/* DSP%d   %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_1 = %s;" % (i, x, y, j, i, x, y, j, net_in1))
+                text_func.append("/* DSP%d   %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_2 = %s;" % (i, x, y, j, i, x, y, j, net_in2))
+                text_func.append("/* DSP%d   %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_3 = %s;" % (i, x, y, j, i, x, y, j, net_in3))
+
 wire_to_reg = set()
 lut_assigns = list()
 const_assigns = list()
diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py
index 6da43c9..a8b6990 100644
--- a/icebox/iceboxdb.py
+++ b/icebox/iceboxdb.py
@@ -5329,7 +5329,15 @@ B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
 !B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
 B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
 """
-database_ramb_5k_txt = """
+database_ipcon_5k_txt = """
+B0[50]	Cascade	IPCON_LC00_inmux02_5
+B2[50]	Cascade	IPCON_LC01_inmux02_5
+B4[50]	Cascade	IPCON_LC02_inmux02_5
+B6[50]	Cascade	IPCON_LC03_inmux02_5
+B8[50]	Cascade	IPCON_LC04_inmux02_5
+B10[50]	Cascade	IPCON_LC05_inmux02_5
+B12[50]	Cascade	IPCON_LC06_inmux02_5
+B14[50]	Cascade	IPCON_LC07_inmux02_5
 B9[7]	ColBufCtrl	8k_glb_netwk_0
 B8[7]	ColBufCtrl	8k_glb_netwk_1
 B11[7]	ColBufCtrl	8k_glb_netwk_2
@@ -5338,8 +5346,22 @@ B13[7]	ColBufCtrl	8k_glb_netwk_4
 B12[7]	ColBufCtrl	8k_glb_netwk_5
 B15[7]	ColBufCtrl	8k_glb_netwk_6
 B14[7]	ColBufCtrl	8k_glb_netwk_7
-B0[0]	NegClk
-B1[7]	RamConfig	PowerUp
+B1[7]	IpConfig	CBIT_0
+B0[7]	IpConfig	CBIT_1
+B3[7]	IpConfig	CBIT_2
+B2[7]	IpConfig	CBIT_3
+B5[7]	IpConfig	CBIT_4
+B4[7]	IpConfig	CBIT_5
+B7[7]	IpConfig	CBIT_6
+B6[7]	IpConfig	CBIT_7
+B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43]	LC_0
+B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43]	LC_1
+B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43]	LC_2
+B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43]	LC_3
+B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43]	LC_4
+B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43]	LC_5
+B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43]	LC_6
+B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43]	LC_7
 B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	bnl_op_0	lc_trk_g2_0
 B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	bnl_op_0	lc_trk_g3_0
 !B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	bnl_op_1	lc_trk_g2_1
@@ -5372,52 +5394,1382 @@ B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	bnr_op_6	lc_trk_g0_6
 B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	bnr_op_6	lc_trk_g1_6
 B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	bnr_op_7	lc_trk_g0_7
 B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	bnr_op_7	lc_trk_g1_7
-!B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	bot_op_0	lc_trk_g0_0
 !B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	bot_op_0	lc_trk_g1_0
-!B0[25],B1[22],!B1[23],B1[24],!B1[25]	buffer	bot_op_2	lc_trk_g0_2
+B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	bot_op_1	lc_trk_g1_1
 !B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	bot_op_2	lc_trk_g1_2
+!B0[21],B0[22],!B0[23],B0[24],!B1[21]	buffer	bot_op_3	lc_trk_g0_3
 !B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	bot_op_4	lc_trk_g0_4
 !B6[14],!B7[14],B7[15],!B7[16],B7[17]	buffer	bot_op_4	lc_trk_g1_4
-!B2[25],B3[22],!B3[23],B3[24],!B3[25]	buffer	bot_op_6	lc_trk_g0_6
+B6[15],!B6[16],B6[17],!B6[18],!B7[18]	buffer	bot_op_5	lc_trk_g1_5
 !B6[25],B7[22],!B7[23],B7[24],!B7[25]	buffer	bot_op_6	lc_trk_g1_6
+!B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	bot_op_7	lc_trk_g0_7
 !B2[14],!B3[14],!B3[15],!B3[16],B3[17]	buffer	glb2local_0	lc_trk_g0_4
 !B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
 !B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
 !B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
-!B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_0	wire_bram/ram/RCLK
+!B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_0	clk
+!B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_0	glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_0	glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_0	glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_0	glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_1	clk
 !B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
 !B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_1	glb2local_1
 !B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_1	glb2local_2
 !B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_1	glb2local_3
-!B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_1	wire_bram/ram/RCLK
-B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_2	wire_bram/ram/RCLK
-!B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_2	wire_bram/ram/RE
+B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_2	clk
+B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_2	glb2local_0
+B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_2	glb2local_1
+B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_2	glb2local_2
+B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_2	glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_3	clk
 B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_3	glb2local_0
 B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_3	glb2local_1
 B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
 B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_3	glb2local_3
-B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_3	wire_bram/ram/RCLK
+!B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_4	clk
 !B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_4	glb2local_0
 !B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_4	glb2local_1
 !B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
 !B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_4	glb2local_3
-!B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_4	wire_bram/ram/RCLK
-B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_bram/ram/RE
+!B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_5	clk
 !B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
 !B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
 !B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_5	glb2local_2
 !B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
-!B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_5	wire_bram/ram/RCLK
-B4[0],B4[1],!B5[0],!B5[1]	buffer	glb_netwk_5	wire_bram/ram/RCLKE
+B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_6	clk
 B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_6	glb2local_0
 B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_6	glb2local_1
 B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
 B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_6	glb2local_3
-B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_6	wire_bram/ram/RCLK
-B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_6	wire_bram/ram/RE
+B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	clk
 B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_7	glb2local_0
 B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_7	glb2local_1
 B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_7	glb2local_2
+B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_7	glb2local_3
+!B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g0_0	clk
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	wire_con_box/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g0_0	wire_con_box/lc_1/in_1
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_0	wire_con_box/lc_2/in_0
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g0_0	wire_con_box/lc_3/in_1
+!B8[26],!B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_0	wire_con_box/lc_4/in_0
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g0_0	wire_con_box/lc_5/in_1
+!B12[26],!B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_0	wire_con_box/lc_6/in_0
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g0_0	wire_con_box/lc_7/in_1
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g0_1	wire_con_box/lc_0/in_1
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_1	wire_con_box/lc_1/in_0
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g0_1	wire_con_box/lc_2/in_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_1	wire_con_box/lc_3/in_0
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_con_box/lc_4/in_1
+!B10[26],!B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_1	wire_con_box/lc_5/in_0
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g0_1	wire_con_box/lc_6/in_1
+!B14[26],!B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_1	wire_con_box/lc_7/in_0
+!B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_2	wire_con_box/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_con_box/lc_1/in_1
+!B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_con_box/lc_1/in_3
+!B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_2	wire_con_box/lc_2/in_0
+!B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_con_box/lc_3/in_1
+!B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_con_box/lc_3/in_3
+!B8[26],B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_2	wire_con_box/lc_4/in_0
+!B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_con_box/lc_5/in_1
+!B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_con_box/lc_5/in_3
+!B12[26],B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_2	wire_con_box/lc_6/in_0
+!B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_con_box/lc_7/in_1
+!B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_con_box/lc_7/in_3
+!B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_con_box/lc_0/in_1
+!B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_con_box/lc_0/in_3
+!B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_3	wire_con_box/lc_1/in_0
+!B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_con_box/lc_2/in_1
+!B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_con_box/lc_2/in_3
+!B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_3	wire_con_box/lc_3/in_0
+!B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_con_box/lc_4/in_1
+!B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_3	wire_con_box/lc_4/in_3
+!B10[26],B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_3	wire_con_box/lc_5/in_0
+!B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_con_box/lc_6/in_1
+!B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_con_box/lc_6/in_3
+!B14[26],B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_3	wire_con_box/lc_7/in_0
+B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_4	wire_con_box/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_con_box/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_con_box/lc_1/in_3
+B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_4	wire_con_box/lc_2/in_0
+!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_con_box/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],!B7[31]	buffer	lc_trk_g0_4	wire_con_box/lc_3/in_3
+B8[26],!B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_4	wire_con_box/lc_4/in_0
+!B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_con_box/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],!B11[31]	buffer	lc_trk_g0_4	wire_con_box/lc_5/in_3
+B12[26],!B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_4	wire_con_box/lc_6/in_0
+!B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_con_box/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_con_box/lc_7/in_3
+!B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g0_5	wire_con_box/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_con_box/lc_0/in_3
+B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_5	wire_con_box/lc_1/in_0
+!B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_con_box/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_con_box/lc_2/in_3
+B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_5	wire_con_box/lc_3/in_0
+!B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_con_box/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_con_box/lc_4/in_3
+B10[26],!B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_5	wire_con_box/lc_5/in_0
+!B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_con_box/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_con_box/lc_6/in_3
+B14[26],!B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_5	wire_con_box/lc_7/in_0
+B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_6	wire_con_box/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g0_6	wire_con_box/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_con_box/lc_1/in_3
+B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_6	wire_con_box/lc_2/in_0
+!B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g0_6	wire_con_box/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_con_box/lc_3/in_3
+B8[26],B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_6	wire_con_box/lc_4/in_0
+!B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_con_box/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_con_box/lc_5/in_3
+B12[26],B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_6	wire_con_box/lc_6/in_0
+!B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_con_box/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_con_box/lc_7/in_3
+!B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_con_box/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_con_box/lc_0/in_3
+B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_7	wire_con_box/lc_1/in_0
+!B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_con_box/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_con_box/lc_2/in_3
+B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_7	wire_con_box/lc_3/in_0
+!B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_con_box/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_con_box/lc_4/in_3
+B10[26],B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_7	wire_con_box/lc_5/in_0
+!B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_con_box/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_con_box/lc_6/in_3
+B14[26],B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_7	wire_con_box/lc_7/in_0
+B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_con_box/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_con_box/lc_0/in_3
+!B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_0	wire_con_box/lc_1/in_0
+B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g1_0	wire_con_box/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_con_box/lc_2/in_3
+!B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_0	wire_con_box/lc_3/in_0
+B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_con_box/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_con_box/lc_4/in_3
+!B10[26],!B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_0	wire_con_box/lc_5/in_0
+B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_con_box/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_con_box/lc_6/in_3
+!B14[26],!B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_0	wire_con_box/lc_7/in_0
+!B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g1_1	clk
+!B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_1	wire_con_box/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_con_box/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_con_box/lc_1/in_3
+!B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_1	wire_con_box/lc_2/in_0
+B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g1_1	wire_con_box/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_con_box/lc_3/in_3
+!B8[26],!B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_1	wire_con_box/lc_4/in_0
+B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_con_box/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_con_box/lc_5/in_3
+!B12[26],!B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_1	wire_con_box/lc_6/in_0
+B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_con_box/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_con_box/lc_7/in_3
+B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_con_box/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_con_box/lc_0/in_3
+!B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_2	wire_con_box/lc_1/in_0
+B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_con_box/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_con_box/lc_2/in_3
+!B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_2	wire_con_box/lc_3/in_0
+B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_con_box/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_con_box/lc_4/in_3
+!B10[26],B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_2	wire_con_box/lc_5/in_0
+B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_con_box/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_con_box/lc_6/in_3
+!B14[26],B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_2	wire_con_box/lc_7/in_0
+!B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	wire_con_box/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_con_box/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_con_box/lc_1/in_3
+!B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_3	wire_con_box/lc_2/in_0
+B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_con_box/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_con_box/lc_3/in_3
+!B8[26],B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_3	wire_con_box/lc_4/in_0
+B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_con_box/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_con_box/lc_5/in_3
+!B12[26],B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_3	wire_con_box/lc_6/in_0
+B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_con_box/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_con_box/lc_7/in_3
+B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g1_4	wire_con_box/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_4	wire_con_box/lc_0/in_3
+B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_4	wire_con_box/lc_1/in_0
+B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g1_4	wire_con_box/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_4	wire_con_box/lc_2/in_3
+B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_4	wire_con_box/lc_3/in_0
+B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g1_4	wire_con_box/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_4	wire_con_box/lc_4/in_3
+B10[26],!B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_4	wire_con_box/lc_5/in_0
+B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g1_4	wire_con_box/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_4	wire_con_box/lc_6/in_3
+B14[26],!B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_4	wire_con_box/lc_7/in_0
+B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_5	wire_con_box/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_con_box/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_con_box/lc_1/in_3
+B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_5	wire_con_box/lc_2/in_0
+B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_con_box/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_con_box/lc_3/in_3
+B8[26],!B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_5	wire_con_box/lc_4/in_0
+B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_con_box/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_con_box/lc_5/in_3
+B12[26],!B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_5	wire_con_box/lc_6/in_0
+B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_con_box/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_con_box/lc_7/in_3
+B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g1_6	wire_con_box/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_con_box/lc_0/in_3
+B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_6	wire_con_box/lc_1/in_0
+B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_con_box/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_con_box/lc_2/in_3
+B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_6	wire_con_box/lc_3/in_0
+B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_con_box/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_con_box/lc_4/in_3
+B10[26],B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_6	wire_con_box/lc_5/in_0
+B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_con_box/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_con_box/lc_6/in_3
+B14[26],B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_6	wire_con_box/lc_7/in_0
+B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_7	wire_con_box/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_con_box/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_con_box/lc_1/in_3
+B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_7	wire_con_box/lc_2/in_0
+B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_con_box/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_con_box/lc_3/in_3
+B8[26],B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_7	wire_con_box/lc_4/in_0
+B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_con_box/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_con_box/lc_5/in_3
+B12[26],B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_7	wire_con_box/lc_6/in_0
+B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_con_box/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_con_box/lc_7/in_3
+B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	clk
+!B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	wire_con_box/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_con_box/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_con_box/lc_1/in_3
+!B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_0	wire_con_box/lc_2/in_0
+!B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_con_box/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_0	wire_con_box/lc_3/in_3
+!B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_0	wire_con_box/lc_4/in_0
+!B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_con_box/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_0	wire_con_box/lc_5/in_3
+!B12[26],!B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_0	wire_con_box/lc_6/in_0
+!B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_con_box/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_con_box/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g2_1	wire_con_box/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_con_box/lc_0/in_3
+!B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_1	wire_con_box/lc_1/in_0
+!B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_con_box/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_con_box/lc_2/in_3
+!B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_1	wire_con_box/lc_3/in_0
+!B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_con_box/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_con_box/lc_4/in_3
+!B10[26],!B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_1	wire_con_box/lc_5/in_0
+!B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_con_box/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_con_box/lc_6/in_3
+!B14[26],!B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_1	wire_con_box/lc_7/in_0
+!B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_2	wire_con_box/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g2_2	wire_con_box/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_2	wire_con_box/lc_1/in_3
+!B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_2	wire_con_box/lc_2/in_0
+!B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g2_2	wire_con_box/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_2	wire_con_box/lc_3/in_3
+!B8[26],B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_2	wire_con_box/lc_4/in_0
+!B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_con_box/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_2	wire_con_box/lc_5/in_3
+!B12[26],B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_2	wire_con_box/lc_6/in_0
+!B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_con_box/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_2	wire_con_box/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g2_3	wire_con_box/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_con_box/lc_0/in_3
+!B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_3	wire_con_box/lc_1/in_0
+!B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_con_box/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_con_box/lc_2/in_3
+!B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_3	wire_con_box/lc_3/in_0
+!B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_con_box/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_con_box/lc_4/in_3
+!B10[26],B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_3	wire_con_box/lc_5/in_0
+!B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g2_3	wire_con_box/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_con_box/lc_6/in_3
+!B14[26],B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_3	wire_con_box/lc_7/in_0
+B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_4	wire_con_box/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_con_box/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_con_box/lc_1/in_3
+B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_4	wire_con_box/lc_2/in_0
+!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_con_box/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_con_box/lc_3/in_3
+B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_4	wire_con_box/lc_4/in_0
+!B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_con_box/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_4	wire_con_box/lc_5/in_3
+B12[26],!B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_4	wire_con_box/lc_6/in_0
+!B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_con_box/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_con_box/lc_7/in_3
+!B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g2_5	wire_con_box/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_con_box/lc_0/in_3
+B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_5	wire_con_box/lc_1/in_0
+!B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g2_5	wire_con_box/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_con_box/lc_2/in_3
+B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_5	wire_con_box/lc_3/in_0
+!B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_con_box/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_con_box/lc_4/in_3
+B10[26],!B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_5	wire_con_box/lc_5/in_0
+!B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_con_box/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_con_box/lc_6/in_3
+B14[26],!B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_5	wire_con_box/lc_7/in_0
+B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_6	wire_con_box/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g2_6	wire_con_box/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_6	wire_con_box/lc_1/in_3
+B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_6	wire_con_box/lc_2/in_0
+!B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g2_6	wire_con_box/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_6	wire_con_box/lc_3/in_3
+B8[26],B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_6	wire_con_box/lc_4/in_0
+!B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g2_6	wire_con_box/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_6	wire_con_box/lc_5/in_3
+B12[26],B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_6	wire_con_box/lc_6/in_0
+!B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g2_6	wire_con_box/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_6	wire_con_box/lc_7/in_3
+!B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g2_7	wire_con_box/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_con_box/lc_0/in_3
+B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_7	wire_con_box/lc_1/in_0
+!B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g2_7	wire_con_box/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_con_box/lc_2/in_3
+B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_7	wire_con_box/lc_3/in_0
+!B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g2_7	wire_con_box/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_con_box/lc_4/in_3
+B10[26],B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_7	wire_con_box/lc_5/in_0
+!B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g2_7	wire_con_box/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_con_box/lc_6/in_3
+B14[26],B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_7	wire_con_box/lc_7/in_0
+B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g3_0	wire_con_box/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_0	wire_con_box/lc_0/in_3
+!B2[26],!B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_0	wire_con_box/lc_1/in_0
+B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g3_0	wire_con_box/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_0	wire_con_box/lc_2/in_3
+!B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_0	wire_con_box/lc_3/in_0
+B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g3_0	wire_con_box/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_0	wire_con_box/lc_4/in_3
+!B10[26],!B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_0	wire_con_box/lc_5/in_0
+B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_con_box/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_0	wire_con_box/lc_6/in_3
+!B14[26],!B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_0	wire_con_box/lc_7/in_0
+B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g3_1	clk
+!B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_1	wire_con_box/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g3_1	wire_con_box/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_1	wire_con_box/lc_1/in_3
+!B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_1	wire_con_box/lc_2/in_0
+B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g3_1	wire_con_box/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_1	wire_con_box/lc_3/in_3
+!B8[26],!B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_1	wire_con_box/lc_4/in_0
+B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g3_1	wire_con_box/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_1	wire_con_box/lc_5/in_3
+!B12[26],!B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_1	wire_con_box/lc_6/in_0
+B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g3_1	wire_con_box/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_1	wire_con_box/lc_7/in_3
+B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g3_2	wire_con_box/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_con_box/lc_0/in_3
+!B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_2	wire_con_box/lc_1/in_0
+B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g3_2	wire_con_box/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_con_box/lc_2/in_3
+!B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_2	wire_con_box/lc_3/in_0
+B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g3_2	wire_con_box/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_con_box/lc_4/in_3
+!B10[26],B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_2	wire_con_box/lc_5/in_0
+B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_con_box/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_con_box/lc_6/in_3
+!B14[26],B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_2	wire_con_box/lc_7/in_0
+!B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_3	wire_con_box/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g3_3	wire_con_box/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_3	wire_con_box/lc_1/in_3
+!B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_3	wire_con_box/lc_2/in_0
+B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g3_3	wire_con_box/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_3	wire_con_box/lc_3/in_3
+!B8[26],B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_3	wire_con_box/lc_4/in_0
+B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g3_3	wire_con_box/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_3	wire_con_box/lc_5/in_3
+!B12[26],B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_3	wire_con_box/lc_6/in_0
+B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g3_3	wire_con_box/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_3	wire_con_box/lc_7/in_3
+B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g3_4	wire_con_box/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_con_box/lc_0/in_3
+B2[26],!B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_4	wire_con_box/lc_1/in_0
+B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g3_4	wire_con_box/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_con_box/lc_2/in_3
+B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_4	wire_con_box/lc_3/in_0
+B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_con_box/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_con_box/lc_4/in_3
+B10[26],!B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_4	wire_con_box/lc_5/in_0
+B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_con_box/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_con_box/lc_6/in_3
+B14[26],!B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_4	wire_con_box/lc_7/in_0
+B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_5	wire_con_box/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g3_5	wire_con_box/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_con_box/lc_1/in_3
+B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_5	wire_con_box/lc_2/in_0
+B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g3_5	wire_con_box/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_con_box/lc_3/in_3
+B8[26],!B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_5	wire_con_box/lc_4/in_0
+B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_con_box/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_con_box/lc_5/in_3
+B12[26],!B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_5	wire_con_box/lc_6/in_0
+B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_con_box/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_con_box/lc_7/in_3
+B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g3_6	wire_con_box/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_con_box/lc_0/in_3
+B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_6	wire_con_box/lc_1/in_0
+B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_con_box/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_con_box/lc_2/in_3
+B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_6	wire_con_box/lc_3/in_0
+B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_con_box/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_con_box/lc_4/in_3
+B10[26],B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_6	wire_con_box/lc_5/in_0
+B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g3_6	wire_con_box/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_con_box/lc_6/in_3
+B14[26],B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_6	wire_con_box/lc_7/in_0
+B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_7	wire_con_box/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_con_box/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_7	wire_con_box/lc_1/in_3
+B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_7	wire_con_box/lc_2/in_0
+B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_con_box/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_7	wire_con_box/lc_3/in_3
+B8[26],B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_7	wire_con_box/lc_4/in_0
+B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_con_box/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_7	wire_con_box/lc_5/in_3
+B12[26],B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_7	wire_con_box/lc_6/in_0
+B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g3_7	wire_con_box/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_7	wire_con_box/lc_7/in_3
+B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	lft_op_0	lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18]	buffer	lft_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25]	buffer	lft_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	lft_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21]	buffer	lft_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21]	buffer	lft_op_3	lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	lft_op_4	lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17]	buffer	lft_op_4	lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18]	buffer	lft_op_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18]	buffer	lft_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25]	buffer	lft_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25]	buffer	lft_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	lft_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21]	buffer	lft_op_7	lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	rgt_op_0	lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	rgt_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18]	buffer	rgt_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	rgt_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	rgt_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	rgt_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	rgt_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	rgt_op_3	lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	rgt_op_4	lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	rgt_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18]	buffer	rgt_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18]	buffer	rgt_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	rgt_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	rgt_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	rgt_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
+B8[14],!B9[14],!B9[15],!B9[16],B9[17]	buffer	slf_op_0	lc_trk_g2_0
+B0[47]	buffer	slf_op_0	sp12_h_l_7
+B0[51]	buffer	slf_op_0	sp12_v_b_0
+B0[52]	buffer	slf_op_0	sp12_v_b_16
+B1[47]	buffer	slf_op_0	sp4_h_l_21
+B1[46]	buffer	slf_op_0	sp4_h_r_0
+B0[46]	buffer	slf_op_0	sp4_h_r_16
+B1[52]	buffer	slf_op_0	sp4_r_v_b_1
+B0[53]	buffer	slf_op_0	sp4_r_v_b_17
+B1[53]	buffer	slf_op_0	sp4_r_v_b_33
+B0[48]	buffer	slf_op_0	sp4_v_b_0
+B1[51]	buffer	slf_op_0	sp4_v_t_21
+B1[48]	buffer	slf_op_0	sp4_v_t_5
+!B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	slf_op_1	lc_trk_g3_1
+B2[47]	buffer	slf_op_1	sp12_h_l_9
+B2[51]	buffer	slf_op_1	sp12_v_t_1
+B2[52]	buffer	slf_op_1	sp12_v_t_17
+B2[46]	buffer	slf_op_1	sp4_h_l_7
+B3[46]	buffer	slf_op_1	sp4_h_r_2
+B3[47]	buffer	slf_op_1	sp4_h_r_34
+B2[53]	buffer	slf_op_1	sp4_r_v_b_19
+B3[52]	buffer	slf_op_1	sp4_r_v_b_3
+B3[53]	buffer	slf_op_1	sp4_r_v_b_35
+B3[48]	buffer	slf_op_1	sp4_v_b_18
+B2[48]	buffer	slf_op_1	sp4_v_b_2
+B3[51]	buffer	slf_op_1	sp4_v_t_23
+B12[25],B13[22],!B13[23],!B13[24],!B13[25]	buffer	slf_op_2	lc_trk_g3_2
+B4[47]	buffer	slf_op_2	sp12_h_l_11
+B4[52]	buffer	slf_op_2	sp12_v_b_20
+B4[51]	buffer	slf_op_2	sp12_v_b_4
+B4[46]	buffer	slf_op_2	sp4_h_r_20
+B5[47]	buffer	slf_op_2	sp4_h_r_36
+B5[46]	buffer	slf_op_2	sp4_h_r_4
+B4[53]	buffer	slf_op_2	sp4_r_v_b_21
+B5[53]	buffer	slf_op_2	sp4_r_v_b_37
+B5[52]	buffer	slf_op_2	sp4_r_v_b_5
+B5[51]	buffer	slf_op_2	sp4_v_b_36
+B4[48]	buffer	slf_op_2	sp4_v_b_4
+B5[48]	buffer	slf_op_2	sp4_v_t_9
+B0[21],B0[22],!B0[23],!B0[24],!B1[21]	buffer	slf_op_3	lc_trk_g0_3
+B6[47]	buffer	slf_op_3	sp12_h_r_14
+B6[51]	buffer	slf_op_3	sp12_v_b_6
+B6[52]	buffer	slf_op_3	sp12_v_t_21
+B6[46]	buffer	slf_op_3	sp4_h_l_11
+B7[47]	buffer	slf_op_3	sp4_h_r_38
+B7[46]	buffer	slf_op_3	sp4_h_r_6
+B6[53]	buffer	slf_op_3	sp4_r_v_b_23
+B7[53]	buffer	slf_op_3	sp4_r_v_b_39
+B7[52]	buffer	slf_op_3	sp4_r_v_b_7
+B7[48]	buffer	slf_op_3	sp4_v_b_22
+B6[48]	buffer	slf_op_3	sp4_v_b_6
+B7[51]	buffer	slf_op_3	sp4_v_t_27
+B14[14],!B15[14],!B15[15],!B15[16],B15[17]	buffer	slf_op_4	lc_trk_g3_4
+B8[48]	buffer	slf_op_4	sp12_h_l_15
+B8[47]	buffer	slf_op_4	sp12_h_r_0
+B8[52]	buffer	slf_op_4	sp12_v_t_7
+B9[47]	buffer	slf_op_4	sp4_h_l_29
+B8[46]	buffer	slf_op_4	sp4_h_r_24
+B9[46]	buffer	slf_op_4	sp4_h_r_8
+B8[53]	buffer	slf_op_4	sp4_r_v_b_25
+B9[53]	buffer	slf_op_4	sp4_r_v_b_41
+B9[52]	buffer	slf_op_4	sp4_r_v_b_9
+B8[51]	buffer	slf_op_4	sp4_v_b_40
+B9[48]	buffer	slf_op_4	sp4_v_b_8
+B9[51]	buffer	slf_op_4	sp4_v_t_13
+B10[47]	buffer	slf_op_5	sp12_h_l_1
+B10[48]	buffer	slf_op_5	sp12_h_l_17
+B10[52]	buffer	slf_op_5	sp12_v_b_10
+B11[46]	buffer	slf_op_5	sp4_h_r_10
+B10[46]	buffer	slf_op_5	sp4_h_r_26
+B11[47]	buffer	slf_op_5	sp4_h_r_42
+B11[52]	buffer	slf_op_5	sp4_r_v_b_11
+B10[53]	buffer	slf_op_5	sp4_r_v_b_27
+B11[53]	buffer	slf_op_5	sp4_r_v_b_43
+B11[48]	buffer	slf_op_5	sp4_v_b_10
+B11[51]	buffer	slf_op_5	sp4_v_t_15
+B10[51]	buffer	slf_op_5	sp4_v_t_31
+B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	slf_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],!B7[25]	buffer	slf_op_6	lc_trk_g1_6
+B12[48]	buffer	slf_op_6	sp12_h_r_20
+B12[47]	buffer	slf_op_6	sp12_h_r_4
+B12[52]	buffer	slf_op_6	sp12_v_b_12
+B13[46]	buffer	slf_op_6	sp4_h_l_1
+B13[47]	buffer	slf_op_6	sp4_h_l_33
+B12[46]	buffer	slf_op_6	sp4_h_r_28
+B13[52]	buffer	slf_op_6	sp4_r_v_b_13
+B12[53]	buffer	slf_op_6	sp4_r_v_b_29
+B13[53]	buffer	slf_op_6	sp4_r_v_b_45
+B13[48]	buffer	slf_op_6	sp4_v_b_12
+B13[51]	buffer	slf_op_6	sp4_v_t_17
+B12[51]	buffer	slf_op_6	sp4_v_t_33
+B10[21],B10[22],!B10[23],!B10[24],!B11[21]	buffer	slf_op_7	lc_trk_g2_7
+B14[47]	buffer	slf_op_7	sp12_h_l_5
+B14[48]	buffer	slf_op_7	sp12_h_r_22
+B14[52]	buffer	slf_op_7	sp12_v_b_14
+B14[46]	buffer	slf_op_7	sp4_h_l_19
+B15[46]	buffer	slf_op_7	sp4_h_l_3
+B15[47]	buffer	slf_op_7	sp4_h_l_35
+B15[52]	buffer	slf_op_7	sp4_r_v_b_15
+B14[53]	buffer	slf_op_7	sp4_r_v_b_31
+B15[53]	buffer	slf_op_7	sp4_r_v_b_47
+B14[51]	buffer	slf_op_7	sp4_v_b_46
+B15[51]	buffer	slf_op_7	sp4_v_t_19
+B15[48]	buffer	slf_op_7	sp4_v_t_3
+B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_l_1	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_l_1	lc_trk_g1_2
+B12[19]	buffer	sp12_h_l_1	sp4_h_r_13
+!B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_l_10	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_l_10	lc_trk_g1_5
+!B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_l_11	lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_l_11	lc_trk_g1_4
+B4[2]	buffer	sp12_h_l_11	sp4_h_l_7
+!B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_l_12	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_l_12	lc_trk_g1_7
+!B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_l_15	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_l_15	lc_trk_g1_0
+B8[2]	buffer	sp12_h_l_15	sp4_h_r_20
+!B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_l_16	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_l_16	lc_trk_g1_3
+!B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_l_17	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_l_17	lc_trk_g1_2
+B10[2]	buffer	sp12_h_l_17	sp4_h_l_8
+!B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_l_20	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_l_20	lc_trk_g1_7
+B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_l_5	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_l_5	lc_trk_g1_6
+B14[19]	buffer	sp12_h_l_5	sp4_h_l_2
+!B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_l_7	lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_l_7	lc_trk_g1_0
+B0[2]	buffer	sp12_h_l_7	sp4_h_r_16
+!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_l_9	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_l_9	lc_trk_g1_2
+B3[1]	buffer	sp12_h_l_9	sp4_h_r_17
+B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	sp12_h_r_0	lc_trk_g1_0
+B13[19]	buffer	sp12_h_r_0	sp4_h_l_1
+B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	sp12_h_r_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
+!B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp12_h_r_11	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp12_h_r_11	lc_trk_g1_3
+!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_r_14	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_r_14	lc_trk_g1_6
+B6[2]	buffer	sp12_h_r_14	sp4_h_r_19
+!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_r_17	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_r_17	lc_trk_g1_1
+!B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_20	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_20	lc_trk_g1_4
+B12[2]	buffer	sp12_h_r_20	sp4_h_l_11
+!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_r_21	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_r_21	lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_r_22	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_r_22	lc_trk_g1_6
+B14[2]	buffer	sp12_h_r_22	sp4_h_l_10
+B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_r_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_r_3	lc_trk_g1_3
+B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_r_4	lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17]	buffer	sp12_h_r_4	lc_trk_g1_4
+B15[19]	buffer	sp12_h_r_4	sp4_h_l_3
+B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_r_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_r_5	lc_trk_g1_5
+B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_r_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_r_7	lc_trk_g1_7
+!B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_r_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_r_9	lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
+B1[19]	buffer	sp12_v_b_1	sp4_v_b_12
+!B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_b_10	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp12_v_b_10	lc_trk_g3_2
+!B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp12_v_b_11	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_b_11	lc_trk_g3_3
+B4[19]	buffer	sp12_v_b_11	sp4_v_b_17
+!B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_12	lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_12	lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp12_v_b_14	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp12_v_b_14	lc_trk_g3_6
+!B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_16	lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_b_16	lc_trk_g3_0
+!B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp12_v_b_19	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp12_v_b_19	lc_trk_g3_3
+B8[19]	buffer	sp12_v_b_19	sp4_v_t_8
+!B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_20	lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_20	lc_trk_g3_4
+!B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp12_v_b_21	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp12_v_b_21	lc_trk_g3_5
+B11[19]	buffer	sp12_v_b_21	sp4_v_b_22
+!B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp12_v_b_23	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp12_v_b_23	lc_trk_g3_7
+B10[19]	buffer	sp12_v_b_23	sp4_v_b_23
+B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	sp12_v_b_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	sp12_v_b_3	lc_trk_g3_3
+B0[19]	buffer	sp12_v_b_3	sp4_v_t_0
+B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_b_4	lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_b_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	sp12_v_b_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	sp12_v_b_5	lc_trk_g3_5
+B3[19]	buffer	sp12_v_b_5	sp4_v_t_3
+B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	sp12_v_b_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	sp12_v_b_6	lc_trk_g3_6
+!B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp12_v_b_9	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp12_v_b_9	lc_trk_g3_1
+B5[19]	buffer	sp12_v_b_9	sp4_v_t_5
+B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	sp12_v_t_1	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	sp12_v_t_1	lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp12_v_t_10	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp12_v_t_10	lc_trk_g3_5
+B7[19]	buffer	sp12_v_t_10	sp4_v_b_18
+!B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp12_v_t_12	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp12_v_t_12	lc_trk_g3_7
+B6[19]	buffer	sp12_v_t_12	sp4_v_t_6
+!B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp12_v_t_14	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp12_v_t_14	lc_trk_g3_1
+B9[19]	buffer	sp12_v_t_14	sp4_v_t_9
+!B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp12_v_t_17	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp12_v_t_17	lc_trk_g3_2
+!B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_t_21	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_t_21	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	sp12_v_t_4	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	sp12_v_t_4	lc_trk_g3_7
+B2[19]	buffer	sp12_v_t_4	sp4_v_b_15
+!B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_t_7	lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_t_7	lc_trk_g3_0
+B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_l_1	lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_l_1	lc_trk_g1_4
+B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_l_10	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_l_10	lc_trk_g1_7
+B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_l_11	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_l_11	lc_trk_g1_6
+!B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_l_14	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_l_14	lc_trk_g3_3
+B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_h_l_16	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_h_l_16	lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_l_19	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_l_19	lc_trk_g3_6
+B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_h_l_2	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_h_l_2	lc_trk_g1_7
+B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_21	lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_21	lc_trk_g3_0
+B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_l_26	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_l_26	lc_trk_g3_7
+B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_h_l_28	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_h_l_28	lc_trk_g3_1
+B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_29	lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_29	lc_trk_g3_0
+B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_h_l_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_h_l_3	lc_trk_g1_6
+B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_33	lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_33	lc_trk_g3_4
+B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_l_34	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_l_34	lc_trk_g3_7
+B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_l_35	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_l_35	lc_trk_g3_6
+B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_l_7	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_l_7	lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_l_8	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_l_8	lc_trk_g1_5
+!B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_h_r_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_h_r_11	lc_trk_g1_3
+B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_h_r_13	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_h_r_13	lc_trk_g1_5
+B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_16	lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_16	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_h_r_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_h_r_17	lc_trk_g1_1
+B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_19	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_19	lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_2	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_2	lc_trk_g1_2
+B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_20	lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_20	lc_trk_g1_4
+!B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_24	lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_24	lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_r_25	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_r_25	lc_trk_g3_1
+!B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_26	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_26	lc_trk_g3_2
+!B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_28	lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_28	lc_trk_g3_4
+!B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_3	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_3	lc_trk_g1_3
+!B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_r_31	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_r_31	lc_trk_g3_7
+B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_h_r_33	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_h_r_33	lc_trk_g3_1
+B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_h_r_34	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_h_r_34	lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_r_35	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_r_35	lc_trk_g3_3
+B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_36	lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_36	lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_r_37	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_r_37	lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_r_38	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_r_38	lc_trk_g3_6
+!B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
+B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_42	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_42	lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_43	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_43	lc_trk_g3_3
+B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_h_r_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_r_45	lc_trk_g3_5
+B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_6	lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_8	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_h_r_9	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_h_r_9	lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_0	lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_r_v_b_1	lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25]	buffer	sp4_r_v_b_10	lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21]	buffer	sp4_r_v_b_11	lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_12	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_r_v_b_13	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25]	buffer	sp4_r_v_b_14	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21]	buffer	sp4_r_v_b_15	lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_16	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_r_v_b_17	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25]	buffer	sp4_r_v_b_18	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21]	buffer	sp4_r_v_b_19	lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25]	buffer	sp4_r_v_b_2	lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_20	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_r_v_b_21	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25]	buffer	sp4_r_v_b_22	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21]	buffer	sp4_r_v_b_23	lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_24	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_24	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_r_v_b_25	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_r_v_b_25	lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25]	buffer	sp4_r_v_b_26	lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	sp4_r_v_b_26	lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21]	buffer	sp4_r_v_b_27	lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	sp4_r_v_b_27	lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	sp4_r_v_b_28	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_28	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_r_v_b_29	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_r_v_b_29	lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21]	buffer	sp4_r_v_b_3	lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	sp4_r_v_b_30	lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	sp4_r_v_b_30	lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	sp4_r_v_b_31	lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	sp4_r_v_b_31	lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	sp4_r_v_b_32	lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_32	lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	sp4_r_v_b_33	lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_r_v_b_33	lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_r_v_b_34	lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	sp4_r_v_b_34	lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_35	lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	sp4_r_v_b_35	lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_36	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_r_v_b_37	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	sp4_r_v_b_38	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	sp4_r_v_b_39	lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_4	lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_40	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_r_v_b_41	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	sp4_r_v_b_42	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	sp4_r_v_b_43	lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_44	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_r_v_b_45	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	sp4_r_v_b_46	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	sp4_r_v_b_47	lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_r_v_b_5	lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25]	buffer	sp4_r_v_b_6	lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21]	buffer	sp4_r_v_b_7	lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_8	lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_r_v_b_9	lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_0	lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_0	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_v_b_1	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_v_b_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp4_v_b_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp4_v_b_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp4_v_b_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp4_v_b_11	lc_trk_g1_3
+B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_12	lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_12	lc_trk_g1_4
+B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp4_v_b_15	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp4_v_b_15	lc_trk_g1_7
+B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_v_b_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_v_b_17	lc_trk_g1_1
+!B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_v_b_18	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_v_b_18	lc_trk_g1_2
+B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp4_v_b_2	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp4_v_b_2	lc_trk_g1_2
+!B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_v_b_22	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_v_b_22	lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_v_b_23	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_v_b_23	lc_trk_g1_7
+B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp4_v_b_27	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp4_v_b_27	lc_trk_g3_3
+!B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_v_b_29	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_v_b_29	lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp4_v_b_3	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp4_v_b_3	lc_trk_g1_3
+!B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_v_b_33	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_v_b_33	lc_trk_g3_1
+B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_b_36	lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_b_36	lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp4_v_b_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp4_v_b_39	lc_trk_g3_7
+B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_4	lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_4	lc_trk_g1_4
+!B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_v_b_40	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_v_b_40	lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_v_b_41	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_v_b_41	lc_trk_g3_1
+B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_v_b_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_v_b_45	lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_v_b_46	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_v_b_46	lc_trk_g3_6
+!B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_v_b_5	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_v_b_5	lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp4_v_b_6	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp4_v_b_6	lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp4_v_b_7	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp4_v_b_7	lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_8	lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_8	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_v_b_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_v_b_9	lc_trk_g1_1
+!B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_v_t_0	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_v_t_0	lc_trk_g1_5
+!B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_v_t_12	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_v_t_12	lc_trk_g3_1
+B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_t_13	lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_t_13	lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp4_v_t_15	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp4_v_t_15	lc_trk_g3_2
+B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_t_17	lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_t_17	lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp4_v_t_18	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp4_v_t_18	lc_trk_g3_7
+B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp4_v_t_19	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp4_v_t_19	lc_trk_g3_6
+B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_t_21	lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_t_21	lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp4_v_t_22	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp4_v_t_22	lc_trk_g3_3
+B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp4_v_t_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp4_v_t_23	lc_trk_g3_2
+!B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_v_t_24	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_v_t_24	lc_trk_g3_5
+B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp4_v_t_27	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp4_v_t_27	lc_trk_g3_6
+B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp4_v_t_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp4_v_t_3	lc_trk_g1_6
+!B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_v_t_30	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_v_t_30	lc_trk_g3_3
+!B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_v_t_31	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_v_t_31	lc_trk_g3_2
+!B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_v_t_33	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_v_t_33	lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_v_t_34	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_v_t_34	lc_trk_g3_7
+!B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_v_t_5	lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_v_t_5	lc_trk_g1_0
+!B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_v_t_6	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_v_t_6	lc_trk_g1_3
+B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp4_v_t_8	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_t_8	lc_trk_g1_5
+!B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_v_t_9	lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_v_t_9	lc_trk_g1_4
+!B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
+B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	tnl_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	tnl_op_6	lc_trk_g2_6
+!B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	tnl_op_7	lc_trk_g3_7
+!B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	tnr_op_1	lc_trk_g2_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	tnr_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	tnr_op_2	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	tnr_op_3	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	tnr_op_4	lc_trk_g2_4
+B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
+!B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	top_op_0	lc_trk_g1_0
+B0[15],!B0[16],B0[17],!B0[18],B1[18]	buffer	top_op_1	lc_trk_g0_1
+!B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	top_op_2	lc_trk_g1_2
+!B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	top_op_3	lc_trk_g1_3
+B6[15],!B6[16],B6[17],!B6[18],B7[18]	buffer	top_op_5	lc_trk_g1_5
+!B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	top_op_6	lc_trk_g0_6
+!B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	top_op_7	lc_trk_g0_7
+!B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	top_op_7	lc_trk_g1_7
+!B12[3],B13[3]	routing	sp12_h_l_22	sp12_h_r_1
+!B8[3],B9[3]	routing	sp12_h_l_22	sp12_v_b_1
+!B14[3],B15[3]	routing	sp12_h_l_22	sp12_v_t_22
+!B4[3],B5[3]	routing	sp12_h_l_23	sp12_h_r_0
+!B0[3],B1[3]	routing	sp12_h_l_23	sp12_v_b_0
+!B6[3],B7[3]	routing	sp12_h_l_23	sp12_v_t_23
+B2[3],B3[3]	routing	sp12_h_r_0	sp12_h_l_23
+B0[3],B1[3]	routing	sp12_h_r_0	sp12_v_b_0
+B6[3],B7[3]	routing	sp12_h_r_0	sp12_v_t_23
+B8[3],B9[3]	routing	sp12_h_r_1	sp12_v_b_1
+B14[3],B15[3]	routing	sp12_h_r_1	sp12_v_t_22
+!B2[3],B3[3]	routing	sp12_v_b_0	sp12_h_l_23
+B4[3],B5[3]	routing	sp12_v_b_0	sp12_h_r_0
+B6[3],!B7[3]	routing	sp12_v_b_0	sp12_v_t_23
+B11[3]	routing	sp12_v_b_1	sp12_h_l_22
+B12[3],B13[3]	routing	sp12_v_b_1	sp12_h_r_1
+B14[3],!B15[3]	routing	sp12_v_b_1	sp12_v_t_22
+B10[3]	routing	sp12_v_t_22	sp12_h_l_22
+B12[3],!B13[3]	routing	sp12_v_t_22	sp12_h_r_1
+B8[3],!B9[3]	routing	sp12_v_t_22	sp12_v_b_1
+B2[3],!B3[3]	routing	sp12_v_t_23	sp12_h_l_23
+B4[3],!B5[3]	routing	sp12_v_t_23	sp12_h_r_0
+B0[3],!B1[3]	routing	sp12_v_t_23	sp12_v_b_0
+B0[8],!B0[9],!B0[10]	routing	sp4_h_l_36	sp4_h_r_1
+!B4[8],B4[9],B4[10]	routing	sp4_h_l_36	sp4_h_r_4
+!B12[5],B13[4],B13[6]	routing	sp4_h_l_36	sp4_h_r_9
+B1[8],B1[9],!B1[10]	routing	sp4_h_l_36	sp4_v_b_1
+B9[8],B9[9],B9[10]	routing	sp4_h_l_36	sp4_v_b_7
+B3[8],!B3[9],!B3[10]	routing	sp4_h_l_36	sp4_v_t_36
+!B10[4],B10[6],!B11[5]	routing	sp4_h_l_36	sp4_v_t_43
+!B0[5],!B1[4],B1[6]	routing	sp4_h_l_37	sp4_h_r_0
+B4[5],B5[4],!B5[6]	routing	sp4_h_l_37	sp4_h_r_3
+!B8[12],B9[11],B9[13]	routing	sp4_h_l_37	sp4_h_r_8
+B0[4],!B0[6],B1[5]	routing	sp4_h_l_37	sp4_v_b_0
+B8[4],B8[6],B9[5]	routing	sp4_h_l_37	sp4_v_b_6
+!B2[4],!B2[6],B3[5]	routing	sp4_h_l_37	sp4_v_t_37
+B6[11],!B6[13],!B7[12]	routing	sp4_h_l_37	sp4_v_t_40
+!B4[5],!B5[4],B5[6]	routing	sp4_h_l_38	sp4_h_r_3
+B8[5],B9[4],!B9[6]	routing	sp4_h_l_38	sp4_h_r_6
+B4[4],!B4[6],B5[5]	routing	sp4_h_l_38	sp4_v_b_3
+B12[4],B12[6],B13[5]	routing	sp4_h_l_38	sp4_v_b_9
+!B6[4],!B6[6],B7[5]	routing	sp4_h_l_38	sp4_v_t_38
+B10[11],!B10[13],!B11[12]	routing	sp4_h_l_38	sp4_v_t_45
+!B0[12],B1[11],!B1[13]	routing	sp4_h_l_39	sp4_h_r_2
+B4[12],!B5[11],B5[13]	routing	sp4_h_l_39	sp4_h_r_5
+!B0[11],B0[13],B1[12]	routing	sp4_h_l_39	sp4_v_b_2
+B8[11],B8[13],B9[12]	routing	sp4_h_l_39	sp4_v_b_8
+!B2[11],!B2[13],B3[12]	routing	sp4_h_l_39	sp4_v_t_39
+!B11[8],!B11[9],B11[10]	routing	sp4_h_l_39	sp4_v_t_42
+B0[8],!B0[9],B0[10]	routing	sp4_h_l_40	sp4_h_r_1
+!B4[12],B5[11],!B5[13]	routing	sp4_h_l_40	sp4_h_r_5
+B8[12],!B9[11],B9[13]	routing	sp4_h_l_40	sp4_h_r_8
+B12[11],B12[13],B13[12]	routing	sp4_h_l_40	sp4_v_b_11
+!B4[11],B4[13],B5[12]	routing	sp4_h_l_40	sp4_v_b_5
+!B6[11],!B6[13],B7[12]	routing	sp4_h_l_40	sp4_v_t_40
+!B15[8],!B15[9],B15[10]	routing	sp4_h_l_40	sp4_v_t_47
+!B0[5],B1[4],B1[6]	routing	sp4_h_l_41	sp4_h_r_0
+B4[8],!B4[9],!B4[10]	routing	sp4_h_l_41	sp4_h_r_4
+!B8[8],B8[9],B8[10]	routing	sp4_h_l_41	sp4_h_r_7
+B13[8],B13[9],B13[10]	routing	sp4_h_l_41	sp4_v_b_10
+B5[8],B5[9],!B5[10]	routing	sp4_h_l_41	sp4_v_b_4
+B7[8],!B7[9],!B7[10]	routing	sp4_h_l_41	sp4_v_t_41
+!B14[4],B14[6],!B15[5]	routing	sp4_h_l_41	sp4_v_t_44
+!B12[8],B12[9],B12[10]	routing	sp4_h_l_42	sp4_h_r_10
+!B4[5],B5[4],B5[6]	routing	sp4_h_l_42	sp4_h_r_3
+B8[8],!B8[9],!B8[10]	routing	sp4_h_l_42	sp4_h_r_7
+B1[8],B1[9],B1[10]	routing	sp4_h_l_42	sp4_v_b_1
+B9[8],B9[9],!B9[10]	routing	sp4_h_l_42	sp4_v_b_7
+!B2[4],B2[6],!B3[5]	routing	sp4_h_l_42	sp4_v_t_37
+B11[8],!B11[9],!B11[10]	routing	sp4_h_l_42	sp4_v_t_42
+!B0[12],B1[11],B1[13]	routing	sp4_h_l_43	sp4_h_r_2
+!B8[5],!B9[4],B9[6]	routing	sp4_h_l_43	sp4_h_r_6
+B12[5],B13[4],!B13[6]	routing	sp4_h_l_43	sp4_h_r_9
+B0[4],B0[6],B1[5]	routing	sp4_h_l_43	sp4_v_b_0
+B8[4],!B8[6],B9[5]	routing	sp4_h_l_43	sp4_v_b_6
+!B10[4],!B10[6],B11[5]	routing	sp4_h_l_43	sp4_v_t_43
+B14[11],!B14[13],!B15[12]	routing	sp4_h_l_43	sp4_v_t_46
+B0[5],B1[4],!B1[6]	routing	sp4_h_l_44	sp4_h_r_0
+!B4[12],B5[11],B5[13]	routing	sp4_h_l_44	sp4_h_r_5
+!B12[5],!B13[4],B13[6]	routing	sp4_h_l_44	sp4_h_r_9
+B4[4],B4[6],B5[5]	routing	sp4_h_l_44	sp4_v_b_3
+B12[4],!B12[6],B13[5]	routing	sp4_h_l_44	sp4_v_b_9
+B2[11],!B2[13],!B3[12]	routing	sp4_h_l_44	sp4_v_t_39
+!B14[4],!B14[6],B15[5]	routing	sp4_h_l_44	sp4_v_t_44
+B12[12],!B13[11],B13[13]	routing	sp4_h_l_45	sp4_h_r_11
+B4[8],!B4[9],B4[10]	routing	sp4_h_l_45	sp4_h_r_4
+!B8[12],B9[11],!B9[13]	routing	sp4_h_l_45	sp4_h_r_8
+B0[11],B0[13],B1[12]	routing	sp4_h_l_45	sp4_v_b_2
+!B8[11],B8[13],B9[12]	routing	sp4_h_l_45	sp4_v_b_8
+!B3[8],!B3[9],B3[10]	routing	sp4_h_l_45	sp4_v_t_36
+!B10[11],!B10[13],B11[12]	routing	sp4_h_l_45	sp4_v_t_45
+!B12[12],B13[11],!B13[13]	routing	sp4_h_l_46	sp4_h_r_11
+B0[12],!B1[11],B1[13]	routing	sp4_h_l_46	sp4_h_r_2
+B8[8],!B8[9],B8[10]	routing	sp4_h_l_46	sp4_h_r_7
+!B12[11],B12[13],B13[12]	routing	sp4_h_l_46	sp4_v_b_11
+B4[11],B4[13],B5[12]	routing	sp4_h_l_46	sp4_v_b_5
+!B7[8],!B7[9],B7[10]	routing	sp4_h_l_46	sp4_v_t_41
+!B14[11],!B14[13],B15[12]	routing	sp4_h_l_46	sp4_v_t_46
+!B0[8],B0[9],B0[10]	routing	sp4_h_l_47	sp4_h_r_1
+B12[8],!B12[9],!B12[10]	routing	sp4_h_l_47	sp4_h_r_10
+!B8[5],B9[4],B9[6]	routing	sp4_h_l_47	sp4_h_r_6
+B13[8],B13[9],!B13[10]	routing	sp4_h_l_47	sp4_v_b_10
+B5[8],B5[9],B5[10]	routing	sp4_h_l_47	sp4_v_b_4
+!B6[4],B6[6],!B7[5]	routing	sp4_h_l_47	sp4_v_t_38
+B15[8],!B15[9],!B15[10]	routing	sp4_h_l_47	sp4_v_t_47
+!B2[5],!B3[4],B3[6]	routing	sp4_h_r_0	sp4_h_l_37
+B6[5],B7[4],!B7[6]	routing	sp4_h_r_0	sp4_h_l_38
+!B10[12],B11[11],B11[13]	routing	sp4_h_r_0	sp4_h_l_45
+!B0[4],!B0[6],B1[5]	routing	sp4_h_r_0	sp4_v_b_0
+B4[11],!B4[13],!B5[12]	routing	sp4_h_r_0	sp4_v_b_5
+B2[4],!B2[6],B3[5]	routing	sp4_h_r_0	sp4_v_t_37
+B10[4],B10[6],B11[5]	routing	sp4_h_r_0	sp4_v_t_43
+!B6[8],B6[9],B6[10]	routing	sp4_h_r_1	sp4_h_l_41
+!B14[5],B15[4],B15[6]	routing	sp4_h_r_1	sp4_h_l_44
+B1[8],!B1[9],!B1[10]	routing	sp4_h_r_1	sp4_v_b_1
+!B8[4],B8[6],!B9[5]	routing	sp4_h_r_1	sp4_v_b_6
+B3[8],B3[9],!B3[10]	routing	sp4_h_r_1	sp4_v_t_36
+B11[8],B11[9],B11[10]	routing	sp4_h_r_1	sp4_v_t_42
+!B2[8],B2[9],B2[10]	routing	sp4_h_r_10	sp4_h_l_36
+!B10[5],B11[4],B11[6]	routing	sp4_h_r_10	sp4_h_l_43
+B14[8],!B14[9],!B14[10]	routing	sp4_h_r_10	sp4_h_l_47
+B13[8],!B13[9],!B13[10]	routing	sp4_h_r_10	sp4_v_b_10
+!B4[4],B4[6],!B5[5]	routing	sp4_h_r_10	sp4_v_b_3
+B7[8],B7[9],B7[10]	routing	sp4_h_r_10	sp4_v_t_41
+B15[8],B15[9],!B15[10]	routing	sp4_h_r_10	sp4_v_t_47
+B10[8],!B10[9],B10[10]	routing	sp4_h_r_11	sp4_h_l_42
+!B14[12],B15[11],!B15[13]	routing	sp4_h_r_11	sp4_h_l_46
+!B12[11],!B12[13],B13[12]	routing	sp4_h_r_11	sp4_v_b_11
+!B5[8],!B5[9],B5[10]	routing	sp4_h_r_11	sp4_v_b_4
+B6[11],B6[13],B7[12]	routing	sp4_h_r_11	sp4_v_t_40
+!B14[11],B14[13],B15[12]	routing	sp4_h_r_11	sp4_v_t_46
+!B2[12],B3[11],!B3[13]	routing	sp4_h_r_2	sp4_h_l_39
+B6[12],!B7[11],B7[13]	routing	sp4_h_r_2	sp4_h_l_40
+B14[8],!B14[9],B14[10]	routing	sp4_h_r_2	sp4_h_l_47
+!B0[11],!B0[13],B1[12]	routing	sp4_h_r_2	sp4_v_b_2
+!B9[8],!B9[9],B9[10]	routing	sp4_h_r_2	sp4_v_b_7
+!B2[11],B2[13],B3[12]	routing	sp4_h_r_2	sp4_v_t_39
+B10[11],B10[13],B11[12]	routing	sp4_h_r_2	sp4_v_t_45
+!B14[12],B15[11],B15[13]	routing	sp4_h_r_3	sp4_h_l_46
+!B4[4],!B4[6],B5[5]	routing	sp4_h_r_3	sp4_v_b_3
+B8[11],!B8[13],!B9[12]	routing	sp4_h_r_3	sp4_v_b_8
+B6[4],!B6[6],B7[5]	routing	sp4_h_r_3	sp4_v_t_38
+B14[4],B14[6],B15[5]	routing	sp4_h_r_3	sp4_v_t_44
+!B2[5],B3[4],B3[6]	routing	sp4_h_r_4	sp4_h_l_37
+B6[8],!B6[9],!B6[10]	routing	sp4_h_r_4	sp4_h_l_41
+!B10[8],B10[9],B10[10]	routing	sp4_h_r_4	sp4_h_l_42
+B5[8],!B5[9],!B5[10]	routing	sp4_h_r_4	sp4_v_b_4
+!B12[4],B12[6],!B13[5]	routing	sp4_h_r_4	sp4_v_b_9
+B7[8],B7[9],!B7[10]	routing	sp4_h_r_4	sp4_v_t_41
+B15[8],B15[9],B15[10]	routing	sp4_h_r_4	sp4_v_t_47
+B2[8],!B2[9],B2[10]	routing	sp4_h_r_5	sp4_h_l_36
+!B13[8],!B13[9],B13[10]	routing	sp4_h_r_5	sp4_v_b_10
+!B4[11],!B4[13],B5[12]	routing	sp4_h_r_5	sp4_v_b_5
+!B6[11],B6[13],B7[12]	routing	sp4_h_r_5	sp4_v_t_40
+B14[11],B14[13],B15[12]	routing	sp4_h_r_5	sp4_v_t_46
+!B2[12],B3[11],B3[13]	routing	sp4_h_r_6	sp4_h_l_39
+B12[11],!B12[13],!B13[12]	routing	sp4_h_r_6	sp4_v_b_11
+!B8[4],!B8[6],B9[5]	routing	sp4_h_r_6	sp4_v_b_6
+B2[4],B2[6],B3[5]	routing	sp4_h_r_6	sp4_v_t_37
+B10[4],!B10[6],B11[5]	routing	sp4_h_r_6	sp4_v_t_43
+B10[8],!B10[9],!B10[10]	routing	sp4_h_r_7	sp4_h_l_42
+!B0[4],B0[6],!B1[5]	routing	sp4_h_r_7	sp4_v_b_0
+B9[8],!B9[9],!B9[10]	routing	sp4_h_r_7	sp4_v_b_7
+B3[8],B3[9],B3[10]	routing	sp4_h_r_7	sp4_v_t_36
+B11[8],B11[9],!B11[10]	routing	sp4_h_r_7	sp4_v_t_42
+B6[8],!B6[9],B6[10]	routing	sp4_h_r_8	sp4_h_l_41
+!B10[12],B11[11],!B11[13]	routing	sp4_h_r_8	sp4_h_l_45
+B14[12],!B15[11],B15[13]	routing	sp4_h_r_8	sp4_h_l_46
+!B1[8],!B1[9],B1[10]	routing	sp4_h_r_8	sp4_v_b_1
+!B8[11],!B8[13],B9[12]	routing	sp4_h_r_8	sp4_v_b_8
+B2[11],B2[13],B3[12]	routing	sp4_h_r_8	sp4_v_t_39
+!B10[11],B10[13],B11[12]	routing	sp4_h_r_8	sp4_v_t_45
+B2[5],B3[4],!B3[6]	routing	sp4_h_r_9	sp4_h_l_37
+B0[11],!B0[13],!B1[12]	routing	sp4_h_r_9	sp4_v_b_2
+!B12[4],!B12[6],B13[5]	routing	sp4_h_r_9	sp4_v_b_9
+B6[4],B6[6],B7[5]	routing	sp4_h_r_9	sp4_v_t_38
+B14[4],!B14[6],B15[5]	routing	sp4_h_r_9	sp4_v_t_44
+B2[5],!B3[4],!B3[6]	routing	sp4_v_b_0	sp4_h_l_37
+!B6[12],!B7[11],B7[13]	routing	sp4_v_b_0	sp4_h_l_40
+B0[5],!B1[4],B1[6]	routing	sp4_v_b_0	sp4_h_r_0
+B8[5],B9[4],B9[6]	routing	sp4_v_b_0	sp4_h_r_6
+B2[4],!B2[6],!B3[5]	routing	sp4_v_b_0	sp4_v_t_37
+!B6[4],B6[6],B7[5]	routing	sp4_v_b_0	sp4_v_t_38
+B10[11],B10[13],!B11[12]	routing	sp4_v_b_0	sp4_v_t_45
+!B2[8],B2[9],!B2[10]	routing	sp4_v_b_1	sp4_h_l_36
+!B10[5],B11[4],!B11[6]	routing	sp4_v_b_1	sp4_h_l_43
+B0[8],B0[9],!B0[10]	routing	sp4_v_b_1	sp4_h_r_1
+B8[8],B8[9],B8[10]	routing	sp4_v_b_1	sp4_h_r_7
+!B3[8],B3[9],!B3[10]	routing	sp4_v_b_1	sp4_v_t_36
+B7[8],!B7[9],B7[10]	routing	sp4_v_b_1	sp4_v_t_41
+B14[4],B14[6],!B15[5]	routing	sp4_v_b_1	sp4_v_t_44
+!B6[5],B7[4],!B7[6]	routing	sp4_v_b_10	sp4_h_l_38
+!B14[8],B14[9],!B14[10]	routing	sp4_v_b_10	sp4_h_l_47
+B12[8],B12[9],!B12[10]	routing	sp4_v_b_10	sp4_h_r_10
+B4[8],B4[9],B4[10]	routing	sp4_v_b_10	sp4_h_r_4
+B3[8],!B3[9],B3[10]	routing	sp4_v_b_10	sp4_v_t_36
+B10[4],B10[6],!B11[5]	routing	sp4_v_b_10	sp4_v_t_43
+!B15[8],B15[9],!B15[10]	routing	sp4_v_b_10	sp4_v_t_47
+!B6[8],!B6[9],B6[10]	routing	sp4_v_b_11	sp4_h_l_41
+B14[12],!B15[11],!B15[13]	routing	sp4_v_b_11	sp4_h_l_46
+B12[12],B13[11],!B13[13]	routing	sp4_v_b_11	sp4_h_r_11
+B4[12],B5[11],B5[13]	routing	sp4_v_b_11	sp4_h_r_5
+B2[11],!B2[13],B3[12]	routing	sp4_v_b_11	sp4_v_t_39
+!B11[8],B11[9],B11[10]	routing	sp4_v_b_11	sp4_v_t_42
+!B14[11],B14[13],!B15[12]	routing	sp4_v_b_11	sp4_v_t_46
+B2[12],!B3[11],!B3[13]	routing	sp4_v_b_2	sp4_h_l_39
+!B10[8],!B10[9],B10[10]	routing	sp4_v_b_2	sp4_h_l_42
+B0[12],B1[11],!B1[13]	routing	sp4_v_b_2	sp4_h_r_2
+B8[12],B9[11],B9[13]	routing	sp4_v_b_2	sp4_h_r_8
+!B2[11],B2[13],!B3[12]	routing	sp4_v_b_2	sp4_v_t_39
+B6[11],!B6[13],B7[12]	routing	sp4_v_b_2	sp4_v_t_40
+!B15[8],B15[9],B15[10]	routing	sp4_v_b_2	sp4_v_t_47
+B6[5],!B7[4],!B7[6]	routing	sp4_v_b_3	sp4_h_l_38
+!B10[12],!B11[11],B11[13]	routing	sp4_v_b_3	sp4_h_l_45
+B4[5],!B5[4],B5[6]	routing	sp4_v_b_3	sp4_h_r_3
+B12[5],B13[4],B13[6]	routing	sp4_v_b_3	sp4_h_r_9
+B6[4],!B6[6],!B7[5]	routing	sp4_v_b_3	sp4_v_t_38
+!B10[4],B10[6],B11[5]	routing	sp4_v_b_3	sp4_v_t_43
+B14[11],B14[13],!B15[12]	routing	sp4_v_b_3	sp4_v_t_46
+!B6[8],B6[9],!B6[10]	routing	sp4_v_b_4	sp4_h_l_41
+!B14[5],B15[4],!B15[6]	routing	sp4_v_b_4	sp4_h_l_44
+B12[8],B12[9],B12[10]	routing	sp4_v_b_4	sp4_h_r_10
+B4[8],B4[9],!B4[10]	routing	sp4_v_b_4	sp4_h_r_4
+B2[4],B2[6],!B3[5]	routing	sp4_v_b_4	sp4_v_t_37
+!B7[8],B7[9],!B7[10]	routing	sp4_v_b_4	sp4_v_t_41
+B11[8],!B11[9],B11[10]	routing	sp4_v_b_4	sp4_v_t_42
+B6[12],!B7[11],!B7[13]	routing	sp4_v_b_5	sp4_h_l_40
+!B14[8],!B14[9],B14[10]	routing	sp4_v_b_5	sp4_h_l_47
+B12[12],B13[11],B13[13]	routing	sp4_v_b_5	sp4_h_r_11
+B4[12],B5[11],!B5[13]	routing	sp4_v_b_5	sp4_h_r_5
+!B3[8],B3[9],B3[10]	routing	sp4_v_b_5	sp4_v_t_36
+!B6[11],B6[13],!B7[12]	routing	sp4_v_b_5	sp4_v_t_40
+B10[11],!B10[13],B11[12]	routing	sp4_v_b_5	sp4_v_t_45
+B10[5],!B11[4],!B11[6]	routing	sp4_v_b_6	sp4_h_l_43
+!B14[12],!B15[11],B15[13]	routing	sp4_v_b_6	sp4_h_l_46
+B0[5],B1[4],B1[6]	routing	sp4_v_b_6	sp4_h_r_0
+B8[5],!B9[4],B9[6]	routing	sp4_v_b_6	sp4_h_r_6
+B2[11],B2[13],!B3[12]	routing	sp4_v_b_6	sp4_v_t_39
+B10[4],!B10[6],!B11[5]	routing	sp4_v_b_6	sp4_v_t_43
+!B14[4],B14[6],B15[5]	routing	sp4_v_b_6	sp4_v_t_44
+!B2[5],B3[4],!B3[6]	routing	sp4_v_b_7	sp4_h_l_37
+!B10[8],B10[9],!B10[10]	routing	sp4_v_b_7	sp4_h_l_42
+B0[8],B0[9],B0[10]	routing	sp4_v_b_7	sp4_h_r_1
+B8[8],B8[9],!B8[10]	routing	sp4_v_b_7	sp4_h_r_7
+B6[4],B6[6],!B7[5]	routing	sp4_v_b_7	sp4_v_t_38
+!B11[8],B11[9],!B11[10]	routing	sp4_v_b_7	sp4_v_t_42
+B15[8],!B15[9],B15[10]	routing	sp4_v_b_7	sp4_v_t_47
+!B2[8],!B2[9],B2[10]	routing	sp4_v_b_8	sp4_h_l_36
+B10[12],!B11[11],!B11[13]	routing	sp4_v_b_8	sp4_h_l_45
+B0[12],B1[11],B1[13]	routing	sp4_v_b_8	sp4_h_r_2
+B8[12],B9[11],!B9[13]	routing	sp4_v_b_8	sp4_h_r_8
+!B7[8],B7[9],B7[10]	routing	sp4_v_b_8	sp4_v_t_41
+!B10[11],B10[13],!B11[12]	routing	sp4_v_b_8	sp4_v_t_45
+B14[11],!B14[13],B15[12]	routing	sp4_v_b_8	sp4_v_t_46
+!B2[12],!B3[11],B3[13]	routing	sp4_v_b_9	sp4_h_l_39
+B14[5],!B15[4],!B15[6]	routing	sp4_v_b_9	sp4_h_l_44
+B4[5],B5[4],B5[6]	routing	sp4_v_b_9	sp4_h_r_3
+B12[5],!B13[4],B13[6]	routing	sp4_v_b_9	sp4_h_r_9
+!B2[4],B2[6],B3[5]	routing	sp4_v_b_9	sp4_v_t_37
+B6[11],B6[13],!B7[12]	routing	sp4_v_b_9	sp4_v_t_40
+B14[4],!B14[6],!B15[5]	routing	sp4_v_b_9	sp4_v_t_44
+B2[8],B2[9],!B2[10]	routing	sp4_v_t_36	sp4_h_l_36
+B10[8],B10[9],B10[10]	routing	sp4_v_t_36	sp4_h_l_42
+!B0[8],B0[9],!B0[10]	routing	sp4_v_t_36	sp4_h_r_1
+!B8[5],B9[4],!B9[6]	routing	sp4_v_t_36	sp4_h_r_6
+!B1[8],B1[9],!B1[10]	routing	sp4_v_t_36	sp4_v_b_1
+B5[8],!B5[9],B5[10]	routing	sp4_v_t_36	sp4_v_b_4
+B12[4],B12[6],!B13[5]	routing	sp4_v_t_36	sp4_v_b_9
+B2[5],!B3[4],B3[6]	routing	sp4_v_t_37	sp4_h_l_37
+B10[5],B11[4],B11[6]	routing	sp4_v_t_37	sp4_h_l_43
+B0[5],!B1[4],!B1[6]	routing	sp4_v_t_37	sp4_h_r_0
+!B4[12],!B5[11],B5[13]	routing	sp4_v_t_37	sp4_h_r_5
+B0[4],!B0[6],!B1[5]	routing	sp4_v_t_37	sp4_v_b_0
+!B4[4],B4[6],B5[5]	routing	sp4_v_t_37	sp4_v_b_3
+B8[11],B8[13],!B9[12]	routing	sp4_v_t_37	sp4_v_b_8
+B6[5],!B7[4],B7[6]	routing	sp4_v_t_38	sp4_h_l_38
+B14[5],B15[4],B15[6]	routing	sp4_v_t_38	sp4_h_l_44
+B4[5],!B5[4],!B5[6]	routing	sp4_v_t_38	sp4_h_r_3
+!B8[12],!B9[11],B9[13]	routing	sp4_v_t_38	sp4_h_r_8
+B12[11],B12[13],!B13[12]	routing	sp4_v_t_38	sp4_v_b_11
+B4[4],!B4[6],!B5[5]	routing	sp4_v_t_38	sp4_v_b_3
+!B8[4],B8[6],B9[5]	routing	sp4_v_t_38	sp4_v_b_6
+B2[12],B3[11],!B3[13]	routing	sp4_v_t_39	sp4_h_l_39
+B10[12],B11[11],B11[13]	routing	sp4_v_t_39	sp4_h_l_45
+B0[12],!B1[11],!B1[13]	routing	sp4_v_t_39	sp4_h_r_2
+!B8[8],!B8[9],B8[10]	routing	sp4_v_t_39	sp4_h_r_7
+!B13[8],B13[9],B13[10]	routing	sp4_v_t_39	sp4_v_b_10
+!B0[11],B0[13],!B1[12]	routing	sp4_v_t_39	sp4_v_b_2
+B4[11],!B4[13],B5[12]	routing	sp4_v_t_39	sp4_v_b_5
+B6[12],B7[11],!B7[13]	routing	sp4_v_t_40	sp4_h_l_40
+B14[12],B15[11],B15[13]	routing	sp4_v_t_40	sp4_h_l_46
+!B12[8],!B12[9],B12[10]	routing	sp4_v_t_40	sp4_h_r_10
+B4[12],!B5[11],!B5[13]	routing	sp4_v_t_40	sp4_h_r_5
+!B1[8],B1[9],B1[10]	routing	sp4_v_t_40	sp4_v_b_1
+!B4[11],B4[13],!B5[12]	routing	sp4_v_t_40	sp4_v_b_5
+B8[11],!B8[13],B9[12]	routing	sp4_v_t_40	sp4_v_b_8
+B6[8],B6[9],!B6[10]	routing	sp4_v_t_41	sp4_h_l_41
+B14[8],B14[9],B14[10]	routing	sp4_v_t_41	sp4_h_l_47
+!B4[8],B4[9],!B4[10]	routing	sp4_v_t_41	sp4_h_r_4
+!B12[5],B13[4],!B13[6]	routing	sp4_v_t_41	sp4_h_r_9
+B0[4],B0[6],!B1[5]	routing	sp4_v_t_41	sp4_v_b_0
+!B5[8],B5[9],!B5[10]	routing	sp4_v_t_41	sp4_v_b_4
+B9[8],!B9[9],B9[10]	routing	sp4_v_t_41	sp4_v_b_7
+B2[8],B2[9],B2[10]	routing	sp4_v_t_42	sp4_h_l_36
+B10[8],B10[9],!B10[10]	routing	sp4_v_t_42	sp4_h_l_42
+!B0[5],B1[4],!B1[6]	routing	sp4_v_t_42	sp4_h_r_0
+!B8[8],B8[9],!B8[10]	routing	sp4_v_t_42	sp4_h_r_7
+B13[8],!B13[9],B13[10]	routing	sp4_v_t_42	sp4_v_b_10
+B4[4],B4[6],!B5[5]	routing	sp4_v_t_42	sp4_v_b_3
+!B9[8],B9[9],!B9[10]	routing	sp4_v_t_42	sp4_v_b_7
+B2[5],B3[4],B3[6]	routing	sp4_v_t_43	sp4_h_l_37
+B10[5],!B11[4],B11[6]	routing	sp4_v_t_43	sp4_h_l_43
+!B12[12],!B13[11],B13[13]	routing	sp4_v_t_43	sp4_h_r_11
+B8[5],!B9[4],!B9[6]	routing	sp4_v_t_43	sp4_h_r_6
+B0[11],B0[13],!B1[12]	routing	sp4_v_t_43	sp4_v_b_2
+B8[4],!B8[6],!B9[5]	routing	sp4_v_t_43	sp4_v_b_6
+!B12[4],B12[6],B13[5]	routing	sp4_v_t_43	sp4_v_b_9
+B6[5],B7[4],B7[6]	routing	sp4_v_t_44	sp4_h_l_38
+B14[5],!B15[4],B15[6]	routing	sp4_v_t_44	sp4_h_l_44
+!B0[12],!B1[11],B1[13]	routing	sp4_v_t_44	sp4_h_r_2
+B12[5],!B13[4],!B13[6]	routing	sp4_v_t_44	sp4_h_r_9
+!B0[4],B0[6],B1[5]	routing	sp4_v_t_44	sp4_v_b_0
+B4[11],B4[13],!B5[12]	routing	sp4_v_t_44	sp4_v_b_5
+B12[4],!B12[6],!B13[5]	routing	sp4_v_t_44	sp4_v_b_9
+B2[12],B3[11],B3[13]	routing	sp4_v_t_45	sp4_h_l_39
+B10[12],B11[11],!B11[13]	routing	sp4_v_t_45	sp4_h_l_45
+!B0[8],!B0[9],B0[10]	routing	sp4_v_t_45	sp4_h_r_1
+B8[12],!B9[11],!B9[13]	routing	sp4_v_t_45	sp4_h_r_8
+B12[11],!B12[13],B13[12]	routing	sp4_v_t_45	sp4_v_b_11
+!B5[8],B5[9],B5[10]	routing	sp4_v_t_45	sp4_v_b_4
+!B8[11],B8[13],!B9[12]	routing	sp4_v_t_45	sp4_v_b_8
+B6[12],B7[11],B7[13]	routing	sp4_v_t_46	sp4_h_l_40
+B14[12],B15[11],!B15[13]	routing	sp4_v_t_46	sp4_h_l_46
+B12[12],!B13[11],!B13[13]	routing	sp4_v_t_46	sp4_h_r_11
+!B4[8],!B4[9],B4[10]	routing	sp4_v_t_46	sp4_h_r_4
+!B12[11],B12[13],!B13[12]	routing	sp4_v_t_46	sp4_v_b_11
+B0[11],!B0[13],B1[12]	routing	sp4_v_t_46	sp4_v_b_2
+!B9[8],B9[9],B9[10]	routing	sp4_v_t_46	sp4_v_b_7
+B6[8],B6[9],B6[10]	routing	sp4_v_t_47	sp4_h_l_41
+B14[8],B14[9],!B14[10]	routing	sp4_v_t_47	sp4_h_l_47
+!B12[8],B12[9],!B12[10]	routing	sp4_v_t_47	sp4_h_r_10
+!B4[5],B5[4],!B5[6]	routing	sp4_v_t_47	sp4_h_r_3
+B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
+!B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
+B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
+"""
+database_ramb_5k_txt = """
+B8[7]	ColBufCtrl	8k_glb_netwk_1
+B11[7]	ColBufCtrl	8k_glb_netwk_2
+B10[7]	ColBufCtrl	8k_glb_netwk_3
+B13[7]	ColBufCtrl	8k_glb_netwk_4
+B12[7]	ColBufCtrl	8k_glb_netwk_5
+B15[7]	ColBufCtrl	8k_glb_netwk_6
+B14[7]	ColBufCtrl	8k_glb_netwk_7
+B0[0]	NegClk
+B1[7]	RamConfig	PowerUp
+B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	bnl_op_0	lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	bnl_op_0	lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	bnl_op_1	lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	bnl_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	bnl_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	bnl_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	bnl_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	bnl_op_3	lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	bnl_op_4	lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	bnl_op_4	lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	bnl_op_5	lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	bnl_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	bnl_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	bnl_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	bnl_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	bnl_op_7	lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	bnr_op_0	lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	bnr_op_0	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	bnr_op_1	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	bnr_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	bnr_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	bnr_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	bnr_op_3	lc_trk_g0_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	bnr_op_4	lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	bnr_op_4	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	bnr_op_5	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	bnr_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	bnr_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	bnr_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	bnr_op_7	lc_trk_g0_7
+!B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	bot_op_0	lc_trk_g1_0
+!B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	bot_op_2	lc_trk_g1_2
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17]	buffer	glb2local_0	lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
+B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
+!B12[0],B12[1],B13[0]	buffer	glb_netwk_1	glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_1	wire_bram/ram/RCLK
+B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_2	glb2local_2
+B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_2	wire_bram/ram/RCLK
+B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
+B12[0],B12[1],B13[0]	buffer	glb_netwk_3	glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_3	wire_bram/ram/RCLK
+!B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
+!B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_4	wire_bram/ram/RCLK
+B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_bram/ram/RE
+B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
+B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
+!B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_5	wire_bram/ram/RCLK
+B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
 B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/RCLK
 !B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	input0_0
 !B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_0	input0_2
@@ -5433,7 +6785,6 @@ B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/RCLK
 !B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_1	input0_3
 !B10[26],!B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_1	input0_5
 !B14[26],!B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_1	input0_7
-!B10[35],B11[32],!B11[33],!B11[34],!B11[35]	buffer	lc_trk_g0_1	input2_5
 !B14[35],B15[32],!B15[33],!B15[34],!B15[35]	buffer	lc_trk_g0_1	input2_7
 !B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_bram/ram/WDATA_11
 !B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g0_1	wire_bram/ram/WDATA_13
@@ -5446,13 +6797,10 @@ B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/RCLK
 !B12[35],B13[32],!B13[33],!B13[34],B13[35]	buffer	lc_trk_g0_2	input2_6
 !B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_10
 !B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_12
-!B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_14
 !B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_8
 !B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g0_2	wire_bram/ram/RCLKE
 !B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_10
 !B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_12
-!B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_14
-!B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_8
 !B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_3	input0_1
 !B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_3	input0_3
 !B10[26],B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_3	input0_5
@@ -5463,7 +6811,6 @@ B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/RCLK
 !B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_13
 !B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_15
 !B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_9
-!B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_11
 !B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_13
 !B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_15
 !B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_9
@@ -5478,34 +6825,25 @@ B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_bram/ram/MASK_14
 B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_bram/ram/MASK_8
 !B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g0_4	wire_bram/ram/RE
 !B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_10
-!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_12
 !B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_14
 !B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_8
 B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_5	input0_1
 B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_5	input0_3
 B10[26],!B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_5	input0_5
 B14[26],!B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_5	input0_7
-B10[35],B11[32],!B11[33],!B11[34],!B11[35]	buffer	lc_trk_g0_5	input2_5
 B14[35],B15[32],!B15[33],!B15[34],!B15[35]	buffer	lc_trk_g0_5	input2_7
 B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_11
-B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_13
 B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_15
-B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_9
-!B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_11
 !B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_13
-!B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_15
 !B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_9
 B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_6	input0_0
 B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_6	input0_2
 B8[26],B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_6	input0_4
 B12[26],B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_6	input0_6
 B12[35],B13[32],!B13[33],!B13[34],B13[35]	buffer	lc_trk_g0_6	input2_6
-B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_10
-B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_12
 B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_14
 B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_8
 !B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_bram/ram/WDATA_10
-!B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g0_6	wire_bram/ram/WDATA_12
 !B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g0_6	wire_bram/ram/WDATA_14
 !B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_bram/ram/WDATA_8
 B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_7	input0_1
@@ -5514,13 +6852,11 @@ B10[26],B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_7	input0_5
 B14[26],B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_7	input0_7
 B10[35],B11[32],!B11[33],!B11[34],B11[35]	buffer	lc_trk_g0_7	input2_5
 B14[35],B15[32],!B15[33],!B15[34],B15[35]	buffer	lc_trk_g0_7	input2_7
-B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_11
 B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_13
 B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_15
 B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_9
 !B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_11
 !B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_13
-!B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_15
 !B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_9
 !B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_0	input0_1
 !B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_0	input0_3
@@ -5529,9 +6865,7 @@ B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_
 !B10[35],B11[32],!B11[33],B11[34],!B11[35]	buffer	lc_trk_g1_0	input2_5
 !B14[35],B15[32],!B15[33],B15[34],!B15[35]	buffer	lc_trk_g1_0	input2_7
 !B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_11
-!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_13
 !B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_15
-!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_9
 B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDATA_11
 B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDATA_13
 B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDATA_15
@@ -5543,26 +6877,19 @@ B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDAT
 !B12[35],B13[32],!B13[33],B13[34],!B13[35]	buffer	lc_trk_g1_1	input2_6
 !B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_10
 !B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_12
-!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_14
 !B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_8
 !B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g1_1	wire_bram/ram/RCLK
-B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_10
-B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_12
 B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_14
 B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_8
 !B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_2	input0_1
 !B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_2	input0_3
 !B10[26],B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_2	input0_5
 !B14[26],B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_2	input0_7
-!B10[35],B11[32],!B11[33],B11[34],B11[35]	buffer	lc_trk_g1_2	input2_5
 !B14[35],B15[32],!B15[33],B15[34],B15[35]	buffer	lc_trk_g1_2	input2_7
-!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_11
 !B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_13
 !B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_15
 !B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_9
-B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_11
 B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_13
-B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_15
 B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_9
 !B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	input0_0
 !B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_3	input0_2
@@ -5572,10 +6899,7 @@ B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA
 !B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_10
 !B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_12
 !B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_14
-!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_8
 !B4[0],B4[1],B5[0],B5[1]	buffer	lc_trk_g1_3	wire_bram/ram/RCLKE
-B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_10
-B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_12
 B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_14
 B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_8
 B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_4	input0_1
@@ -5597,28 +6921,18 @@ B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_5	input0_2
 B8[26],!B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_5	input0_4
 B12[26],!B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_5	input0_6
 B12[35],B13[32],!B13[33],B13[34],!B13[35]	buffer	lc_trk_g1_5	input2_6
-B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_10
 B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_12
-B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_14
-B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_8
 !B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g1_5	wire_bram/ram/RE
 B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_10
 B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_12
-B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_14
-B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_8
 B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_6	input0_1
 B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_6	input0_3
 B10[26],B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_6	input0_5
 B14[26],B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_6	input0_7
-B10[35],B11[32],!B11[33],B11[34],B11[35]	buffer	lc_trk_g1_6	input2_5
 B14[35],B15[32],!B15[33],B15[34],B15[35]	buffer	lc_trk_g1_6	input2_7
-B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_11
 B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_13
-B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_15
-B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_9
 B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_11
 B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_13
-B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_15
 B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_9
 B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_7	input0_0
 B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_7	input0_2
@@ -5628,11 +6942,7 @@ B12[35],B13[32],!B13[33],B13[34],B13[35]	buffer	lc_trk_g1_7	input2_6
 B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_10
 B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_12
 B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_14
-B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_8
-B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_10
-B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_12
 B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_14
-B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_8
 !B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	input0_0
 !B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_0	input0_2
 !B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_0	input0_4
@@ -5643,7 +6953,6 @@ B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_
 !B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_bram/ram/MASK_14
 !B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_bram/ram/MASK_8
 B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	wire_bram/ram/RCLK
-!B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_10
 !B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_12
 !B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_14
 !B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_8
@@ -5651,13 +6960,11 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	wire_bram/ram/RCLK
 !B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_1	input0_3
 !B10[26],!B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_1	input0_5
 !B14[26],!B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_1	input0_7
-!B10[35],B11[32],B11[33],!B11[34],!B11[35]	buffer	lc_trk_g2_1	input2_5
 !B14[35],B15[32],B15[33],!B15[34],!B15[35]	buffer	lc_trk_g2_1	input2_7
 !B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_11
 !B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_13
 !B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_15
 !B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_9
-!B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_11
 !B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_13
 !B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_15
 !B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_9
@@ -5673,7 +6980,6 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	wire_bram/ram/RCLK
 B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g2_2	wire_bram/ram/RCLKE
 !B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_bram/ram/WDATA_10
 !B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g2_2	wire_bram/ram/WDATA_12
-!B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g2_2	wire_bram/ram/WDATA_14
 !B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_bram/ram/WDATA_8
 !B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_3	input0_1
 !B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_3	input0_3
@@ -5684,7 +6990,6 @@ B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g2_2	wire_bram/ram/RCLKE
 !B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_11
 !B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_13
 !B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_15
-!B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_9
 !B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_bram/ram/WDATA_11
 !B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_bram/ram/WDATA_13
 !B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g2_3	wire_bram/ram/WDATA_15
@@ -5699,47 +7004,32 @@ B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_12
 B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_14
 B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_8
 B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g2_4	wire_bram/ram/RE
-!B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_10
-!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_12
 !B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_14
 !B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_8
 B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_5	input0_1
 B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_5	input0_3
 B10[26],!B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_5	input0_5
 B14[26],!B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_5	input0_7
-B10[35],B11[32],B11[33],!B11[34],!B11[35]	buffer	lc_trk_g2_5	input2_5
 B14[35],B15[32],B15[33],!B15[34],!B15[35]	buffer	lc_trk_g2_5	input2_7
 B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_11
-B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_13
 B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_15
 B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_9
 !B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_bram/ram/WDATA_11
 !B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g2_5	wire_bram/ram/WDATA_13
-!B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g2_5	wire_bram/ram/WDATA_15
 !B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_bram/ram/WDATA_9
 B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_6	input0_0
 B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_6	input0_2
 B8[26],B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_6	input0_4
 B12[26],B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_6	input0_6
 B12[35],B13[32],B13[33],!B13[34],B13[35]	buffer	lc_trk_g2_6	input2_6
-B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_6	wire_bram/ram/MASK_10
-B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_6	wire_bram/ram/MASK_12
 B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_6	wire_bram/ram/MASK_14
 B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_6	wire_bram/ram/MASK_8
-!B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g2_6	wire_bram/ram/WDATA_10
 !B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g2_6	wire_bram/ram/WDATA_12
 !B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g2_6	wire_bram/ram/WDATA_14
-!B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g2_6	wire_bram/ram/WDATA_8
 B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_7	input0_1
 B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_7	input0_3
 B10[26],B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_7	input0_5
 B14[26],B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_7	input0_7
-B10[35],B11[32],B11[33],!B11[34],B11[35]	buffer	lc_trk_g2_7	input2_5
-B14[35],B15[32],B15[33],!B15[34],B15[35]	buffer	lc_trk_g2_7	input2_7
-B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_11
-B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_13
-B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_15
-B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_9
 !B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g2_7	wire_bram/ram/WDATA_11
 !B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g2_7	wire_bram/ram/WDATA_13
 !B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g2_7	wire_bram/ram/WDATA_15
@@ -5764,9 +7054,7 @@ B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_bram/ram/WDATA
 !B12[26],!B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_1	input0_6
 !B12[35],B13[32],B13[33],B13[34],!B13[35]	buffer	lc_trk_g3_1	input2_6
 !B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_1	wire_bram/ram/MASK_10
-!B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_1	wire_bram/ram/MASK_12
 !B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_1	wire_bram/ram/MASK_14
-!B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_1	wire_bram/ram/MASK_8
 B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g3_1	wire_bram/ram/RCLK
 B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g3_1	wire_bram/ram/WDATA_10
 B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g3_1	wire_bram/ram/WDATA_12
@@ -5776,15 +7064,12 @@ B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g3_1	wire_bram/ram/WDATA
 !B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_2	input0_3
 !B10[26],B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_2	input0_5
 !B14[26],B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_2	input0_7
-!B10[35],B11[32],B11[33],B11[34],B11[35]	buffer	lc_trk_g3_2	input2_5
 !B14[35],B15[32],B15[33],B15[34],B15[35]	buffer	lc_trk_g3_2	input2_7
-!B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_11
 !B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_13
 !B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_15
 !B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_9
 B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g3_2	wire_bram/ram/WDATA_11
 B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g3_2	wire_bram/ram/WDATA_13
-B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g3_2	wire_bram/ram/WDATA_15
 B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_bram/ram/WDATA_9
 !B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_3	input0_0
 !B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_3	input0_2
@@ -5792,9 +7077,6 @@ B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_bram/ram/WDATA_
 !B12[26],B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_3	input0_6
 !B12[35],B13[32],B13[33],B13[34],B13[35]	buffer	lc_trk_g3_3	input2_6
 !B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_3	wire_bram/ram/MASK_10
-!B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_3	wire_bram/ram/MASK_12
-!B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_3	wire_bram/ram/MASK_14
-!B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_3	wire_bram/ram/MASK_8
 B4[0],B4[1],B5[0],B5[1]	buffer	lc_trk_g3_3	wire_bram/ram/RCLKE
 B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g3_3	wire_bram/ram/WDATA_10
 B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g3_3	wire_bram/ram/WDATA_12
@@ -5809,8 +7091,6 @@ B14[35],B15[32],B15[33],B15[34],!B15[35]	buffer	lc_trk_g3_4	input2_7
 B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_11
 B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_13
 B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_15
-B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_9
-B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_bram/ram/WDATA_11
 B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g3_4	wire_bram/ram/WDATA_13
 B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g3_4	wire_bram/ram/WDATA_15
 B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_bram/ram/WDATA_9
@@ -5819,15 +7099,10 @@ B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_5	input0_2
 B8[26],!B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_5	input0_4
 B12[26],!B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_5	input0_6
 B12[35],B13[32],B13[33],B13[34],!B13[35]	buffer	lc_trk_g3_5	input2_6
-B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_10
-B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_12
 B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_14
-B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_8
 B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g3_5	wire_bram/ram/RE
 B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_bram/ram/WDATA_10
 B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g3_5	wire_bram/ram/WDATA_12
-B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g3_5	wire_bram/ram/WDATA_14
-B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_bram/ram/WDATA_8
 B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_6	input0_1
 B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_6	input0_3
 B10[26],B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_6	input0_5
@@ -5836,7 +7111,6 @@ B10[35],B11[32],B11[33],B11[34],B11[35]	buffer	lc_trk_g3_6	input2_5
 B14[35],B15[32],B15[33],B15[34],B15[35]	buffer	lc_trk_g3_6	input2_7
 B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_11
 B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_13
-B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_15
 B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_9
 B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_bram/ram/WDATA_11
 B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_bram/ram/WDATA_13
@@ -5851,10 +7125,7 @@ B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_7	wire_bram/ram/MASK_10
 B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_7	wire_bram/ram/MASK_12
 B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_7	wire_bram/ram/MASK_14
 B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_7	wire_bram/ram/MASK_8
-B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_10
 B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_12
-B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_14
-B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_8
 B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	lft_op_0	lc_trk_g0_0
 B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
 B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
@@ -5890,22 +7161,16 @@ B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
 B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_l_1	lc_trk_g0_2
 B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_l_1	lc_trk_g1_2
 B12[19]	buffer	sp12_h_l_1	sp4_h_r_13
-!B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_l_10	lc_trk_g0_5
-!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_l_10	lc_trk_g1_5
 !B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_l_12	lc_trk_g0_7
 !B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_l_12	lc_trk_g1_7
-!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_l_14	lc_trk_g0_1
 !B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_l_14	lc_trk_g1_1
 !B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_l_15	lc_trk_g0_0
-!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_l_15	lc_trk_g1_0
 B8[2]	buffer	sp12_h_l_15	sp4_h_l_9
 !B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_l_16	lc_trk_g0_3
 !B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_l_16	lc_trk_g1_3
 !B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_l_17	lc_trk_g0_2
 !B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_l_17	lc_trk_g1_2
 B10[2]	buffer	sp12_h_l_17	sp4_h_r_21
-B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_l_2	lc_trk_g0_5
-B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_l_2	lc_trk_g1_5
 !B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_l_20	lc_trk_g0_7
 !B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_l_20	lc_trk_g1_7
 B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_l_3	lc_trk_g0_4
@@ -5914,7 +7179,6 @@ B15[19]	buffer	sp12_h_l_3	sp4_h_l_3
 B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_l_5	lc_trk_g0_6
 B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_l_5	lc_trk_g1_6
 B14[19]	buffer	sp12_h_l_5	sp4_h_r_15
-!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_l_9	lc_trk_g0_2
 !B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_l_9	lc_trk_g1_2
 B3[1]	buffer	sp12_h_l_9	sp4_h_r_17
 B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
@@ -5927,29 +7191,21 @@ B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
 !B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_12	lc_trk_g0_4
 !B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_12	lc_trk_g1_4
 B4[2]	buffer	sp12_h_r_12	sp4_h_r_18
-!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_r_14	lc_trk_g0_6
 !B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_r_14	lc_trk_g1_6
 B6[2]	buffer	sp12_h_r_14	sp4_h_l_6
 !B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_20	lc_trk_g0_4
 !B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_20	lc_trk_g1_4
 B12[2]	buffer	sp12_h_r_20	sp4_h_l_11
-!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_r_21	lc_trk_g0_5
-!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_r_21	lc_trk_g1_5
 !B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_r_22	lc_trk_g0_6
-!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_r_22	lc_trk_g1_6
 B14[2]	buffer	sp12_h_r_22	sp4_h_r_23
 B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_r_3	lc_trk_g0_3
 B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_r_3	lc_trk_g1_3
-B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_r_7	lc_trk_g0_7
 B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_r_7	lc_trk_g1_7
 !B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_8	lc_trk_g0_0
 !B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_8	lc_trk_g1_0
 B0[2]	buffer	sp12_h_r_8	sp4_h_r_16
-!B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_r_9	lc_trk_g0_1
-!B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_r_9	lc_trk_g1_1
 B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
 B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
-B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
 B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
 B1[19]	buffer	sp12_v_b_1	sp4_v_b_12
 !B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_b_10	lc_trk_g2_2
@@ -5970,7 +7226,6 @@ B8[19]	buffer	sp12_v_b_19	sp4_v_t_8
 !B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_20	lc_trk_g3_4
 !B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_b_22	lc_trk_g2_6
 !B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_b_22	lc_trk_g3_6
-B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	sp12_v_b_3	lc_trk_g2_3
 B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	sp12_v_b_3	lc_trk_g3_3
 B0[19]	buffer	sp12_v_b_3	sp4_v_b_13
 B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_b_4	lc_trk_g2_4
@@ -5994,7 +7249,6 @@ B9[19]	buffer	sp12_v_t_14	sp4_v_b_20
 !B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp12_v_t_18	lc_trk_g2_5
 !B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp12_v_t_18	lc_trk_g3_5
 B11[19]	buffer	sp12_v_t_18	sp4_v_t_11
-!B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp12_v_t_20	lc_trk_g2_7
 !B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp12_v_t_20	lc_trk_g3_7
 B10[19]	buffer	sp12_v_t_20	sp4_v_b_23
 B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	sp12_v_t_4	lc_trk_g2_7
@@ -6004,7 +7258,6 @@ B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	sp12_v_t_5	lc_trk_g2_6
 B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	sp12_v_t_5	lc_trk_g3_6
 !B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_t_7	lc_trk_g2_0
 !B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_t_7	lc_trk_g3_0
-!B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp12_v_t_8	lc_trk_g2_3
 !B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_t_8	lc_trk_g3_3
 B4[19]	buffer	sp12_v_t_8	sp4_v_t_4
 B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_l_1	lc_trk_g0_4
@@ -6017,9 +7270,7 @@ B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_l_11	lc_trk_g1_6
 !B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_l_15	lc_trk_g3_2
 !B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_l_19	lc_trk_g2_6
 !B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_l_19	lc_trk_g3_6
-B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_l_22	lc_trk_g2_3
 B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_l_22	lc_trk_g3_3
-B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_l_26	lc_trk_g2_7
 B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_l_26	lc_trk_g3_7
 B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_l_27	lc_trk_g2_6
 B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_l_27	lc_trk_g3_6
@@ -6032,12 +7283,10 @@ B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_l_6	lc_trk_g1_3
 B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_l_9	lc_trk_g0_4
 B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_l_9	lc_trk_g1_4
 !B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
-!B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
 B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
 B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
 B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
 B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
-B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_h_r_11	lc_trk_g0_3
 B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_h_r_11	lc_trk_g1_3
 B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_h_r_13	lc_trk_g0_5
 B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_h_r_13	lc_trk_g1_5
@@ -6055,7 +7304,6 @@ B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_r_21	lc_trk_g0_5
 B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_r_21	lc_trk_g1_5
 B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_23	lc_trk_g0_7
 B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_23	lc_trk_g1_7
-!B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_24	lc_trk_g2_0
 !B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_24	lc_trk_g3_0
 B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_r_25	lc_trk_g2_1
 B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_r_25	lc_trk_g3_1
@@ -6078,7 +7326,6 @@ B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_36	lc_trk_g3_4
 B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_r_37	lc_trk_g2_5
 B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_r_37	lc_trk_g3_5
 !B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
-!B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
 B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_40	lc_trk_g2_0
 B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_40	lc_trk_g3_0
 B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_42	lc_trk_g2_2
@@ -6092,7 +7339,6 @@ B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_r_45	lc_trk_g3_5
 B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_46	lc_trk_g2_6
 B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_46	lc_trk_g3_6
 B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_r_47	lc_trk_g2_7
-B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_r_47	lc_trk_g3_7
 B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
 B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
 !B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
@@ -6100,8 +7346,6 @@ B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
 !B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
 !B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
 B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
-B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_8	lc_trk_g1_0
-B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_h_r_9	lc_trk_g0_1
 B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_h_r_9	lc_trk_g1_1
 !B4[14],!B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_0	lc_trk_g1_0
 !B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_r_v_b_1	lc_trk_g1_1
@@ -6176,7 +7420,6 @@ B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_12	lc_trk_g1_4
 !B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_v_b_13	lc_trk_g0_5
 !B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_v_b_13	lc_trk_g1_5
 B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp4_v_b_14	lc_trk_g0_6
-B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp4_v_b_14	lc_trk_g1_6
 !B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_v_b_16	lc_trk_g0_0
 !B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_v_b_16	lc_trk_g1_0
 B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp4_v_b_2	lc_trk_g0_2
@@ -6213,14 +7456,11 @@ B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_v_b_41	lc_trk_g3_1
 !B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_v_b_43	lc_trk_g3_3
 !B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_v_b_44	lc_trk_g2_4
 !B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_v_b_44	lc_trk_g3_4
-B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_v_b_45	lc_trk_g2_5
 B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_v_b_45	lc_trk_g3_5
 !B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_v_b_46	lc_trk_g2_6
-!B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_v_b_46	lc_trk_g3_6
 !B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_v_b_5	lc_trk_g0_5
 !B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_v_b_5	lc_trk_g1_5
 B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp4_v_b_6	lc_trk_g0_6
-B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp4_v_b_6	lc_trk_g1_6
 B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp4_v_b_7	lc_trk_g0_7
 B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp4_v_b_7	lc_trk_g1_7
 B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_8	lc_trk_g0_0
@@ -6262,69 +7502,44 @@ B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_t_8	lc_trk_g1_5
 !B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
 !B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
 B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
-B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	tnl_op_1	lc_trk_g3_1
 !B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
 !B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
 !B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
-!B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
 !B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	tnl_op_4	lc_trk_g2_4
 !B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	tnl_op_4	lc_trk_g3_4
 B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	tnl_op_5	lc_trk_g2_5
 B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	tnl_op_5	lc_trk_g3_5
 !B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	tnl_op_6	lc_trk_g2_6
 !B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	tnl_op_6	lc_trk_g3_6
-!B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	tnl_op_7	lc_trk_g2_7
 !B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	tnl_op_7	lc_trk_g3_7
-!B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	tnr_op_0	lc_trk_g2_0
-!B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
-B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	tnr_op_1	lc_trk_g2_1
-B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	tnr_op_1	lc_trk_g3_1
-!B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	tnr_op_2	lc_trk_g2_2
-!B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	tnr_op_2	lc_trk_g3_2
 !B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	tnr_op_3	lc_trk_g2_3
-!B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	tnr_op_3	lc_trk_g3_3
 !B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	tnr_op_4	lc_trk_g2_4
-!B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	tnr_op_4	lc_trk_g3_4
-B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	tnr_op_5	lc_trk_g2_5
 B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
 !B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	tnr_op_6	lc_trk_g2_6
 !B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
-!B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
-!B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
 B10[37]	buffer	wire_bram/ram/RDATA_10	sp12_h_l_1
 B11[38]	buffer	wire_bram/ram/RDATA_10	sp12_h_l_17
 B11[40]	buffer	wire_bram/ram/RDATA_10	sp12_v_b_10
 B11[37]	buffer	wire_bram/ram/RDATA_10	sp4_h_l_15
-B11[36]	buffer	wire_bram/ram/RDATA_10	sp4_h_r_10
-B10[36]	buffer	wire_bram/ram/RDATA_10	sp4_h_r_42
 B11[41]	buffer	wire_bram/ram/RDATA_10	sp4_r_v_b_11
-B10[40]	buffer	wire_bram/ram/RDATA_10	sp4_r_v_b_27
 B10[41]	buffer	wire_bram/ram/RDATA_10	sp4_r_v_b_43
 B11[39]	buffer	wire_bram/ram/RDATA_10	sp4_v_b_10
-B10[38]	buffer	wire_bram/ram/RDATA_10	sp4_v_t_15
 B10[39]	buffer	wire_bram/ram/RDATA_10	sp4_v_t_31
-B9[38]	buffer	wire_bram/ram/RDATA_11	sp12_h_l_15
 B8[37]	buffer	wire_bram/ram/RDATA_11	sp12_h_r_0
 B9[40]	buffer	wire_bram/ram/RDATA_11	sp12_v_t_7
 B9[37]	buffer	wire_bram/ram/RDATA_11	sp4_h_r_24
-B8[36]	buffer	wire_bram/ram/RDATA_11	sp4_h_r_40
-B9[36]	buffer	wire_bram/ram/RDATA_11	sp4_h_r_8
 B8[40]	buffer	wire_bram/ram/RDATA_11	sp4_r_v_b_25
 B8[41]	buffer	wire_bram/ram/RDATA_11	sp4_r_v_b_41
 B9[41]	buffer	wire_bram/ram/RDATA_11	sp4_r_v_b_9
 B8[39]	buffer	wire_bram/ram/RDATA_11	sp4_v_b_40
 B9[39]	buffer	wire_bram/ram/RDATA_11	sp4_v_b_8
-B8[38]	buffer	wire_bram/ram/RDATA_11	sp4_v_t_13
 B6[37]	buffer	wire_bram/ram/RDATA_12	sp12_h_r_14
 B7[40]	buffer	wire_bram/ram/RDATA_12	sp12_v_b_22
 B6[39]	buffer	wire_bram/ram/RDATA_12	sp12_v_t_5
 B7[37]	buffer	wire_bram/ram/RDATA_12	sp4_h_l_11
-B6[36]	buffer	wire_bram/ram/RDATA_12	sp4_h_l_27
-B7[36]	buffer	wire_bram/ram/RDATA_12	sp4_h_r_6
 B6[40]	buffer	wire_bram/ram/RDATA_12	sp4_r_v_b_23
 B6[41]	buffer	wire_bram/ram/RDATA_12	sp4_r_v_b_39
 B7[41]	buffer	wire_bram/ram/RDATA_12	sp4_r_v_b_7
-B7[38]	buffer	wire_bram/ram/RDATA_12	sp4_v_b_6
 B7[39]	buffer	wire_bram/ram/RDATA_12	sp4_v_t_11
 B6[38]	buffer	wire_bram/ram/RDATA_12	sp4_v_t_27
 B4[37]	buffer	wire_bram/ram/RDATA_13	sp12_h_r_12
@@ -6343,18 +7558,14 @@ B2[37]	buffer	wire_bram/ram/RDATA_14	sp12_h_l_9
 B3[40]	buffer	wire_bram/ram/RDATA_14	sp12_v_b_18
 B2[39]	buffer	wire_bram/ram/RDATA_14	sp12_v_t_1
 B3[37]	buffer	wire_bram/ram/RDATA_14	sp4_h_r_18
-B3[36]	buffer	wire_bram/ram/RDATA_14	sp4_h_r_2
 B2[36]	buffer	wire_bram/ram/RDATA_14	sp4_h_r_34
 B2[40]	buffer	wire_bram/ram/RDATA_14	sp4_r_v_b_19
-B3[41]	buffer	wire_bram/ram/RDATA_14	sp4_r_v_b_3
 B2[41]	buffer	wire_bram/ram/RDATA_14	sp4_r_v_b_35
 B3[38]	buffer	wire_bram/ram/RDATA_14	sp4_v_b_2
 B2[38]	buffer	wire_bram/ram/RDATA_14	sp4_v_b_34
 B3[39]	buffer	wire_bram/ram/RDATA_14	sp4_v_t_7
 B0[37]	buffer	wire_bram/ram/RDATA_15	sp12_h_r_8
 B0[39]	buffer	wire_bram/ram/RDATA_15	sp12_v_b_0
-B1[40]	buffer	wire_bram/ram/RDATA_15	sp12_v_b_16
-B1[36]	buffer	wire_bram/ram/RDATA_15	sp4_h_r_0
 B1[37]	buffer	wire_bram/ram/RDATA_15	sp4_h_r_16
 B0[36]	buffer	wire_bram/ram/RDATA_15	sp4_h_r_32
 B1[41]	buffer	wire_bram/ram/RDATA_15	sp4_r_v_b_1
@@ -6367,14 +7578,11 @@ B14[37]	buffer	wire_bram/ram/RDATA_8	sp12_h_l_5
 B15[38]	buffer	wire_bram/ram/RDATA_8	sp12_h_r_22
 B15[40]	buffer	wire_bram/ram/RDATA_8	sp12_v_b_14
 B15[37]	buffer	wire_bram/ram/RDATA_8	sp4_h_l_19
-B15[36]	buffer	wire_bram/ram/RDATA_8	sp4_h_l_3
 B14[36]	buffer	wire_bram/ram/RDATA_8	sp4_h_r_46
 B15[41]	buffer	wire_bram/ram/RDATA_8	sp4_r_v_b_15
-B14[40]	buffer	wire_bram/ram/RDATA_8	sp4_r_v_b_31
 B14[41]	buffer	wire_bram/ram/RDATA_8	sp4_r_v_b_47
 B15[39]	buffer	wire_bram/ram/RDATA_8	sp4_v_b_14
 B14[39]	buffer	wire_bram/ram/RDATA_8	sp4_v_b_46
-B14[38]	buffer	wire_bram/ram/RDATA_8	sp4_v_t_19
 B12[37]	buffer	wire_bram/ram/RDATA_9	sp12_h_l_3
 B13[38]	buffer	wire_bram/ram/RDATA_9	sp12_h_r_20
 B13[40]	buffer	wire_bram/ram/RDATA_9	sp12_v_t_11
@@ -6382,7 +7590,6 @@ B13[36]	buffer	wire_bram/ram/RDATA_9	sp4_h_l_1
 B13[37]	buffer	wire_bram/ram/RDATA_9	sp4_h_r_28
 B12[36]	buffer	wire_bram/ram/RDATA_9	sp4_h_r_44
 B13[41]	buffer	wire_bram/ram/RDATA_9	sp4_r_v_b_13
-B12[40]	buffer	wire_bram/ram/RDATA_9	sp4_r_v_b_29
 B12[41]	buffer	wire_bram/ram/RDATA_9	sp4_r_v_b_45
 B13[39]	buffer	wire_bram/ram/RDATA_9	sp4_v_b_12
 B12[38]	buffer	wire_bram/ram/RDATA_9	sp4_v_b_28
@@ -6551,6 +7758,7 @@ B10[12],!B11[11],B11[13]	routing	sp4_h_r_5	sp4_h_l_45
 !B4[11],!B4[13],B5[12]	routing	sp4_h_r_5	sp4_v_b_5
 !B6[11],B6[13],B7[12]	routing	sp4_h_r_5	sp4_v_t_40
 B14[11],B14[13],B15[12]	routing	sp4_h_r_5	sp4_v_t_46
+!B2[12],B3[11],B3[13]	routing	sp4_h_r_6	sp4_h_l_39
 !B10[5],!B11[4],B11[6]	routing	sp4_h_r_6	sp4_h_l_43
 B14[5],B15[4],!B15[6]	routing	sp4_h_r_6	sp4_h_l_44
 B12[11],!B12[13],!B13[12]	routing	sp4_h_r_6	sp4_v_b_11
@@ -6566,6 +7774,7 @@ B3[8],B3[9],B3[10]	routing	sp4_h_r_7	sp4_v_t_36
 B11[8],B11[9],!B11[10]	routing	sp4_h_r_7	sp4_v_t_42
 B6[8],!B6[9],B6[10]	routing	sp4_h_r_8	sp4_h_l_41
 !B10[12],B11[11],!B11[13]	routing	sp4_h_r_8	sp4_h_l_45
+B14[12],!B15[11],B15[13]	routing	sp4_h_r_8	sp4_h_l_46
 !B1[8],!B1[9],B1[10]	routing	sp4_h_r_8	sp4_v_b_1
 !B8[11],!B8[13],B9[12]	routing	sp4_h_r_8	sp4_v_b_8
 B2[11],B2[13],B3[12]	routing	sp4_h_r_8	sp4_v_t_39
@@ -6800,40 +8009,20 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	bnr_op_7	lc_trk_g1_7
 !B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
 !B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
 !B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
-!B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_0	wire_bram/ram/WCLK
-!B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
-!B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_1	glb2local_1
-!B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_1	glb2local_2
-!B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_1	glb2local_3
 !B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_1	wire_bram/ram/WCLK
 B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_2	wire_bram/ram/WCLK
 B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_3	glb2local_0
-B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_3	glb2local_1
 B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
-B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_3	glb2local_3
-B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_3	wire_bram/ram/WCLK
-!B4[0],B4[1],B5[0],!B5[1]	buffer	glb_netwk_3	wire_bram/ram/WCLKE
-!B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_4	glb2local_0
-!B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_4	glb2local_1
 !B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
-!B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_4	glb2local_3
 !B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_4	wire_bram/ram/WCLK
 B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_bram/ram/WE
 !B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
-!B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
 !B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_5	glb2local_2
-!B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
+B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
 !B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_5	wire_bram/ram/WCLK
-B4[0],B4[1],!B5[0],!B5[1]	buffer	glb_netwk_5	wire_bram/ram/WCLKE
-B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_6	glb2local_0
-B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_6	glb2local_1
+B8[0],B8[1],B9[1]	buffer	glb_netwk_6	glb2local_1
 B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
-B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_6	glb2local_3
-B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_6	wire_bram/ram/WCLK
 B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_6	wire_bram/ram/WE
-B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_7	glb2local_0
-B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_7	glb2local_2
-B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_7	glb2local_3
 B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/WCLK
 !B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	input0_0
 !B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_0	input0_2
@@ -6844,12 +8033,10 @@ B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/WCLK
 !B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g0_0	wire_bram/ram/WDATA_0
 !B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g0_0	wire_bram/ram/WDATA_2
 !B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g0_0	wire_bram/ram/WDATA_4
-!B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g0_0	wire_bram/ram/WDATA_6
 !B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_1	input0_1
 !B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_1	input0_3
 !B10[26],!B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_1	input0_5
 !B14[26],!B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_1	input0_7
-!B10[35],B11[32],!B11[33],!B11[34],!B11[35]	buffer	lc_trk_g0_1	input2_5
 !B14[35],B15[32],!B15[33],!B15[34],!B15[35]	buffer	lc_trk_g0_1	input2_7
 !B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g0_1	wire_bram/ram/WDATA_1
 !B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_bram/ram/WDATA_3
@@ -6861,41 +8048,29 @@ B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_bram/ram/WCLK
 !B12[26],B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_2	input0_6
 !B12[35],B13[32],!B13[33],!B13[34],B13[35]	buffer	lc_trk_g0_2	input2_6
 !B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_0
-!B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_2
-!B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_4
 !B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_bram/ram/MASK_6
 !B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g0_2	wire_bram/ram/WCLKE
 !B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_0
-!B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_2
 !B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_4
 !B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_bram/ram/WDATA_6
 !B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_3	input0_1
 !B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_3	input0_3
 !B10[26],B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_3	input0_5
 !B14[26],B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_3	input0_7
-!B10[35],B11[32],!B11[33],!B11[34],B11[35]	buffer	lc_trk_g0_3	input2_5
 !B14[35],B15[32],!B15[33],!B15[34],B15[35]	buffer	lc_trk_g0_3	input2_7
-!B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_1
-!B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_3
 !B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_5
 !B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_bram/ram/MASK_7
 !B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_1
 !B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_3
 !B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_5
 !B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_bram/ram/WDATA_7
-B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_4	input0_0
 B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_4	input0_2
 B8[26],!B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_4	input0_4
 B12[26],!B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_4	input0_6
 B12[35],B13[32],!B13[33],!B13[34],!B13[35]	buffer	lc_trk_g0_4	input2_6
 B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_bram/ram/MASK_0
-B10[31],B10[32],!B10[33],!B10[34],!B11[31]	buffer	lc_trk_g0_4	wire_bram/ram/MASK_2
-B6[31],B6[32],!B6[33],!B6[34],!B7[31]	buffer	lc_trk_g0_4	wire_bram/ram/MASK_4
-B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_bram/ram/MASK_6
 !B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_0
 !B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_2
-!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_4
-!B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_bram/ram/WDATA_6
 !B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g0_4	wire_bram/ram/WE
 B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_5	input0_1
 B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_5	input0_3
@@ -6903,10 +8078,8 @@ B10[26],!B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_5	input0_5
 B14[26],!B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_5	input0_7
 B10[35],B11[32],!B11[33],!B11[34],!B11[35]	buffer	lc_trk_g0_5	input2_5
 B14[35],B15[32],!B15[33],!B15[34],!B15[35]	buffer	lc_trk_g0_5	input2_7
-B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_1
 B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_3
 B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_5
-B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_bram/ram/MASK_7
 !B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_1
 !B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_3
 !B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_bram/ram/WDATA_5
@@ -6916,9 +8089,6 @@ B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_6	input0_2
 B8[26],B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_6	input0_4
 B12[26],B13[26],!B13[27],!B13[28],B13[29]	buffer	lc_trk_g0_6	input0_6
 B12[35],B13[32],!B13[33],!B13[34],B13[35]	buffer	lc_trk_g0_6	input2_6
-B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_0
-B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_2
-B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_4
 B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_bram/ram/MASK_6
 !B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_bram/ram/WDATA_0
 !B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_bram/ram/WDATA_2
@@ -6930,23 +8100,18 @@ B10[26],B11[26],!B11[27],!B11[28],B11[29]	buffer	lc_trk_g0_7	input0_5
 B14[26],B15[26],!B15[27],!B15[28],B15[29]	buffer	lc_trk_g0_7	input0_7
 B10[35],B11[32],!B11[33],!B11[34],B11[35]	buffer	lc_trk_g0_7	input2_5
 B14[35],B15[32],!B15[33],!B15[34],B15[35]	buffer	lc_trk_g0_7	input2_7
-B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_1
 B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_3
 B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_5
 B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_bram/ram/MASK_7
 !B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_1
-!B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_3
 !B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_5
 !B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_bram/ram/WDATA_7
 !B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_0	input0_1
 !B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_0	input0_3
 !B10[26],!B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_0	input0_5
 !B14[26],!B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_0	input0_7
-!B10[35],B11[32],!B11[33],B11[34],!B11[35]	buffer	lc_trk_g1_0	input2_5
 !B14[35],B15[32],!B15[33],B15[34],!B15[35]	buffer	lc_trk_g1_0	input2_7
-!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_1
 !B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_3
-!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_5
 !B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_bram/ram/MASK_7
 B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDATA_1
 B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDATA_3
@@ -6958,9 +8123,6 @@ B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_bram/ram/WDATA_7
 !B12[26],!B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_1	input0_6
 !B12[35],B13[32],!B13[33],B13[34],!B13[35]	buffer	lc_trk_g1_1	input2_6
 !B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_0
-!B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_2
-!B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_4
-!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_bram/ram/MASK_6
 !B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g1_1	wire_bram/ram/WCLK
 B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_0
 B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_2
@@ -6970,14 +8132,10 @@ B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_bram/ram/WDATA_6
 !B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_2	input0_3
 !B10[26],B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_2	input0_5
 !B14[26],B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_2	input0_7
-!B10[35],B11[32],!B11[33],B11[34],B11[35]	buffer	lc_trk_g1_2	input2_5
 !B14[35],B15[32],!B15[33],B15[34],B15[35]	buffer	lc_trk_g1_2	input2_7
 !B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_1
-!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_3
 !B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_5
-!B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_bram/ram/MASK_7
 B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_1
-B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_3
 B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_5
 B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_7
 !B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	input0_0
@@ -6985,7 +8143,6 @@ B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_7
 !B8[26],B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_3	input0_4
 !B12[26],B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_3	input0_6
 !B12[35],B13[32],!B13[33],B13[34],B13[35]	buffer	lc_trk_g1_3	input2_6
-!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_0
 !B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_2
 !B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_4
 !B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_bram/ram/MASK_6
@@ -6993,12 +8150,10 @@ B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_bram/ram/WDATA_7
 B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_0
 B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_2
 B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_4
-B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_bram/ram/WDATA_6
 B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_4	input0_1
 B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_4	input0_3
 B10[26],!B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_4	input0_5
 B14[26],!B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_4	input0_7
-B10[35],B11[32],!B11[33],B11[34],!B11[35]	buffer	lc_trk_g1_4	input2_5
 B14[35],B15[32],!B15[33],B15[34],!B15[35]	buffer	lc_trk_g1_4	input2_7
 B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_4	wire_bram/ram/MASK_1
 B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_4	wire_bram/ram/MASK_3
@@ -7014,24 +8169,17 @@ B8[26],!B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_5	input0_4
 B12[26],!B13[26],B13[27],!B13[28],B13[29]	buffer	lc_trk_g1_5	input0_6
 B12[35],B13[32],!B13[33],B13[34],!B13[35]	buffer	lc_trk_g1_5	input2_6
 B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_0
-B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_2
-B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_4
-B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_bram/ram/MASK_6
 B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_0
 B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_2
-B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_4
 B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_bram/ram/WDATA_6
 !B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g1_5	wire_bram/ram/WE
 B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_6	input0_1
 B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_6	input0_3
 B10[26],B11[26],B11[27],!B11[28],B11[29]	buffer	lc_trk_g1_6	input0_5
 B14[26],B15[26],B15[27],!B15[28],B15[29]	buffer	lc_trk_g1_6	input0_7
-B10[35],B11[32],!B11[33],B11[34],B11[35]	buffer	lc_trk_g1_6	input2_5
 B14[35],B15[32],!B15[33],B15[34],B15[35]	buffer	lc_trk_g1_6	input2_7
 B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_1
 B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_3
-B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_5
-B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_bram/ram/MASK_7
 B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_1
 B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_3
 B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_bram/ram/WDATA_5
@@ -7044,35 +8192,25 @@ B12[35],B13[32],!B13[33],B13[34],B13[35]	buffer	lc_trk_g1_7	input2_6
 B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_0
 B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_2
 B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_4
-B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_bram/ram/MASK_6
 B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_0
-B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_2
 B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_4
-B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_bram/ram/WDATA_6
 !B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	input0_0
 !B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_0	input0_2
 !B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_0	input0_4
 !B12[26],!B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_0	input0_6
 !B12[35],B13[32],B13[33],!B13[34],!B13[35]	buffer	lc_trk_g2_0	input2_6
-!B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_bram/ram/MASK_0
-!B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_0	wire_bram/ram/MASK_2
-!B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_0	wire_bram/ram/MASK_4
-!B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_bram/ram/MASK_6
 B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	wire_bram/ram/WCLK
 !B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_0
 !B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_2
 !B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_4
-!B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_bram/ram/WDATA_6
 !B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_1	input0_1
 !B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_1	input0_3
 !B10[26],!B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_1	input0_5
 !B14[26],!B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_1	input0_7
 !B10[35],B11[32],B11[33],!B11[34],!B11[35]	buffer	lc_trk_g2_1	input2_5
 !B14[35],B15[32],B15[33],!B15[34],!B15[35]	buffer	lc_trk_g2_1	input2_7
-!B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_1
 !B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_3
 !B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_5
-!B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_bram/ram/MASK_7
 !B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_1
 !B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_3
 !B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_bram/ram/WDATA_5
@@ -7085,7 +8223,6 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	wire_bram/ram/WCLK
 !B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_2	wire_bram/ram/MASK_0
 !B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_2	wire_bram/ram/MASK_2
 !B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_2	wire_bram/ram/MASK_4
-!B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_2	wire_bram/ram/MASK_6
 B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g2_2	wire_bram/ram/WCLKE
 !B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_bram/ram/WDATA_0
 !B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_bram/ram/WDATA_2
@@ -7099,8 +8236,6 @@ B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g2_2	wire_bram/ram/WCLKE
 !B14[35],B15[32],B15[33],!B15[34],B15[35]	buffer	lc_trk_g2_3	input2_7
 !B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_1
 !B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_3
-!B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_5
-!B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_bram/ram/MASK_7
 !B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g2_3	wire_bram/ram/WDATA_1
 !B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_bram/ram/WDATA_3
 !B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_bram/ram/WDATA_5
@@ -7111,12 +8246,9 @@ B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_4	input0_4
 B12[26],!B13[26],!B13[27],B13[28],B13[29]	buffer	lc_trk_g2_4	input0_6
 B12[35],B13[32],B13[33],!B13[34],!B13[35]	buffer	lc_trk_g2_4	input2_6
 B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_0
-B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_2
-B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_4
 B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_bram/ram/MASK_6
 !B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_0
 !B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_2
-!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_4
 !B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_bram/ram/WDATA_6
 B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g2_4	wire_bram/ram/WE
 B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_5	input0_1
@@ -7127,7 +8259,6 @@ B10[35],B11[32],B11[33],!B11[34],!B11[35]	buffer	lc_trk_g2_5	input2_5
 B14[35],B15[32],B15[33],!B15[34],!B15[35]	buffer	lc_trk_g2_5	input2_7
 B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_1
 B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_3
-B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_5
 B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_bram/ram/MASK_7
 !B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_bram/ram/WDATA_1
 !B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_bram/ram/WDATA_3
@@ -7152,7 +8283,6 @@ B10[26],B11[26],!B11[27],B11[28],B11[29]	buffer	lc_trk_g2_7	input0_5
 B14[26],B15[26],!B15[27],B15[28],B15[29]	buffer	lc_trk_g2_7	input0_7
 B10[35],B11[32],B11[33],!B11[34],B11[35]	buffer	lc_trk_g2_7	input2_5
 B14[35],B15[32],B15[33],!B15[34],B15[35]	buffer	lc_trk_g2_7	input2_7
-B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_1
 B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_3
 B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_5
 B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_7
@@ -7164,12 +8294,10 @@ B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_bram/ram/MASK_7
 !B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_0	input0_3
 !B10[26],!B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_0	input0_5
 !B14[26],!B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_0	input0_7
-!B10[35],B11[32],B11[33],B11[34],!B11[35]	buffer	lc_trk_g3_0	input2_5
 !B14[35],B15[32],B15[33],B15[34],!B15[35]	buffer	lc_trk_g3_0	input2_7
 !B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_0	wire_bram/ram/MASK_1
 !B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_0	wire_bram/ram/MASK_3
 !B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_0	wire_bram/ram/MASK_5
-!B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_0	wire_bram/ram/MASK_7
 B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_bram/ram/WDATA_1
 B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g3_0	wire_bram/ram/WDATA_3
 B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g3_0	wire_bram/ram/WDATA_5
@@ -7194,7 +8322,6 @@ B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g3_1	wire_bram/ram/WDATA_6
 !B14[26],B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_2	input0_7
 !B10[35],B11[32],B11[33],B11[34],B11[35]	buffer	lc_trk_g3_2	input2_5
 !B14[35],B15[32],B15[33],B15[34],B15[35]	buffer	lc_trk_g3_2	input2_7
-!B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_1
 !B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_3
 !B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_5
 !B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_bram/ram/MASK_7
@@ -7224,7 +8351,6 @@ B10[35],B11[32],B11[33],B11[34],!B11[35]	buffer	lc_trk_g3_4	input2_5
 B14[35],B15[32],B15[33],B15[34],!B15[35]	buffer	lc_trk_g3_4	input2_7
 B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_1
 B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_3
-B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_5
 B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_bram/ram/MASK_7
 B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_bram/ram/WDATA_1
 B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_bram/ram/WDATA_3
@@ -7237,7 +8363,6 @@ B12[26],!B13[26],B13[27],B13[28],B13[29]	buffer	lc_trk_g3_5	input0_6
 B12[35],B13[32],B13[33],B13[34],!B13[35]	buffer	lc_trk_g3_5	input2_6
 B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_0
 B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_2
-B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_4
 B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_bram/ram/MASK_6
 B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_bram/ram/WDATA_0
 B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_bram/ram/WDATA_2
@@ -7250,14 +8375,12 @@ B10[26],B11[26],B11[27],B11[28],B11[29]	buffer	lc_trk_g3_6	input0_5
 B14[26],B15[26],B15[27],B15[28],B15[29]	buffer	lc_trk_g3_6	input0_7
 B10[35],B11[32],B11[33],B11[34],B11[35]	buffer	lc_trk_g3_6	input2_5
 B14[35],B15[32],B15[33],B15[34],B15[35]	buffer	lc_trk_g3_6	input2_7
-B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_1
 B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_3
 B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_5
 B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_bram/ram/MASK_7
 B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g3_6	wire_bram/ram/WDATA_1
 B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_bram/ram/WDATA_3
 B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_bram/ram/WDATA_5
-B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g3_6	wire_bram/ram/WDATA_7
 B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_7	input0_0
 B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_7	input0_2
 B8[26],B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_7	input0_4
@@ -7272,12 +8395,10 @@ B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_2
 B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_4
 B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_bram/ram/WDATA_6
 B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	lft_op_0	lc_trk_g0_0
-B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
 B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
 B4[15],!B4[16],B4[17],B4[18],!B5[18]	buffer	lft_op_1	lc_trk_g1_1
 B0[25],B1[22],!B1[23],B1[24],!B1[25]	buffer	lft_op_2	lc_trk_g0_2
 B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	lft_op_2	lc_trk_g1_2
-B0[21],B0[22],!B0[23],B0[24],!B1[21]	buffer	lft_op_3	lc_trk_g0_3
 B4[21],B4[22],!B4[23],B4[24],!B5[21]	buffer	lft_op_3	lc_trk_g1_3
 B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	lft_op_4	lc_trk_g0_4
 B6[14],!B7[14],B7[15],!B7[16],B7[17]	buffer	lft_op_4	lc_trk_g1_4
@@ -7289,82 +8410,47 @@ B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	lft_op_7	lc_trk_g0_7
 B6[21],B6[22],!B6[23],B6[24],!B7[21]	buffer	lft_op_7	lc_trk_g1_7
 B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	rgt_op_0	lc_trk_g2_0
 B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	rgt_op_0	lc_trk_g3_0
-B8[15],!B8[16],B8[17],B8[18],!B9[18]	buffer	rgt_op_1	lc_trk_g2_1
-B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	rgt_op_1	lc_trk_g3_1
 B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	rgt_op_2	lc_trk_g2_2
 B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	rgt_op_2	lc_trk_g3_2
-B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	rgt_op_3	lc_trk_g2_3
 B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	rgt_op_3	lc_trk_g3_3
-B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	rgt_op_4	lc_trk_g2_4
 B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	rgt_op_4	lc_trk_g3_4
 B10[15],!B10[16],B10[17],B10[18],!B11[18]	buffer	rgt_op_5	lc_trk_g2_5
 B14[15],!B14[16],B14[17],B14[18],!B15[18]	buffer	rgt_op_5	lc_trk_g3_5
 B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	rgt_op_6	lc_trk_g2_6
 B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	rgt_op_6	lc_trk_g3_6
-B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	rgt_op_7	lc_trk_g2_7
 B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
 B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_l_0	lc_trk_g0_3
 B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_l_0	lc_trk_g1_3
-!B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_l_12	lc_trk_g0_7
-!B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_l_12	lc_trk_g1_7
-!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_l_13	lc_trk_g0_6
-!B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_l_13	lc_trk_g1_6
 B6[2]	buffer	sp12_h_l_13	sp4_h_r_19
-!B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_l_16	lc_trk_g0_3
-!B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_l_16	lc_trk_g1_3
-!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_l_18	lc_trk_g0_5
-!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_l_18	lc_trk_g1_5
 !B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_l_21	lc_trk_g0_6
-!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_l_21	lc_trk_g1_6
 B14[2]	buffer	sp12_h_l_21	sp4_h_l_10
 B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_l_3	lc_trk_g0_4
 B6[14],B7[14],B7[15],!B7[16],B7[17]	buffer	sp12_h_l_3	lc_trk_g1_4
 B15[19]	buffer	sp12_h_l_3	sp4_h_l_3
-B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_l_4	lc_trk_g0_7
-B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_l_4	lc_trk_g1_7
-B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_l_5	lc_trk_g0_6
 B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_l_5	lc_trk_g1_6
 B14[19]	buffer	sp12_h_l_5	sp4_h_l_2
 !B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_l_6	lc_trk_g0_1
 !B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_l_6	lc_trk_g1_1
-B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
 B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	sp12_h_r_0	lc_trk_g1_0
 B13[19]	buffer	sp12_h_r_0	sp4_h_r_12
 B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	sp12_h_r_1	lc_trk_g0_1
 B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
-!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_r_10	lc_trk_g0_2
 !B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_r_10	lc_trk_g1_2
 B3[1]	buffer	sp12_h_r_10	sp4_h_r_17
-!B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp12_h_r_11	lc_trk_g0_3
-!B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp12_h_r_11	lc_trk_g1_3
-!B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_12	lc_trk_g0_4
-!B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_12	lc_trk_g1_4
 B4[2]	buffer	sp12_h_r_12	sp4_h_l_7
 !B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_r_13	lc_trk_g0_5
-!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_r_13	lc_trk_g1_5
-!B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_16	lc_trk_g0_0
-!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_16	lc_trk_g1_0
 B8[2]	buffer	sp12_h_r_16	sp4_h_r_20
-!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_r_17	lc_trk_g0_1
 !B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_r_17	lc_trk_g1_1
-!B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_r_18	lc_trk_g0_2
-!B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_r_18	lc_trk_g1_2
 B10[2]	buffer	sp12_h_r_18	sp4_h_l_8
 B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_r_2	lc_trk_g0_2
 B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_r_2	lc_trk_g1_2
 B12[19]	buffer	sp12_h_r_2	sp4_h_r_13
-!B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_20	lc_trk_g0_4
-!B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_20	lc_trk_g1_4
 B12[2]	buffer	sp12_h_r_20	sp4_h_r_22
-!B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_r_23	lc_trk_g0_7
-!B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_r_23	lc_trk_g1_7
 B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_r_5	lc_trk_g0_5
 B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_r_5	lc_trk_g1_5
 !B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_8	lc_trk_g0_0
 !B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_8	lc_trk_g1_0
 B0[2]	buffer	sp12_h_r_8	sp4_h_l_5
-B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
-B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
 B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
 B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
 B1[19]	buffer	sp12_v_b_1	sp4_v_t_1
@@ -7372,7 +8458,6 @@ B1[19]	buffer	sp12_v_b_1	sp4_v_t_1
 !B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_b_11	lc_trk_g3_3
 B4[19]	buffer	sp12_v_b_11	sp4_v_b_17
 !B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_12	lc_trk_g2_4
-!B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_12	lc_trk_g3_4
 !B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp12_v_b_14	lc_trk_g2_6
 !B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp12_v_b_14	lc_trk_g3_6
 !B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_16	lc_trk_g2_0
@@ -7414,11 +8499,9 @@ B8[19]	buffer	sp12_v_t_16	sp4_v_t_8
 !B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp12_v_t_17	lc_trk_g2_2
 !B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp12_v_t_17	lc_trk_g3_2
 !B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_t_19	lc_trk_g2_4
-!B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_t_19	lc_trk_g3_4
 !B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_t_21	lc_trk_g2_6
 !B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_t_21	lc_trk_g3_6
 B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_t_3	lc_trk_g2_4
-B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_t_3	lc_trk_g3_4
 !B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_t_7	lc_trk_g2_0
 !B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_t_7	lc_trk_g3_0
 !B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_t_9	lc_trk_g2_2
@@ -7426,7 +8509,6 @@ B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_t_3	lc_trk_g3_4
 B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_l_10	lc_trk_g0_7
 B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_l_10	lc_trk_g1_7
 !B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_13	lc_trk_g2_0
-!B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_13	lc_trk_g3_0
 !B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_l_15	lc_trk_g2_2
 !B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_l_15	lc_trk_g3_2
 B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_h_l_16	lc_trk_g2_5
@@ -7438,11 +8520,7 @@ B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_h_l_16	lc_trk_g3_5
 B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_h_l_2	lc_trk_g0_7
 B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_h_l_2	lc_trk_g1_7
 B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_h_l_20	lc_trk_g2_1
-B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_h_l_20	lc_trk_g3_1
 B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_21	lc_trk_g2_0
-B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_21	lc_trk_g3_0
-B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_l_26	lc_trk_g2_7
-B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_l_26	lc_trk_g3_7
 B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_l_27	lc_trk_g2_6
 B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_l_27	lc_trk_g3_6
 B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_h_l_28	lc_trk_g2_1
@@ -7461,7 +8539,6 @@ B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_l_8	lc_trk_g0_5
 B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_l_8	lc_trk_g1_5
 !B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
 !B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
-B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
 B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
 B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
 B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
@@ -7476,43 +8553,33 @@ B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_h_r_17	lc_trk_g1_1
 B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_19	lc_trk_g0_3
 B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_19	lc_trk_g1_3
 !B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_2	lc_trk_g0_2
-!B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_2	lc_trk_g1_2
 B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_20	lc_trk_g0_4
 B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_20	lc_trk_g1_4
 B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_22	lc_trk_g0_6
 B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_22	lc_trk_g1_6
 B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_r_25	lc_trk_g2_1
 B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_r_25	lc_trk_g3_1
-!B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_27	lc_trk_g2_3
 !B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_27	lc_trk_g3_3
-!B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_3	lc_trk_g0_3
 !B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_3	lc_trk_g1_3
 !B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_30	lc_trk_g2_6
-!B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_30	lc_trk_g3_6
 B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_h_r_34	lc_trk_g2_2
 B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_h_r_34	lc_trk_g3_2
 B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_r_35	lc_trk_g2_3
 B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_r_35	lc_trk_g3_3
 B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_36	lc_trk_g2_4
-B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_36	lc_trk_g3_4
-B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_r_37	lc_trk_g2_5
 B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_r_37	lc_trk_g3_5
 !B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
 !B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
 B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_42	lc_trk_g2_2
 B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_42	lc_trk_g3_2
 B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_44	lc_trk_g2_4
-B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_44	lc_trk_g3_4
 B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_h_r_45	lc_trk_g2_5
-B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_r_45	lc_trk_g3_5
 B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_46	lc_trk_g2_6
 B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_46	lc_trk_g3_6
 B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_r_47	lc_trk_g2_7
-B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_r_47	lc_trk_g3_7
 B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
 B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
 !B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
-!B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_6	lc_trk_g1_6
 !B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
 !B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
 B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
@@ -7675,11 +8742,9 @@ B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp4_v_t_26	lc_trk_g3_7
 !B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_v_t_7	lc_trk_g1_2
 B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp4_v_t_8	lc_trk_g0_5
 B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_t_8	lc_trk_g1_5
-!B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
 !B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
 B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
 B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	tnl_op_1	lc_trk_g3_1
-!B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
 !B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
 !B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
 !B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
@@ -7689,8 +8754,6 @@ B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	tnl_op_5	lc_trk_g2_5
 B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	tnl_op_5	lc_trk_g3_5
 !B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	tnl_op_6	lc_trk_g2_6
 !B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	tnl_op_6	lc_trk_g3_6
-!B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	tnl_op_7	lc_trk_g2_7
-!B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	tnl_op_7	lc_trk_g3_7
 !B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	tnr_op_0	lc_trk_g2_0
 !B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
 B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	tnr_op_1	lc_trk_g2_1
@@ -7707,17 +8770,11 @@ B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
 !B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
 !B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
 !B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
-!B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	top_op_2	lc_trk_g0_2
-!B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	top_op_2	lc_trk_g1_2
-!B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	top_op_4	lc_trk_g0_4
-!B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	top_op_6	lc_trk_g0_6
-!B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	top_op_6	lc_trk_g1_6
 B15[38]	buffer	wire_bram/ram/RDATA_0	sp12_h_l_21
 B14[37]	buffer	wire_bram/ram/RDATA_0	sp12_h_l_5
 B15[40]	buffer	wire_bram/ram/RDATA_0	sp12_v_b_14
 B15[36]	buffer	wire_bram/ram/RDATA_0	sp4_h_l_3
 B15[37]	buffer	wire_bram/ram/RDATA_0	sp4_h_r_30
-B14[36]	buffer	wire_bram/ram/RDATA_0	sp4_h_r_46
 B15[41]	buffer	wire_bram/ram/RDATA_0	sp4_r_v_b_15
 B14[40]	buffer	wire_bram/ram/RDATA_0	sp4_r_v_b_31
 B14[41]	buffer	wire_bram/ram/RDATA_0	sp4_r_v_b_47
@@ -7741,19 +8798,16 @@ B10[37]	buffer	wire_bram/ram/RDATA_2	sp12_h_r_2
 B11[40]	buffer	wire_bram/ram/RDATA_2	sp12_v_t_9
 B11[37]	buffer	wire_bram/ram/RDATA_2	sp4_h_l_15
 B11[36]	buffer	wire_bram/ram/RDATA_2	sp4_h_r_10
-B10[36]	buffer	wire_bram/ram/RDATA_2	sp4_h_r_42
 B11[41]	buffer	wire_bram/ram/RDATA_2	sp4_r_v_b_11
 B10[40]	buffer	wire_bram/ram/RDATA_2	sp4_r_v_b_27
 B10[41]	buffer	wire_bram/ram/RDATA_2	sp4_r_v_b_43
 B11[39]	buffer	wire_bram/ram/RDATA_2	sp4_v_b_10
-B10[38]	buffer	wire_bram/ram/RDATA_2	sp4_v_b_26
 B10[39]	buffer	wire_bram/ram/RDATA_2	sp4_v_t_31
 B8[37]	buffer	wire_bram/ram/RDATA_3	sp12_h_r_0
 B9[38]	buffer	wire_bram/ram/RDATA_3	sp12_h_r_16
 B9[40]	buffer	wire_bram/ram/RDATA_3	sp12_v_t_7
 B9[37]	buffer	wire_bram/ram/RDATA_3	sp4_h_l_13
 B8[36]	buffer	wire_bram/ram/RDATA_3	sp4_h_l_29
-B9[36]	buffer	wire_bram/ram/RDATA_3	sp4_h_r_8
 B8[40]	buffer	wire_bram/ram/RDATA_3	sp4_r_v_b_25
 B8[41]	buffer	wire_bram/ram/RDATA_3	sp4_r_v_b_41
 B9[41]	buffer	wire_bram/ram/RDATA_3	sp4_r_v_b_9
@@ -7788,9 +8842,7 @@ B2[37]	buffer	wire_bram/ram/RDATA_6	sp12_h_r_10
 B2[39]	buffer	wire_bram/ram/RDATA_6	sp12_v_b_2
 B3[40]	buffer	wire_bram/ram/RDATA_6	sp12_v_t_17
 B3[37]	buffer	wire_bram/ram/RDATA_6	sp4_h_l_7
-B3[36]	buffer	wire_bram/ram/RDATA_6	sp4_h_r_2
 B2[36]	buffer	wire_bram/ram/RDATA_6	sp4_h_r_34
-B2[40]	buffer	wire_bram/ram/RDATA_6	sp4_r_v_b_19
 B3[41]	buffer	wire_bram/ram/RDATA_6	sp4_r_v_b_3
 B2[41]	buffer	wire_bram/ram/RDATA_6	sp4_r_v_b_35
 B3[38]	buffer	wire_bram/ram/RDATA_6	sp4_v_b_2
@@ -7801,9 +8853,6 @@ B0[39]	buffer	wire_bram/ram/RDATA_7	sp12_v_b_0
 B1[40]	buffer	wire_bram/ram/RDATA_7	sp12_v_b_16
 B0[36]	buffer	wire_bram/ram/RDATA_7	sp4_h_l_21
 B1[37]	buffer	wire_bram/ram/RDATA_7	sp4_h_l_5
-B1[36]	buffer	wire_bram/ram/RDATA_7	sp4_h_r_0
-B1[41]	buffer	wire_bram/ram/RDATA_7	sp4_r_v_b_1
-B0[40]	buffer	wire_bram/ram/RDATA_7	sp4_r_v_b_17
 B0[41]	buffer	wire_bram/ram/RDATA_7	sp4_r_v_b_33
 B1[38]	buffer	wire_bram/ram/RDATA_7	sp4_v_b_0
 B1[39]	buffer	wire_bram/ram/RDATA_7	sp4_v_b_16
@@ -7854,6 +8903,7 @@ B12[4],B12[6],B13[5]	routing	sp4_h_l_38	sp4_v_b_9
 !B6[4],!B6[6],B7[5]	routing	sp4_h_l_38	sp4_v_t_38
 B10[11],!B10[13],!B11[12]	routing	sp4_h_l_38	sp4_v_t_45
 B12[8],!B12[9],B12[10]	routing	sp4_h_l_39	sp4_h_r_10
+!B0[12],B1[11],!B1[13]	routing	sp4_h_l_39	sp4_h_r_2
 B4[12],!B5[11],B5[13]	routing	sp4_h_l_39	sp4_h_r_5
 !B0[11],B0[13],B1[12]	routing	sp4_h_l_39	sp4_v_b_2
 B8[11],B8[13],B9[12]	routing	sp4_h_l_39	sp4_v_b_8
@@ -7888,6 +8938,7 @@ B8[4],!B8[6],B9[5]	routing	sp4_h_l_43	sp4_v_b_6
 !B10[4],!B10[6],B11[5]	routing	sp4_h_l_43	sp4_v_t_43
 B14[11],!B14[13],!B15[12]	routing	sp4_h_l_43	sp4_v_t_46
 B0[5],B1[4],!B1[6]	routing	sp4_h_l_44	sp4_h_r_0
+!B4[12],B5[11],B5[13]	routing	sp4_h_l_44	sp4_h_r_5
 !B12[5],!B13[4],B13[6]	routing	sp4_h_l_44	sp4_h_r_9
 B4[4],B4[6],B5[5]	routing	sp4_h_l_44	sp4_v_b_3
 B12[4],!B12[6],B13[5]	routing	sp4_h_l_44	sp4_v_b_9
@@ -11034,3 +12085,5002 @@ B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
 !B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
 B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
 """
+database_dsp0_5k_txt = """
+B0[50]	Cascade	MULT0_LC00_inmux02_5
+B2[50]	Cascade	MULT0_LC01_inmux02_5
+B4[50]	Cascade	MULT0_LC02_inmux02_5
+B6[50]	Cascade	MULT0_LC03_inmux02_5
+B8[50]	Cascade	MULT0_LC04_inmux02_5
+B10[50]	Cascade	MULT0_LC05_inmux02_5
+B12[50]	Cascade	MULT0_LC06_inmux02_5
+B14[50]	Cascade	MULT0_LC07_inmux02_5
+B9[7]	ColBufCtrl	8k_glb_netwk_0
+B8[7]	ColBufCtrl	8k_glb_netwk_1
+B11[7]	ColBufCtrl	8k_glb_netwk_2
+B10[7]	ColBufCtrl	8k_glb_netwk_3
+B13[7]	ColBufCtrl	8k_glb_netwk_4
+B12[7]	ColBufCtrl	8k_glb_netwk_5
+B15[7]	ColBufCtrl	8k_glb_netwk_6
+B14[7]	ColBufCtrl	8k_glb_netwk_7
+B1[7]	IpConfig	CBIT_0
+B0[7]	IpConfig	CBIT_1
+B3[7]	IpConfig	CBIT_2
+B2[7]	IpConfig	CBIT_3
+B5[7]	IpConfig	CBIT_4
+B4[7]	IpConfig	CBIT_5
+B7[7]	IpConfig	CBIT_6
+B6[7]	IpConfig	CBIT_7
+B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43]	LC_0
+B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43]	LC_1
+B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43]	LC_2
+B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43]	LC_3
+B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43]	LC_4
+B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43]	LC_5
+B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43]	LC_6
+B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43]	LC_7
+B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	bnl_op_0	lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	bnl_op_0	lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	bnl_op_1	lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	bnl_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	bnl_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	bnl_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	bnl_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	bnl_op_3	lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	bnl_op_4	lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	bnl_op_4	lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	bnl_op_5	lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	bnl_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	bnl_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	bnl_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	bnl_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	bnl_op_7	lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	bnr_op_0	lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	bnr_op_0	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	bnr_op_1	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	bnr_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	bnr_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	bnr_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	bnr_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	bnr_op_3	lc_trk_g1_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	bnr_op_4	lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	bnr_op_4	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	bnr_op_5	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	bnr_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	bnr_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	bnr_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	bnr_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	bnr_op_7	lc_trk_g1_7
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17]	buffer	glb2local_0	lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_0	glb2local_0
+!B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_0	glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_0	glb2local_3
+!B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_0	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
+!B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_1	glb2local_1
+!B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_1	glb2local_2
+!B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_1	glb2local_3
+B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_2	glb2local_0
+B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_2	glb2local_1
+B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_2	glb2local_2
+B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_2	glb2local_3
+!B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_2	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_3	glb2local_0
+B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_3	glb2local_1
+B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
+B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_3	glb2local_3
+!B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_4	glb2local_0
+!B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_4	glb2local_1
+!B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
+!B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_4	glb2local_3
+B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
+!B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
+!B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_5	glb2local_2
+!B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
+B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_6	glb2local_0
+B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_6	glb2local_1
+B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
+B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_6	glb2local_3
+B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_6	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_7	glb2local_0
+B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_7	glb2local_1
+B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_7	glb2local_2
+B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_7	glb2local_3
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g0_0	wire_mult/lc_1/in_1
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_0	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g0_0	wire_mult/lc_3/in_1
+!B8[26],!B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_0	wire_mult/lc_4/in_0
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g0_0	wire_mult/lc_5/in_1
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g0_0	wire_mult/lc_7/in_1
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g0_1	wire_mult/lc_0/in_1
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_1	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g0_1	wire_mult/lc_2/in_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_1	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_mult/lc_4/in_1
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g0_1	wire_mult/lc_6/in_1
+!B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_2	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_3
+!B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_2	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_3
+!B8[26],B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_2	wire_mult/lc_4/in_0
+!B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_3
+!B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_3	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_3
+!B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_3	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_4	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_3
+B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_4	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],!B7[31]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_3
+B8[26],!B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_4	wire_mult/lc_4/in_0
+!B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],!B11[31]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_3
+!B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g0_4	wire_mult/lc_7/s_r
+!B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_3
+B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_5	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_3
+B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_5	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_6	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_3
+B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_6	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_3
+B8[26],B9[26],!B9[27],!B9[28],B9[29]	buffer	lc_trk_g0_6	wire_mult/lc_4/in_0
+!B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_3
+B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_7	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_3
+B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_7	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_3
+B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_3
+!B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_0	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_3
+!B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_0	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_1	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_3
+!B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_1	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_3
+!B8[26],!B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_1	wire_mult/lc_4/in_0
+B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_3
+!B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_2	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_3
+!B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_2	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_3
+!B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_3	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_3
+!B8[26],B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_3	wire_mult/lc_4/in_0
+B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_3
+B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_4	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_3
+B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_4	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_5	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_3
+B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_5	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_3
+B8[26],!B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_5	wire_mult/lc_4/in_0
+B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_3
+!B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g1_5	wire_mult/lc_7/s_r
+B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_3
+B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_6	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_3
+B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_6	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_7	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_3
+B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_7	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_3
+B8[26],B9[26],B9[27],!B9[28],B9[29]	buffer	lc_trk_g1_7	wire_mult/lc_4/in_0
+B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_3
+!B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_3
+!B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_0	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_3
+!B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_0	wire_mult/lc_4/in_0
+!B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_3
+!B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_1	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_3
+!B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_1	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_3
+!B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_2	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_3
+!B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_2	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_3
+!B8[26],B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_2	wire_mult/lc_4/in_0
+!B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_3
+!B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_3	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_3
+!B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_3	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_4	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_3
+B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_4	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_3
+B8[26],!B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_4	wire_mult/lc_4/in_0
+!B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_3
+B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g2_4	wire_mult/lc_7/s_r
+!B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_3
+B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_5	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_3
+B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_5	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_6	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_3
+B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_6	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_3
+B8[26],B9[26],!B9[27],B9[28],B9[29]	buffer	lc_trk_g2_6	wire_mult/lc_4/in_0
+!B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_3
+B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_7	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_3
+B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_7	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_3
+B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_3
+!B2[26],!B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_0	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_3
+!B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_0	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_1	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_3
+!B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_1	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_3
+!B8[26],!B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_1	wire_mult/lc_4/in_0
+B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_3
+!B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_2	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_3
+!B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_2	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_3	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_3
+!B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_3	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_3
+!B8[26],B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_3	wire_mult/lc_4/in_0
+B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_3
+B2[26],!B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_4	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_3
+B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_4	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_5	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_3
+B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_5	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_3
+B8[26],!B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_5	wire_mult/lc_4/in_0
+B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_3
+B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g3_5	wire_mult/lc_7/s_r
+B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_3
+B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_6	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_3
+B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_6	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_7	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_3
+B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_7	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_3
+B8[26],B9[26],B9[27],B9[28],B9[29]	buffer	lc_trk_g3_7	wire_mult/lc_4/in_0
+B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_3
+B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	lft_op_0	lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18]	buffer	lft_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25]	buffer	lft_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	lft_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21]	buffer	lft_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21]	buffer	lft_op_3	lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	lft_op_4	lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17]	buffer	lft_op_4	lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18]	buffer	lft_op_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18]	buffer	lft_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25]	buffer	lft_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25]	buffer	lft_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	lft_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21]	buffer	lft_op_7	lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	rgt_op_0	lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	rgt_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18]	buffer	rgt_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	rgt_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	rgt_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	rgt_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	rgt_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	rgt_op_3	lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	rgt_op_4	lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	rgt_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18]	buffer	rgt_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18]	buffer	rgt_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	rgt_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	rgt_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	rgt_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
+B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_l_1	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_l_1	lc_trk_g1_2
+B12[19]	buffer	sp12_h_l_1	sp4_h_l_0
+!B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_l_10	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_l_10	lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_l_12	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_l_12	lc_trk_g1_7
+!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_l_14	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_l_14	lc_trk_g1_1
+!B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_l_15	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_l_15	lc_trk_g1_0
+B8[2]	buffer	sp12_h_l_15	sp4_h_r_20
+!B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_l_16	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_l_16	lc_trk_g1_3
+!B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_l_17	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_l_17	lc_trk_g1_2
+B10[2]	buffer	sp12_h_l_17	sp4_h_l_8
+!B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_l_19	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_l_19	lc_trk_g1_4
+B12[2]	buffer	sp12_h_l_19	sp4_h_l_11
+B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_l_2	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_l_2	lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_l_20	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_l_20	lc_trk_g1_7
+B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_l_3	lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17]	buffer	sp12_h_l_3	lc_trk_g1_4
+B15[19]	buffer	sp12_h_l_3	sp4_h_l_3
+B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_l_5	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_l_5	lc_trk_g1_6
+B14[19]	buffer	sp12_h_l_5	sp4_h_r_15
+!B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_l_7	lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_l_7	lc_trk_g1_0
+B0[2]	buffer	sp12_h_l_7	sp4_h_l_5
+!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_l_9	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_l_9	lc_trk_g1_2
+B3[1]	buffer	sp12_h_l_9	sp4_h_r_17
+B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	sp12_h_r_0	lc_trk_g1_0
+B13[19]	buffer	sp12_h_r_0	sp4_h_r_12
+B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	sp12_h_r_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
+!B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp12_h_r_11	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp12_h_r_11	lc_trk_g1_3
+!B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_12	lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_12	lc_trk_g1_4
+B4[2]	buffer	sp12_h_r_12	sp4_h_l_7
+!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_r_14	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_r_14	lc_trk_g1_6
+B6[2]	buffer	sp12_h_r_14	sp4_h_r_19
+!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_r_21	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_r_21	lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_r_22	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_r_22	lc_trk_g1_6
+B14[2]	buffer	sp12_h_r_22	sp4_h_l_10
+B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_r_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_r_3	lc_trk_g1_3
+B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_r_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_r_7	lc_trk_g1_7
+!B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_r_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_r_9	lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
+B1[19]	buffer	sp12_v_b_1	sp4_v_t_1
+!B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_b_10	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp12_v_b_10	lc_trk_g3_2
+!B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp12_v_b_19	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp12_v_b_19	lc_trk_g3_3
+B8[19]	buffer	sp12_v_b_19	sp4_v_t_8
+B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	sp12_v_b_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	sp12_v_b_2	lc_trk_g3_2
+!B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_20	lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_20	lc_trk_g3_4
+!B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp12_v_b_21	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp12_v_b_21	lc_trk_g3_5
+B11[19]	buffer	sp12_v_b_21	sp4_v_t_11
+!B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp12_v_b_23	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp12_v_b_23	lc_trk_g3_7
+B10[19]	buffer	sp12_v_b_23	sp4_v_t_10
+B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_b_4	lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_b_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	sp12_v_b_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	sp12_v_b_5	lc_trk_g3_5
+B3[19]	buffer	sp12_v_b_5	sp4_v_b_14
+B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	sp12_v_b_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	sp12_v_b_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	sp12_v_b_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	sp12_v_b_7	lc_trk_g3_7
+B2[19]	buffer	sp12_v_b_7	sp4_v_t_2
+!B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_8	lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_b_8	lc_trk_g3_0
+!B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp12_v_b_9	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp12_v_b_9	lc_trk_g3_1
+B5[19]	buffer	sp12_v_b_9	sp4_v_b_16
+B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	sp12_v_t_0	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	sp12_v_t_0	lc_trk_g3_3
+B0[19]	buffer	sp12_v_t_0	sp4_v_b_13
+!B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp12_v_t_10	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp12_v_t_10	lc_trk_g3_5
+B7[19]	buffer	sp12_v_t_10	sp4_v_b_18
+!B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_t_11	lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_t_11	lc_trk_g3_4
+!B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp12_v_t_12	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp12_v_t_12	lc_trk_g3_7
+B6[19]	buffer	sp12_v_t_12	sp4_v_t_6
+!B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp12_v_t_13	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp12_v_t_13	lc_trk_g3_6
+!B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp12_v_t_14	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp12_v_t_14	lc_trk_g3_1
+B9[19]	buffer	sp12_v_t_14	sp4_v_b_20
+!B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_t_15	lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_t_15	lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp12_v_t_17	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp12_v_t_17	lc_trk_g3_2
+!B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_t_21	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_t_21	lc_trk_g3_6
+!B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp12_v_t_8	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_t_8	lc_trk_g3_3
+B4[19]	buffer	sp12_v_t_8	sp4_v_t_4
+B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_h_l_0	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_h_l_0	lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_l_10	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_l_10	lc_trk_g1_7
+B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_l_11	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_l_11	lc_trk_g1_6
+!B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_13	lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_13	lc_trk_g3_0
+!B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_l_14	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_l_14	lc_trk_g3_3
+!B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_17	lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_17	lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_l_18	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_l_18	lc_trk_g3_7
+B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_h_l_20	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_h_l_20	lc_trk_g3_1
+B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_l_22	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_l_22	lc_trk_g3_3
+B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_h_l_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_h_l_23	lc_trk_g3_2
+B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_l_24	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_l_24	lc_trk_g3_5
+B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_29	lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_29	lc_trk_g3_0
+B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_h_l_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_h_l_3	lc_trk_g1_6
+B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_l_30	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_l_30	lc_trk_g3_3
+B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_l_31	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_l_31	lc_trk_g3_2
+B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_h_l_32	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_l_32	lc_trk_g3_5
+B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_33	lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_33	lc_trk_g3_4
+B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_l_35	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_l_35	lc_trk_g3_6
+B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_l_5	lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_l_5	lc_trk_g1_0
+B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_l_7	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_l_7	lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_l_8	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_l_8	lc_trk_g1_5
+!B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_h_r_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_h_r_11	lc_trk_g1_3
+B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_12	lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_12	lc_trk_g1_4
+B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_h_r_15	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_h_r_15	lc_trk_g1_7
+B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_h_r_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_h_r_17	lc_trk_g1_1
+B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_19	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_19	lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_2	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_2	lc_trk_g1_2
+B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_20	lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_20	lc_trk_g1_4
+B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_r_25	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_r_25	lc_trk_g3_1
+!B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_26	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_26	lc_trk_g3_2
+B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_h_r_29	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_h_r_29	lc_trk_g3_5
+!B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_3	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_3	lc_trk_g1_3
+!B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_30	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_30	lc_trk_g3_6
+B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_32	lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_32	lc_trk_g3_0
+B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_36	lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_36	lc_trk_g3_4
+B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_r_38	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_r_38	lc_trk_g3_6
+B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_r_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_r_39	lc_trk_g3_7
+!B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
+B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_h_r_41	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_h_r_41	lc_trk_g3_1
+B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_r_47	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_r_47	lc_trk_g3_7
+B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_6	lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_8	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_h_r_9	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_h_r_9	lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_0	lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_r_v_b_1	lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25]	buffer	sp4_r_v_b_10	lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21]	buffer	sp4_r_v_b_11	lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_12	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_r_v_b_13	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25]	buffer	sp4_r_v_b_14	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21]	buffer	sp4_r_v_b_15	lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_16	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_r_v_b_17	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25]	buffer	sp4_r_v_b_18	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21]	buffer	sp4_r_v_b_19	lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25]	buffer	sp4_r_v_b_2	lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_20	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_r_v_b_21	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25]	buffer	sp4_r_v_b_22	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21]	buffer	sp4_r_v_b_23	lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_24	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_24	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_r_v_b_25	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_r_v_b_25	lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25]	buffer	sp4_r_v_b_26	lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	sp4_r_v_b_26	lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21]	buffer	sp4_r_v_b_27	lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	sp4_r_v_b_27	lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	sp4_r_v_b_28	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_28	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_r_v_b_29	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_r_v_b_29	lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21]	buffer	sp4_r_v_b_3	lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	sp4_r_v_b_30	lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	sp4_r_v_b_30	lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	sp4_r_v_b_31	lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	sp4_r_v_b_31	lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	sp4_r_v_b_32	lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_32	lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	sp4_r_v_b_33	lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_r_v_b_33	lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_r_v_b_34	lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	sp4_r_v_b_34	lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_35	lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	sp4_r_v_b_35	lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_36	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_r_v_b_37	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	sp4_r_v_b_38	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	sp4_r_v_b_39	lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_4	lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_40	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_r_v_b_41	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	sp4_r_v_b_42	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	sp4_r_v_b_43	lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_44	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_r_v_b_45	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	sp4_r_v_b_46	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	sp4_r_v_b_47	lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_r_v_b_5	lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25]	buffer	sp4_r_v_b_6	lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21]	buffer	sp4_r_v_b_7	lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_8	lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_r_v_b_9	lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_0	lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_0	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_v_b_1	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_v_b_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp4_v_b_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp4_v_b_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp4_v_b_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp4_v_b_11	lc_trk_g1_3
+!B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_v_b_13	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_v_b_13	lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp4_v_b_14	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp4_v_b_14	lc_trk_g1_6
+!B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_v_b_16	lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_v_b_16	lc_trk_g1_0
+!B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_v_b_18	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_v_b_18	lc_trk_g1_2
+B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp4_v_b_2	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp4_v_b_2	lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_v_b_20	lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_v_b_20	lc_trk_g1_4
+B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_b_24	lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_b_24	lc_trk_g3_0
+!B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_v_b_25	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_v_b_25	lc_trk_g3_1
+B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp4_v_b_27	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp4_v_b_27	lc_trk_g3_3
+B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_b_28	lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_b_28	lc_trk_g3_4
+!B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_v_b_29	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_v_b_29	lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp4_v_b_3	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp4_v_b_3	lc_trk_g1_3
+B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp4_v_b_30	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp4_v_b_30	lc_trk_g3_6
+!B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_v_b_33	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_v_b_33	lc_trk_g3_1
+B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_b_36	lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_b_36	lc_trk_g3_4
+B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp4_v_b_38	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp4_v_b_38	lc_trk_g3_6
+B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp4_v_b_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp4_v_b_39	lc_trk_g3_7
+B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_4	lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_4	lc_trk_g1_4
+!B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_v_b_43	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_v_b_43	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_v_b_44	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_v_b_44	lc_trk_g3_4
+B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_v_b_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_v_b_45	lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_v_b_46	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_v_b_46	lc_trk_g3_6
+!B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_v_b_5	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_v_b_5	lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp4_v_b_6	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp4_v_b_6	lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp4_v_b_7	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp4_v_b_7	lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_8	lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_8	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_v_b_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_v_b_9	lc_trk_g1_1
+B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_t_1	lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_t_1	lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_v_t_10	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_v_t_10	lc_trk_g1_7
+!B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_v_t_11	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_v_t_11	lc_trk_g1_6
+B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp4_v_t_15	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp4_v_t_15	lc_trk_g3_2
+B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp4_v_t_18	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp4_v_t_18	lc_trk_g3_7
+B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp4_v_t_2	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp4_v_t_2	lc_trk_g1_7
+B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_t_21	lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_t_21	lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp4_v_t_22	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp4_v_t_22	lc_trk_g3_3
+B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp4_v_t_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp4_v_t_23	lc_trk_g3_2
+!B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_v_t_24	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_v_t_24	lc_trk_g3_5
+B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_v_t_28	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_v_t_28	lc_trk_g3_1
+!B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_v_t_29	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_v_t_29	lc_trk_g3_0
+!B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_v_t_31	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_v_t_31	lc_trk_g3_2
+!B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_v_t_34	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_v_t_34	lc_trk_g3_7
+B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_v_t_4	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_v_t_4	lc_trk_g1_1
+!B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_v_t_6	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_v_t_6	lc_trk_g1_3
+B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp4_v_t_8	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_t_8	lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	tnl_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	tnl_op_4	lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	tnl_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	tnl_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	tnl_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	tnl_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	tnl_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	tnl_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	tnl_op_7	lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	tnr_op_0	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	tnr_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	tnr_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	tnr_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	tnr_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	tnr_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	tnr_op_3	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	tnr_op_4	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	tnr_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	tnr_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	tnr_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
+B0[47]	buffer	wire_mult/mult/O_0	sp12_h_l_7
+B0[51]	buffer	wire_mult/mult/O_0	sp12_v_b_0
+B0[52]	buffer	wire_mult/mult/O_0	sp12_v_t_15
+B0[46]	buffer	wire_mult/mult/O_0	sp4_h_l_5
+B1[46]	buffer	wire_mult/mult/O_0	sp4_h_r_0
+B1[47]	buffer	wire_mult/mult/O_0	sp4_h_r_32
+B1[52]	buffer	wire_mult/mult/O_0	sp4_r_v_b_1
+B0[53]	buffer	wire_mult/mult/O_0	sp4_r_v_b_17
+B1[53]	buffer	wire_mult/mult/O_0	sp4_r_v_b_33
+B0[48]	buffer	wire_mult/mult/O_0	sp4_v_b_0
+B1[48]	buffer	wire_mult/mult/O_0	sp4_v_b_16
+B1[51]	buffer	wire_mult/mult/O_0	sp4_v_t_21
+B2[47]	buffer	wire_mult/mult/O_1	sp12_h_l_9
+B2[51]	buffer	wire_mult/mult/O_1	sp12_v_b_2
+B2[52]	buffer	wire_mult/mult/O_1	sp12_v_t_17
+B3[47]	buffer	wire_mult/mult/O_1	sp4_h_l_23
+B2[46]	buffer	wire_mult/mult/O_1	sp4_h_l_7
+B3[46]	buffer	wire_mult/mult/O_1	sp4_h_r_2
+B2[53]	buffer	wire_mult/mult/O_1	sp4_r_v_b_19
+B3[52]	buffer	wire_mult/mult/O_1	sp4_r_v_b_3
+B3[53]	buffer	wire_mult/mult/O_1	sp4_r_v_b_35
+B3[48]	buffer	wire_mult/mult/O_1	sp4_v_b_18
+B2[48]	buffer	wire_mult/mult/O_1	sp4_v_b_2
+B3[51]	buffer	wire_mult/mult/O_1	sp4_v_t_23
+B4[47]	buffer	wire_mult/mult/O_2	sp12_h_r_12
+B4[52]	buffer	wire_mult/mult/O_2	sp12_v_b_20
+B4[51]	buffer	wire_mult/mult/O_2	sp12_v_b_4
+B4[46]	buffer	wire_mult/mult/O_2	sp4_h_r_20
+B5[47]	buffer	wire_mult/mult/O_2	sp4_h_r_36
+B5[46]	buffer	wire_mult/mult/O_2	sp4_h_r_4
+B4[53]	buffer	wire_mult/mult/O_2	sp4_r_v_b_21
+B5[53]	buffer	wire_mult/mult/O_2	sp4_r_v_b_37
+B5[52]	buffer	wire_mult/mult/O_2	sp4_r_v_b_5
+B5[48]	buffer	wire_mult/mult/O_2	sp4_v_b_20
+B5[51]	buffer	wire_mult/mult/O_2	sp4_v_b_36
+B4[48]	buffer	wire_mult/mult/O_2	sp4_v_b_4
+B6[47]	buffer	wire_mult/mult/O_3	sp12_h_r_14
+B6[51]	buffer	wire_mult/mult/O_3	sp12_v_b_6
+B6[52]	buffer	wire_mult/mult/O_3	sp12_v_t_21
+B6[46]	buffer	wire_mult/mult/O_3	sp4_h_l_11
+B7[47]	buffer	wire_mult/mult/O_3	sp4_h_r_38
+B7[46]	buffer	wire_mult/mult/O_3	sp4_h_r_6
+B6[53]	buffer	wire_mult/mult/O_3	sp4_r_v_b_23
+B7[53]	buffer	wire_mult/mult/O_3	sp4_r_v_b_39
+B7[52]	buffer	wire_mult/mult/O_3	sp4_r_v_b_7
+B7[51]	buffer	wire_mult/mult/O_3	sp4_v_b_38
+B6[48]	buffer	wire_mult/mult/O_3	sp4_v_b_6
+B7[48]	buffer	wire_mult/mult/O_3	sp4_v_t_11
+B8[48]	buffer	wire_mult/mult/O_4	sp12_h_l_15
+B8[47]	buffer	wire_mult/mult/O_4	sp12_h_r_0
+B8[52]	buffer	wire_mult/mult/O_4	sp12_v_b_8
+B8[46]	buffer	wire_mult/mult/O_4	sp4_h_l_13
+B9[47]	buffer	wire_mult/mult/O_4	sp4_h_l_29
+B9[46]	buffer	wire_mult/mult/O_4	sp4_h_r_8
+B8[53]	buffer	wire_mult/mult/O_4	sp4_r_v_b_25
+B9[53]	buffer	wire_mult/mult/O_4	sp4_r_v_b_41
+B9[52]	buffer	wire_mult/mult/O_4	sp4_r_v_b_9
+B9[51]	buffer	wire_mult/mult/O_4	sp4_v_b_24
+B9[48]	buffer	wire_mult/mult/O_4	sp4_v_b_8
+B8[51]	buffer	wire_mult/mult/O_4	sp4_v_t_29
+B10[47]	buffer	wire_mult/mult/O_5	sp12_h_l_1
+B10[48]	buffer	wire_mult/mult/O_5	sp12_h_l_17
+B10[52]	buffer	wire_mult/mult/O_5	sp12_v_b_10
+B11[47]	buffer	wire_mult/mult/O_5	sp4_h_l_31
+B11[46]	buffer	wire_mult/mult/O_5	sp4_h_r_10
+B10[46]	buffer	wire_mult/mult/O_5	sp4_h_r_26
+B11[52]	buffer	wire_mult/mult/O_5	sp4_r_v_b_11
+B10[53]	buffer	wire_mult/mult/O_5	sp4_r_v_b_27
+B11[53]	buffer	wire_mult/mult/O_5	sp4_r_v_b_43
+B11[48]	buffer	wire_mult/mult/O_5	sp4_v_b_10
+B11[51]	buffer	wire_mult/mult/O_5	sp4_v_t_15
+B10[51]	buffer	wire_mult/mult/O_5	sp4_v_t_31
+B12[48]	buffer	wire_mult/mult/O_6	sp12_h_l_19
+B12[47]	buffer	wire_mult/mult/O_6	sp12_h_l_3
+B12[52]	buffer	wire_mult/mult/O_6	sp12_v_t_11
+B12[46]	buffer	wire_mult/mult/O_6	sp4_h_l_17
+B13[47]	buffer	wire_mult/mult/O_6	sp4_h_l_33
+B13[46]	buffer	wire_mult/mult/O_6	sp4_h_r_12
+B13[52]	buffer	wire_mult/mult/O_6	sp4_r_v_b_13
+B12[53]	buffer	wire_mult/mult/O_6	sp4_r_v_b_29
+B13[53]	buffer	wire_mult/mult/O_6	sp4_r_v_b_45
+B13[51]	buffer	wire_mult/mult/O_6	sp4_v_b_28
+B12[51]	buffer	wire_mult/mult/O_6	sp4_v_b_44
+B13[48]	buffer	wire_mult/mult/O_6	sp4_v_t_1
+B14[47]	buffer	wire_mult/mult/O_7	sp12_h_l_5
+B14[48]	buffer	wire_mult/mult/O_7	sp12_h_r_22
+B14[52]	buffer	wire_mult/mult/O_7	sp12_v_t_13
+B15[46]	buffer	wire_mult/mult/O_7	sp4_h_l_3
+B15[47]	buffer	wire_mult/mult/O_7	sp4_h_l_35
+B14[46]	buffer	wire_mult/mult/O_7	sp4_h_r_30
+B15[52]	buffer	wire_mult/mult/O_7	sp4_r_v_b_15
+B14[53]	buffer	wire_mult/mult/O_7	sp4_r_v_b_31
+B15[53]	buffer	wire_mult/mult/O_7	sp4_r_v_b_47
+B15[48]	buffer	wire_mult/mult/O_7	sp4_v_b_14
+B15[51]	buffer	wire_mult/mult/O_7	sp4_v_b_30
+B14[51]	buffer	wire_mult/mult/O_7	sp4_v_b_46
+!B12[3],B13[3]	routing	sp12_h_l_22	sp12_h_r_1
+!B8[3],B9[3]	routing	sp12_h_l_22	sp12_v_b_1
+!B14[3],B15[3]	routing	sp12_h_l_22	sp12_v_t_22
+!B4[3],B5[3]	routing	sp12_h_l_23	sp12_h_r_0
+!B0[3],B1[3]	routing	sp12_h_l_23	sp12_v_b_0
+!B6[3],B7[3]	routing	sp12_h_l_23	sp12_v_t_23
+B2[3],B3[3]	routing	sp12_h_r_0	sp12_h_l_23
+B0[3],B1[3]	routing	sp12_h_r_0	sp12_v_b_0
+B6[3],B7[3]	routing	sp12_h_r_0	sp12_v_t_23
+B8[3],B9[3]	routing	sp12_h_r_1	sp12_v_b_1
+B14[3],B15[3]	routing	sp12_h_r_1	sp12_v_t_22
+!B2[3],B3[3]	routing	sp12_v_b_0	sp12_h_l_23
+B4[3],B5[3]	routing	sp12_v_b_0	sp12_h_r_0
+B6[3],!B7[3]	routing	sp12_v_b_0	sp12_v_t_23
+B11[3]	routing	sp12_v_b_1	sp12_h_l_22
+B12[3],B13[3]	routing	sp12_v_b_1	sp12_h_r_1
+B14[3],!B15[3]	routing	sp12_v_b_1	sp12_v_t_22
+B10[3]	routing	sp12_v_t_22	sp12_h_l_22
+B12[3],!B13[3]	routing	sp12_v_t_22	sp12_h_r_1
+B8[3],!B9[3]	routing	sp12_v_t_22	sp12_v_b_1
+B2[3],!B3[3]	routing	sp12_v_t_23	sp12_h_l_23
+B4[3],!B5[3]	routing	sp12_v_t_23	sp12_h_r_0
+B0[3],!B1[3]	routing	sp12_v_t_23	sp12_v_b_0
+!B4[8],B4[9],B4[10]	routing	sp4_h_l_36	sp4_h_r_4
+B1[8],B1[9],!B1[10]	routing	sp4_h_l_36	sp4_v_b_1
+B9[8],B9[9],B9[10]	routing	sp4_h_l_36	sp4_v_b_7
+B3[8],!B3[9],!B3[10]	routing	sp4_h_l_36	sp4_v_t_36
+!B10[4],B10[6],!B11[5]	routing	sp4_h_l_36	sp4_v_t_43
+B4[5],B5[4],!B5[6]	routing	sp4_h_l_37	sp4_h_r_3
+!B8[12],B9[11],B9[13]	routing	sp4_h_l_37	sp4_h_r_8
+B0[4],!B0[6],B1[5]	routing	sp4_h_l_37	sp4_v_b_0
+B8[4],B8[6],B9[5]	routing	sp4_h_l_37	sp4_v_b_6
+!B2[4],!B2[6],B3[5]	routing	sp4_h_l_37	sp4_v_t_37
+B6[11],!B6[13],!B7[12]	routing	sp4_h_l_37	sp4_v_t_40
+!B4[5],!B5[4],B5[6]	routing	sp4_h_l_38	sp4_h_r_3
+B8[5],B9[4],!B9[6]	routing	sp4_h_l_38	sp4_h_r_6
+B4[4],!B4[6],B5[5]	routing	sp4_h_l_38	sp4_v_b_3
+B12[4],B12[6],B13[5]	routing	sp4_h_l_38	sp4_v_b_9
+!B6[4],!B6[6],B7[5]	routing	sp4_h_l_38	sp4_v_t_38
+B10[11],!B10[13],!B11[12]	routing	sp4_h_l_38	sp4_v_t_45
+B12[8],!B12[9],B12[10]	routing	sp4_h_l_39	sp4_h_r_10
+!B0[12],B1[11],!B1[13]	routing	sp4_h_l_39	sp4_h_r_2
+B4[12],!B5[11],B5[13]	routing	sp4_h_l_39	sp4_h_r_5
+!B0[11],B0[13],B1[12]	routing	sp4_h_l_39	sp4_v_b_2
+B8[11],B8[13],B9[12]	routing	sp4_h_l_39	sp4_v_b_8
+!B2[11],!B2[13],B3[12]	routing	sp4_h_l_39	sp4_v_t_39
+!B11[8],!B11[9],B11[10]	routing	sp4_h_l_39	sp4_v_t_42
+B0[8],!B0[9],B0[10]	routing	sp4_h_l_40	sp4_h_r_1
+!B4[12],B5[11],!B5[13]	routing	sp4_h_l_40	sp4_h_r_5
+B12[11],B12[13],B13[12]	routing	sp4_h_l_40	sp4_v_b_11
+!B4[11],B4[13],B5[12]	routing	sp4_h_l_40	sp4_v_b_5
+!B6[11],!B6[13],B7[12]	routing	sp4_h_l_40	sp4_v_t_40
+!B15[8],!B15[9],B15[10]	routing	sp4_h_l_40	sp4_v_t_47
+!B0[5],B1[4],B1[6]	routing	sp4_h_l_41	sp4_h_r_0
+B4[8],!B4[9],!B4[10]	routing	sp4_h_l_41	sp4_h_r_4
+!B8[8],B8[9],B8[10]	routing	sp4_h_l_41	sp4_h_r_7
+B13[8],B13[9],B13[10]	routing	sp4_h_l_41	sp4_v_b_10
+B5[8],B5[9],!B5[10]	routing	sp4_h_l_41	sp4_v_b_4
+B7[8],!B7[9],!B7[10]	routing	sp4_h_l_41	sp4_v_t_41
+!B14[4],B14[6],!B15[5]	routing	sp4_h_l_41	sp4_v_t_44
+!B12[8],B12[9],B12[10]	routing	sp4_h_l_42	sp4_h_r_10
+!B4[5],B5[4],B5[6]	routing	sp4_h_l_42	sp4_h_r_3
+B8[8],!B8[9],!B8[10]	routing	sp4_h_l_42	sp4_h_r_7
+B1[8],B1[9],B1[10]	routing	sp4_h_l_42	sp4_v_b_1
+B9[8],B9[9],!B9[10]	routing	sp4_h_l_42	sp4_v_b_7
+!B2[4],B2[6],!B3[5]	routing	sp4_h_l_42	sp4_v_t_37
+B11[8],!B11[9],!B11[10]	routing	sp4_h_l_42	sp4_v_t_42
+!B0[12],B1[11],B1[13]	routing	sp4_h_l_43	sp4_h_r_2
+B0[4],B0[6],B1[5]	routing	sp4_h_l_43	sp4_v_b_0
+B8[4],!B8[6],B9[5]	routing	sp4_h_l_43	sp4_v_b_6
+!B10[4],!B10[6],B11[5]	routing	sp4_h_l_43	sp4_v_t_43
+B14[11],!B14[13],!B15[12]	routing	sp4_h_l_43	sp4_v_t_46
+!B4[12],B5[11],B5[13]	routing	sp4_h_l_44	sp4_h_r_5
+!B12[5],!B13[4],B13[6]	routing	sp4_h_l_44	sp4_h_r_9
+B4[4],B4[6],B5[5]	routing	sp4_h_l_44	sp4_v_b_3
+B12[4],!B12[6],B13[5]	routing	sp4_h_l_44	sp4_v_b_9
+B2[11],!B2[13],!B3[12]	routing	sp4_h_l_44	sp4_v_t_39
+!B14[4],!B14[6],B15[5]	routing	sp4_h_l_44	sp4_v_t_44
+B12[12],!B13[11],B13[13]	routing	sp4_h_l_45	sp4_h_r_11
+B4[8],!B4[9],B4[10]	routing	sp4_h_l_45	sp4_h_r_4
+!B8[12],B9[11],!B9[13]	routing	sp4_h_l_45	sp4_h_r_8
+B0[11],B0[13],B1[12]	routing	sp4_h_l_45	sp4_v_b_2
+!B8[11],B8[13],B9[12]	routing	sp4_h_l_45	sp4_v_b_8
+!B3[8],!B3[9],B3[10]	routing	sp4_h_l_45	sp4_v_t_36
+!B10[11],!B10[13],B11[12]	routing	sp4_h_l_45	sp4_v_t_45
+!B12[12],B13[11],!B13[13]	routing	sp4_h_l_46	sp4_h_r_11
+B0[12],!B1[11],B1[13]	routing	sp4_h_l_46	sp4_h_r_2
+B8[8],!B8[9],B8[10]	routing	sp4_h_l_46	sp4_h_r_7
+!B12[11],B12[13],B13[12]	routing	sp4_h_l_46	sp4_v_b_11
+B4[11],B4[13],B5[12]	routing	sp4_h_l_46	sp4_v_b_5
+!B7[8],!B7[9],B7[10]	routing	sp4_h_l_46	sp4_v_t_41
+!B14[11],!B14[13],B15[12]	routing	sp4_h_l_46	sp4_v_t_46
+!B0[8],B0[9],B0[10]	routing	sp4_h_l_47	sp4_h_r_1
+B12[8],!B12[9],!B12[10]	routing	sp4_h_l_47	sp4_h_r_10
+!B8[5],B9[4],B9[6]	routing	sp4_h_l_47	sp4_h_r_6
+B13[8],B13[9],!B13[10]	routing	sp4_h_l_47	sp4_v_b_10
+B5[8],B5[9],B5[10]	routing	sp4_h_l_47	sp4_v_b_4
+!B6[4],B6[6],!B7[5]	routing	sp4_h_l_47	sp4_v_t_38
+B15[8],!B15[9],!B15[10]	routing	sp4_h_l_47	sp4_v_t_47
+!B2[5],!B3[4],B3[6]	routing	sp4_h_r_0	sp4_h_l_37
+B6[5],B7[4],!B7[6]	routing	sp4_h_r_0	sp4_h_l_38
+!B10[12],B11[11],B11[13]	routing	sp4_h_r_0	sp4_h_l_45
+!B0[4],!B0[6],B1[5]	routing	sp4_h_r_0	sp4_v_b_0
+B4[11],!B4[13],!B5[12]	routing	sp4_h_r_0	sp4_v_b_5
+B2[4],!B2[6],B3[5]	routing	sp4_h_r_0	sp4_v_t_37
+B10[4],B10[6],B11[5]	routing	sp4_h_r_0	sp4_v_t_43
+B1[8],!B1[9],!B1[10]	routing	sp4_h_r_1	sp4_v_b_1
+!B8[4],B8[6],!B9[5]	routing	sp4_h_r_1	sp4_v_b_6
+B3[8],B3[9],!B3[10]	routing	sp4_h_r_1	sp4_v_t_36
+B11[8],B11[9],B11[10]	routing	sp4_h_r_1	sp4_v_t_42
+!B2[8],B2[9],B2[10]	routing	sp4_h_r_10	sp4_h_l_36
+!B10[5],B11[4],B11[6]	routing	sp4_h_r_10	sp4_h_l_43
+B13[8],!B13[9],!B13[10]	routing	sp4_h_r_10	sp4_v_b_10
+!B4[4],B4[6],!B5[5]	routing	sp4_h_r_10	sp4_v_b_3
+B7[8],B7[9],B7[10]	routing	sp4_h_r_10	sp4_v_t_41
+B15[8],B15[9],!B15[10]	routing	sp4_h_r_10	sp4_v_t_47
+B10[8],!B10[9],B10[10]	routing	sp4_h_r_11	sp4_h_l_42
+!B12[11],!B12[13],B13[12]	routing	sp4_h_r_11	sp4_v_b_11
+!B5[8],!B5[9],B5[10]	routing	sp4_h_r_11	sp4_v_b_4
+B6[11],B6[13],B7[12]	routing	sp4_h_r_11	sp4_v_t_40
+!B14[11],B14[13],B15[12]	routing	sp4_h_r_11	sp4_v_t_46
+!B2[12],B3[11],!B3[13]	routing	sp4_h_r_2	sp4_h_l_39
+B6[12],!B7[11],B7[13]	routing	sp4_h_r_2	sp4_h_l_40
+B14[8],!B14[9],B14[10]	routing	sp4_h_r_2	sp4_h_l_47
+!B0[11],!B0[13],B1[12]	routing	sp4_h_r_2	sp4_v_b_2
+!B9[8],!B9[9],B9[10]	routing	sp4_h_r_2	sp4_v_b_7
+!B2[11],B2[13],B3[12]	routing	sp4_h_r_2	sp4_v_t_39
+B10[11],B10[13],B11[12]	routing	sp4_h_r_2	sp4_v_t_45
+!B6[5],!B7[4],B7[6]	routing	sp4_h_r_3	sp4_h_l_38
+!B4[4],!B4[6],B5[5]	routing	sp4_h_r_3	sp4_v_b_3
+B8[11],!B8[13],!B9[12]	routing	sp4_h_r_3	sp4_v_b_8
+B6[4],!B6[6],B7[5]	routing	sp4_h_r_3	sp4_v_t_38
+B14[4],B14[6],B15[5]	routing	sp4_h_r_3	sp4_v_t_44
+!B2[5],B3[4],B3[6]	routing	sp4_h_r_4	sp4_h_l_37
+B6[8],!B6[9],!B6[10]	routing	sp4_h_r_4	sp4_h_l_41
+!B10[8],B10[9],B10[10]	routing	sp4_h_r_4	sp4_h_l_42
+B5[8],!B5[9],!B5[10]	routing	sp4_h_r_4	sp4_v_b_4
+!B12[4],B12[6],!B13[5]	routing	sp4_h_r_4	sp4_v_b_9
+B7[8],B7[9],!B7[10]	routing	sp4_h_r_4	sp4_v_t_41
+B15[8],B15[9],B15[10]	routing	sp4_h_r_4	sp4_v_t_47
+B2[8],!B2[9],B2[10]	routing	sp4_h_r_5	sp4_h_l_36
+!B13[8],!B13[9],B13[10]	routing	sp4_h_r_5	sp4_v_b_10
+!B4[11],!B4[13],B5[12]	routing	sp4_h_r_5	sp4_v_b_5
+!B6[11],B6[13],B7[12]	routing	sp4_h_r_5	sp4_v_t_40
+B14[11],B14[13],B15[12]	routing	sp4_h_r_5	sp4_v_t_46
+!B2[12],B3[11],B3[13]	routing	sp4_h_r_6	sp4_h_l_39
+!B10[5],!B11[4],B11[6]	routing	sp4_h_r_6	sp4_h_l_43
+B14[5],B15[4],!B15[6]	routing	sp4_h_r_6	sp4_h_l_44
+B12[11],!B12[13],!B13[12]	routing	sp4_h_r_6	sp4_v_b_11
+!B8[4],!B8[6],B9[5]	routing	sp4_h_r_6	sp4_v_b_6
+B2[4],B2[6],B3[5]	routing	sp4_h_r_6	sp4_v_t_37
+B10[4],!B10[6],B11[5]	routing	sp4_h_r_6	sp4_v_t_43
+!B14[8],B14[9],B14[10]	routing	sp4_h_r_7	sp4_h_l_47
+!B0[4],B0[6],!B1[5]	routing	sp4_h_r_7	sp4_v_b_0
+B9[8],!B9[9],!B9[10]	routing	sp4_h_r_7	sp4_v_b_7
+B3[8],B3[9],B3[10]	routing	sp4_h_r_7	sp4_v_t_36
+B11[8],B11[9],!B11[10]	routing	sp4_h_r_7	sp4_v_t_42
+B6[8],!B6[9],B6[10]	routing	sp4_h_r_8	sp4_h_l_41
+!B10[12],B11[11],!B11[13]	routing	sp4_h_r_8	sp4_h_l_45
+B14[12],!B15[11],B15[13]	routing	sp4_h_r_8	sp4_h_l_46
+!B1[8],!B1[9],B1[10]	routing	sp4_h_r_8	sp4_v_b_1
+!B8[11],!B8[13],B9[12]	routing	sp4_h_r_8	sp4_v_b_8
+B2[11],B2[13],B3[12]	routing	sp4_h_r_8	sp4_v_t_39
+!B10[11],B10[13],B11[12]	routing	sp4_h_r_8	sp4_v_t_45
+B2[5],B3[4],!B3[6]	routing	sp4_h_r_9	sp4_h_l_37
+!B6[12],B7[11],B7[13]	routing	sp4_h_r_9	sp4_h_l_40
+B0[11],!B0[13],!B1[12]	routing	sp4_h_r_9	sp4_v_b_2
+!B12[4],!B12[6],B13[5]	routing	sp4_h_r_9	sp4_v_b_9
+B6[4],B6[6],B7[5]	routing	sp4_h_r_9	sp4_v_t_38
+B14[4],!B14[6],B15[5]	routing	sp4_h_r_9	sp4_v_t_44
+B2[5],!B3[4],!B3[6]	routing	sp4_v_b_0	sp4_h_l_37
+!B6[12],!B7[11],B7[13]	routing	sp4_v_b_0	sp4_h_l_40
+B0[5],!B1[4],B1[6]	routing	sp4_v_b_0	sp4_h_r_0
+B8[5],B9[4],B9[6]	routing	sp4_v_b_0	sp4_h_r_6
+B2[4],!B2[6],!B3[5]	routing	sp4_v_b_0	sp4_v_t_37
+!B6[4],B6[6],B7[5]	routing	sp4_v_b_0	sp4_v_t_38
+B10[11],B10[13],!B11[12]	routing	sp4_v_b_0	sp4_v_t_45
+!B2[8],B2[9],!B2[10]	routing	sp4_v_b_1	sp4_h_l_36
+!B10[5],B11[4],!B11[6]	routing	sp4_v_b_1	sp4_h_l_43
+B0[8],B0[9],!B0[10]	routing	sp4_v_b_1	sp4_h_r_1
+B8[8],B8[9],B8[10]	routing	sp4_v_b_1	sp4_h_r_7
+!B3[8],B3[9],!B3[10]	routing	sp4_v_b_1	sp4_v_t_36
+B7[8],!B7[9],B7[10]	routing	sp4_v_b_1	sp4_v_t_41
+B14[4],B14[6],!B15[5]	routing	sp4_v_b_1	sp4_v_t_44
+!B6[5],B7[4],!B7[6]	routing	sp4_v_b_10	sp4_h_l_38
+!B14[8],B14[9],!B14[10]	routing	sp4_v_b_10	sp4_h_l_47
+B12[8],B12[9],!B12[10]	routing	sp4_v_b_10	sp4_h_r_10
+B4[8],B4[9],B4[10]	routing	sp4_v_b_10	sp4_h_r_4
+B3[8],!B3[9],B3[10]	routing	sp4_v_b_10	sp4_v_t_36
+B10[4],B10[6],!B11[5]	routing	sp4_v_b_10	sp4_v_t_43
+!B15[8],B15[9],!B15[10]	routing	sp4_v_b_10	sp4_v_t_47
+!B6[8],!B6[9],B6[10]	routing	sp4_v_b_11	sp4_h_l_41
+B14[12],!B15[11],!B15[13]	routing	sp4_v_b_11	sp4_h_l_46
+B12[12],B13[11],!B13[13]	routing	sp4_v_b_11	sp4_h_r_11
+B4[12],B5[11],B5[13]	routing	sp4_v_b_11	sp4_h_r_5
+B2[11],!B2[13],B3[12]	routing	sp4_v_b_11	sp4_v_t_39
+!B11[8],B11[9],B11[10]	routing	sp4_v_b_11	sp4_v_t_42
+!B14[11],B14[13],!B15[12]	routing	sp4_v_b_11	sp4_v_t_46
+B2[12],!B3[11],!B3[13]	routing	sp4_v_b_2	sp4_h_l_39
+!B10[8],!B10[9],B10[10]	routing	sp4_v_b_2	sp4_h_l_42
+B0[12],B1[11],!B1[13]	routing	sp4_v_b_2	sp4_h_r_2
+B8[12],B9[11],B9[13]	routing	sp4_v_b_2	sp4_h_r_8
+!B2[11],B2[13],!B3[12]	routing	sp4_v_b_2	sp4_v_t_39
+B6[11],!B6[13],B7[12]	routing	sp4_v_b_2	sp4_v_t_40
+!B15[8],B15[9],B15[10]	routing	sp4_v_b_2	sp4_v_t_47
+B6[5],!B7[4],!B7[6]	routing	sp4_v_b_3	sp4_h_l_38
+!B10[12],!B11[11],B11[13]	routing	sp4_v_b_3	sp4_h_l_45
+B4[5],!B5[4],B5[6]	routing	sp4_v_b_3	sp4_h_r_3
+B12[5],B13[4],B13[6]	routing	sp4_v_b_3	sp4_h_r_9
+B6[4],!B6[6],!B7[5]	routing	sp4_v_b_3	sp4_v_t_38
+!B10[4],B10[6],B11[5]	routing	sp4_v_b_3	sp4_v_t_43
+B14[11],B14[13],!B15[12]	routing	sp4_v_b_3	sp4_v_t_46
+!B6[8],B6[9],!B6[10]	routing	sp4_v_b_4	sp4_h_l_41
+!B14[5],B15[4],!B15[6]	routing	sp4_v_b_4	sp4_h_l_44
+B12[8],B12[9],B12[10]	routing	sp4_v_b_4	sp4_h_r_10
+B4[8],B4[9],!B4[10]	routing	sp4_v_b_4	sp4_h_r_4
+B2[4],B2[6],!B3[5]	routing	sp4_v_b_4	sp4_v_t_37
+!B7[8],B7[9],!B7[10]	routing	sp4_v_b_4	sp4_v_t_41
+B11[8],!B11[9],B11[10]	routing	sp4_v_b_4	sp4_v_t_42
+B6[12],!B7[11],!B7[13]	routing	sp4_v_b_5	sp4_h_l_40
+!B14[8],!B14[9],B14[10]	routing	sp4_v_b_5	sp4_h_l_47
+B12[12],B13[11],B13[13]	routing	sp4_v_b_5	sp4_h_r_11
+B4[12],B5[11],!B5[13]	routing	sp4_v_b_5	sp4_h_r_5
+!B3[8],B3[9],B3[10]	routing	sp4_v_b_5	sp4_v_t_36
+!B6[11],B6[13],!B7[12]	routing	sp4_v_b_5	sp4_v_t_40
+B10[11],!B10[13],B11[12]	routing	sp4_v_b_5	sp4_v_t_45
+B10[5],!B11[4],!B11[6]	routing	sp4_v_b_6	sp4_h_l_43
+!B14[12],!B15[11],B15[13]	routing	sp4_v_b_6	sp4_h_l_46
+B0[5],B1[4],B1[6]	routing	sp4_v_b_6	sp4_h_r_0
+B8[5],!B9[4],B9[6]	routing	sp4_v_b_6	sp4_h_r_6
+B2[11],B2[13],!B3[12]	routing	sp4_v_b_6	sp4_v_t_39
+B10[4],!B10[6],!B11[5]	routing	sp4_v_b_6	sp4_v_t_43
+!B14[4],B14[6],B15[5]	routing	sp4_v_b_6	sp4_v_t_44
+!B2[5],B3[4],!B3[6]	routing	sp4_v_b_7	sp4_h_l_37
+!B10[8],B10[9],!B10[10]	routing	sp4_v_b_7	sp4_h_l_42
+B0[8],B0[9],B0[10]	routing	sp4_v_b_7	sp4_h_r_1
+B8[8],B8[9],!B8[10]	routing	sp4_v_b_7	sp4_h_r_7
+B6[4],B6[6],!B7[5]	routing	sp4_v_b_7	sp4_v_t_38
+!B11[8],B11[9],!B11[10]	routing	sp4_v_b_7	sp4_v_t_42
+B15[8],!B15[9],B15[10]	routing	sp4_v_b_7	sp4_v_t_47
+!B2[8],!B2[9],B2[10]	routing	sp4_v_b_8	sp4_h_l_36
+B10[12],!B11[11],!B11[13]	routing	sp4_v_b_8	sp4_h_l_45
+B0[12],B1[11],B1[13]	routing	sp4_v_b_8	sp4_h_r_2
+B8[12],B9[11],!B9[13]	routing	sp4_v_b_8	sp4_h_r_8
+!B7[8],B7[9],B7[10]	routing	sp4_v_b_8	sp4_v_t_41
+!B10[11],B10[13],!B11[12]	routing	sp4_v_b_8	sp4_v_t_45
+B14[11],!B14[13],B15[12]	routing	sp4_v_b_8	sp4_v_t_46
+!B2[12],!B3[11],B3[13]	routing	sp4_v_b_9	sp4_h_l_39
+B14[5],!B15[4],!B15[6]	routing	sp4_v_b_9	sp4_h_l_44
+B4[5],B5[4],B5[6]	routing	sp4_v_b_9	sp4_h_r_3
+B12[5],!B13[4],B13[6]	routing	sp4_v_b_9	sp4_h_r_9
+!B2[4],B2[6],B3[5]	routing	sp4_v_b_9	sp4_v_t_37
+B6[11],B6[13],!B7[12]	routing	sp4_v_b_9	sp4_v_t_40
+B14[4],!B14[6],!B15[5]	routing	sp4_v_b_9	sp4_v_t_44
+B2[8],B2[9],!B2[10]	routing	sp4_v_t_36	sp4_h_l_36
+B10[8],B10[9],B10[10]	routing	sp4_v_t_36	sp4_h_l_42
+!B0[8],B0[9],!B0[10]	routing	sp4_v_t_36	sp4_h_r_1
+!B8[5],B9[4],!B9[6]	routing	sp4_v_t_36	sp4_h_r_6
+!B1[8],B1[9],!B1[10]	routing	sp4_v_t_36	sp4_v_b_1
+B5[8],!B5[9],B5[10]	routing	sp4_v_t_36	sp4_v_b_4
+B12[4],B12[6],!B13[5]	routing	sp4_v_t_36	sp4_v_b_9
+B2[5],!B3[4],B3[6]	routing	sp4_v_t_37	sp4_h_l_37
+B10[5],B11[4],B11[6]	routing	sp4_v_t_37	sp4_h_l_43
+B0[5],!B1[4],!B1[6]	routing	sp4_v_t_37	sp4_h_r_0
+!B4[12],!B5[11],B5[13]	routing	sp4_v_t_37	sp4_h_r_5
+B0[4],!B0[6],!B1[5]	routing	sp4_v_t_37	sp4_v_b_0
+!B4[4],B4[6],B5[5]	routing	sp4_v_t_37	sp4_v_b_3
+B8[11],B8[13],!B9[12]	routing	sp4_v_t_37	sp4_v_b_8
+B6[5],!B7[4],B7[6]	routing	sp4_v_t_38	sp4_h_l_38
+B14[5],B15[4],B15[6]	routing	sp4_v_t_38	sp4_h_l_44
+B4[5],!B5[4],!B5[6]	routing	sp4_v_t_38	sp4_h_r_3
+!B8[12],!B9[11],B9[13]	routing	sp4_v_t_38	sp4_h_r_8
+B12[11],B12[13],!B13[12]	routing	sp4_v_t_38	sp4_v_b_11
+B4[4],!B4[6],!B5[5]	routing	sp4_v_t_38	sp4_v_b_3
+!B8[4],B8[6],B9[5]	routing	sp4_v_t_38	sp4_v_b_6
+B2[12],B3[11],!B3[13]	routing	sp4_v_t_39	sp4_h_l_39
+B10[12],B11[11],B11[13]	routing	sp4_v_t_39	sp4_h_l_45
+B0[12],!B1[11],!B1[13]	routing	sp4_v_t_39	sp4_h_r_2
+!B8[8],!B8[9],B8[10]	routing	sp4_v_t_39	sp4_h_r_7
+!B13[8],B13[9],B13[10]	routing	sp4_v_t_39	sp4_v_b_10
+!B0[11],B0[13],!B1[12]	routing	sp4_v_t_39	sp4_v_b_2
+B4[11],!B4[13],B5[12]	routing	sp4_v_t_39	sp4_v_b_5
+B6[12],B7[11],!B7[13]	routing	sp4_v_t_40	sp4_h_l_40
+B14[12],B15[11],B15[13]	routing	sp4_v_t_40	sp4_h_l_46
+!B12[8],!B12[9],B12[10]	routing	sp4_v_t_40	sp4_h_r_10
+B4[12],!B5[11],!B5[13]	routing	sp4_v_t_40	sp4_h_r_5
+!B1[8],B1[9],B1[10]	routing	sp4_v_t_40	sp4_v_b_1
+!B4[11],B4[13],!B5[12]	routing	sp4_v_t_40	sp4_v_b_5
+B8[11],!B8[13],B9[12]	routing	sp4_v_t_40	sp4_v_b_8
+B6[8],B6[9],!B6[10]	routing	sp4_v_t_41	sp4_h_l_41
+B14[8],B14[9],B14[10]	routing	sp4_v_t_41	sp4_h_l_47
+!B4[8],B4[9],!B4[10]	routing	sp4_v_t_41	sp4_h_r_4
+!B12[5],B13[4],!B13[6]	routing	sp4_v_t_41	sp4_h_r_9
+B0[4],B0[6],!B1[5]	routing	sp4_v_t_41	sp4_v_b_0
+!B5[8],B5[9],!B5[10]	routing	sp4_v_t_41	sp4_v_b_4
+B9[8],!B9[9],B9[10]	routing	sp4_v_t_41	sp4_v_b_7
+B2[8],B2[9],B2[10]	routing	sp4_v_t_42	sp4_h_l_36
+B10[8],B10[9],!B10[10]	routing	sp4_v_t_42	sp4_h_l_42
+!B0[5],B1[4],!B1[6]	routing	sp4_v_t_42	sp4_h_r_0
+!B8[8],B8[9],!B8[10]	routing	sp4_v_t_42	sp4_h_r_7
+B13[8],!B13[9],B13[10]	routing	sp4_v_t_42	sp4_v_b_10
+B4[4],B4[6],!B5[5]	routing	sp4_v_t_42	sp4_v_b_3
+!B9[8],B9[9],!B9[10]	routing	sp4_v_t_42	sp4_v_b_7
+B2[5],B3[4],B3[6]	routing	sp4_v_t_43	sp4_h_l_37
+B10[5],!B11[4],B11[6]	routing	sp4_v_t_43	sp4_h_l_43
+!B12[12],!B13[11],B13[13]	routing	sp4_v_t_43	sp4_h_r_11
+B8[5],!B9[4],!B9[6]	routing	sp4_v_t_43	sp4_h_r_6
+B0[11],B0[13],!B1[12]	routing	sp4_v_t_43	sp4_v_b_2
+B8[4],!B8[6],!B9[5]	routing	sp4_v_t_43	sp4_v_b_6
+!B12[4],B12[6],B13[5]	routing	sp4_v_t_43	sp4_v_b_9
+B6[5],B7[4],B7[6]	routing	sp4_v_t_44	sp4_h_l_38
+B14[5],!B15[4],B15[6]	routing	sp4_v_t_44	sp4_h_l_44
+!B0[12],!B1[11],B1[13]	routing	sp4_v_t_44	sp4_h_r_2
+B12[5],!B13[4],!B13[6]	routing	sp4_v_t_44	sp4_h_r_9
+!B0[4],B0[6],B1[5]	routing	sp4_v_t_44	sp4_v_b_0
+B4[11],B4[13],!B5[12]	routing	sp4_v_t_44	sp4_v_b_5
+B12[4],!B12[6],!B13[5]	routing	sp4_v_t_44	sp4_v_b_9
+B2[12],B3[11],B3[13]	routing	sp4_v_t_45	sp4_h_l_39
+B10[12],B11[11],!B11[13]	routing	sp4_v_t_45	sp4_h_l_45
+!B0[8],!B0[9],B0[10]	routing	sp4_v_t_45	sp4_h_r_1
+B8[12],!B9[11],!B9[13]	routing	sp4_v_t_45	sp4_h_r_8
+B12[11],!B12[13],B13[12]	routing	sp4_v_t_45	sp4_v_b_11
+!B5[8],B5[9],B5[10]	routing	sp4_v_t_45	sp4_v_b_4
+!B8[11],B8[13],!B9[12]	routing	sp4_v_t_45	sp4_v_b_8
+B6[12],B7[11],B7[13]	routing	sp4_v_t_46	sp4_h_l_40
+B14[12],B15[11],!B15[13]	routing	sp4_v_t_46	sp4_h_l_46
+B12[12],!B13[11],!B13[13]	routing	sp4_v_t_46	sp4_h_r_11
+!B4[8],!B4[9],B4[10]	routing	sp4_v_t_46	sp4_h_r_4
+!B12[11],B12[13],!B13[12]	routing	sp4_v_t_46	sp4_v_b_11
+B0[11],!B0[13],B1[12]	routing	sp4_v_t_46	sp4_v_b_2
+!B9[8],B9[9],B9[10]	routing	sp4_v_t_46	sp4_v_b_7
+B6[8],B6[9],B6[10]	routing	sp4_v_t_47	sp4_h_l_41
+B14[8],B14[9],!B14[10]	routing	sp4_v_t_47	sp4_h_l_47
+!B12[8],B12[9],!B12[10]	routing	sp4_v_t_47	sp4_h_r_10
+!B4[5],B5[4],!B5[6]	routing	sp4_v_t_47	sp4_h_r_3
+B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
+!B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
+B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
+"""
+database_dsp1_5k_txt = """
+B0[50]	Cascade	MULT1_LC00_inmux02_5
+B2[50]	Cascade	MULT1_LC01_inmux02_5
+B4[50]	Cascade	MULT1_LC02_inmux02_5
+B6[50]	Cascade	MULT1_LC03_inmux02_5
+B8[50]	Cascade	MULT1_LC04_inmux02_5
+B10[50]	Cascade	MULT1_LC05_inmux02_5
+B12[50]	Cascade	MULT1_LC06_inmux02_5
+B14[50]	Cascade	MULT1_LC07_inmux02_5
+B1[7]	IpConfig	CBIT_0
+B0[7]	IpConfig	CBIT_1
+B3[7]	IpConfig	CBIT_2
+B2[7]	IpConfig	CBIT_3
+B5[7]	IpConfig	CBIT_4
+B7[7]	IpConfig	CBIT_6
+B6[7]	IpConfig	CBIT_7
+B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43]	LC_0
+B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43]	LC_1
+B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43]	LC_2
+B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43]	LC_3
+B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43]	LC_4
+B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43]	LC_5
+B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43]	LC_6
+B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43]	LC_7
+B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	bnl_op_0	lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	bnl_op_0	lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	bnl_op_1	lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	bnl_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	bnl_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	bnl_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	bnl_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	bnl_op_3	lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	bnl_op_4	lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	bnl_op_4	lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	bnl_op_5	lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	bnl_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	bnl_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	bnl_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	bnl_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	bnl_op_7	lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	bnr_op_0	lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	bnr_op_0	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	bnr_op_1	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	bnr_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	bnr_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	bnr_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	bnr_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	bnr_op_3	lc_trk_g1_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	bnr_op_4	lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	bnr_op_4	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	bnr_op_5	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	bnr_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	bnr_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	bnr_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	bnr_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	bnr_op_7	lc_trk_g1_7
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17]	buffer	glb2local_0	lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_0	glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_0	glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_0	glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_0	glb2local_3
+!B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_0	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
+!B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_1	glb2local_1
+!B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_1	glb2local_2
+!B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_1	glb2local_3
+B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_2	glb2local_2
+B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_2	glb2local_3
+!B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_2	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_3	glb2local_0
+B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_3	glb2local_1
+B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
+B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_3	glb2local_3
+!B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_4	glb2local_0
+!B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_4	glb2local_1
+!B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
+!B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_4	glb2local_3
+B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
+!B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
+!B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_5	glb2local_2
+!B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
+B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_6	glb2local_0
+B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_6	glb2local_1
+B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
+B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_6	glb2local_3
+B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_6	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_7	glb2local_0
+B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_7	glb2local_1
+B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_7	glb2local_2
+B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_7	glb2local_3
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g0_0	wire_mult/lc_1/in_1
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g0_0	wire_mult/lc_3/in_1
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g0_0	wire_mult/lc_5/in_1
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g0_0	wire_mult/lc_7/in_1
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g0_1	wire_mult/lc_0/in_1
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g0_1	wire_mult/lc_2/in_1
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_mult/lc_4/in_1
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g0_1	wire_mult/lc_6/in_1
+!B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_2	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_3
+!B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_3
+!B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_3
+!B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_4	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_3
+!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],!B7[31]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],!B11[31]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_3
+!B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g0_4	wire_mult/lc_7/s_r
+!B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_3
+!B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_3
+!B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_6	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_3
+!B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_3
+!B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_3
+!B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_3
+B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_1	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_5	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_3
+!B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g1_5	wire_mult/lc_7/s_r
+B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_7	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_3
+!B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_3
+!B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_2	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_4	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_3
+B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g2_4	wire_mult/lc_7/s_r
+!B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_6	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_3
+B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_1	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_3	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_5	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_3
+B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g3_5	wire_mult/lc_7/s_r
+B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_7	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_3
+B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	lft_op_0	lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18]	buffer	lft_op_1	lc_trk_g1_1
+B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	lft_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21]	buffer	lft_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21]	buffer	lft_op_3	lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	lft_op_4	lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17]	buffer	lft_op_4	lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18]	buffer	lft_op_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18]	buffer	lft_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25]	buffer	lft_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25]	buffer	lft_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	lft_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21]	buffer	lft_op_7	lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	rgt_op_0	lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	rgt_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18]	buffer	rgt_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	rgt_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	rgt_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	rgt_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	rgt_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	rgt_op_3	lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	rgt_op_4	lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	rgt_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18]	buffer	rgt_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18]	buffer	rgt_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	rgt_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	rgt_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	rgt_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
+B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_l_0	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_l_0	lc_trk_g1_3
+!B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_l_10	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_l_10	lc_trk_g1_5
+!B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_l_11	lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_l_11	lc_trk_g1_4
+B4[2]	buffer	sp12_h_l_11	sp4_h_l_7
+!B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_l_12	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_l_12	lc_trk_g1_7
+!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_l_13	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_l_13	lc_trk_g1_6
+B6[2]	buffer	sp12_h_l_13	sp4_h_r_19
+!B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_l_15	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_l_15	lc_trk_g1_0
+B8[2]	buffer	sp12_h_l_15	sp4_h_l_9
+!B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_l_16	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_l_16	lc_trk_g1_3
+!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_l_18	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_l_18	lc_trk_g1_5
+!B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_l_19	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_l_19	lc_trk_g1_4
+B12[2]	buffer	sp12_h_l_19	sp4_h_l_11
+!B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_l_20	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_l_20	lc_trk_g1_7
+B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_l_3	lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17]	buffer	sp12_h_l_3	lc_trk_g1_4
+B15[19]	buffer	sp12_h_l_3	sp4_h_l_3
+B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_l_4	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_l_4	lc_trk_g1_7
+B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_l_5	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_l_5	lc_trk_g1_6
+B14[19]	buffer	sp12_h_l_5	sp4_h_l_2
+!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_l_9	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_l_9	lc_trk_g1_2
+B3[1]	buffer	sp12_h_l_9	sp4_h_l_4
+B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	sp12_h_r_0	lc_trk_g1_0
+B13[19]	buffer	sp12_h_r_0	sp4_h_r_12
+B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	sp12_h_r_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
+!B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp12_h_r_11	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp12_h_r_11	lc_trk_g1_3
+!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_r_17	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_r_17	lc_trk_g1_1
+!B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_r_18	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_r_18	lc_trk_g1_2
+B10[2]	buffer	sp12_h_r_18	sp4_h_r_21
+B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_r_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_r_2	lc_trk_g1_2
+B12[19]	buffer	sp12_h_r_2	sp4_h_l_0
+!B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_r_22	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_r_22	lc_trk_g1_6
+B14[2]	buffer	sp12_h_r_22	sp4_h_l_10
+B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_r_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_r_5	lc_trk_g1_5
+!B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_8	lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_8	lc_trk_g1_0
+B0[2]	buffer	sp12_h_r_8	sp4_h_r_16
+!B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_r_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_r_9	lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
+B1[19]	buffer	sp12_v_b_1	sp4_v_b_12
+!B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp12_v_b_11	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_b_11	lc_trk_g3_3
+B4[19]	buffer	sp12_v_b_11	sp4_v_b_17
+!B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_12	lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_12	lc_trk_g3_4
+!B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp12_v_b_15	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp12_v_b_15	lc_trk_g3_7
+B6[19]	buffer	sp12_v_b_15	sp4_v_b_19
+!B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp12_v_b_19	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp12_v_b_19	lc_trk_g3_3
+B8[19]	buffer	sp12_v_b_19	sp4_v_b_21
+B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	sp12_v_b_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	sp12_v_b_2	lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp12_v_b_21	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp12_v_b_21	lc_trk_g3_5
+B11[19]	buffer	sp12_v_b_21	sp4_v_t_11
+!B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp12_v_b_23	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp12_v_b_23	lc_trk_g3_7
+B10[19]	buffer	sp12_v_b_23	sp4_v_t_10
+B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	sp12_v_b_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	sp12_v_b_3	lc_trk_g3_3
+B0[19]	buffer	sp12_v_b_3	sp4_v_b_13
+B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	sp12_v_b_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	sp12_v_b_5	lc_trk_g3_5
+B3[19]	buffer	sp12_v_b_5	sp4_v_t_3
+B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	sp12_v_b_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	sp12_v_b_6	lc_trk_g3_6
+!B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_8	lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_b_8	lc_trk_g3_0
+!B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp12_v_b_9	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp12_v_b_9	lc_trk_g3_1
+B5[19]	buffer	sp12_v_b_9	sp4_v_b_16
+!B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp12_v_t_10	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp12_v_t_10	lc_trk_g3_5
+B7[19]	buffer	sp12_v_t_10	sp4_v_t_7
+!B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp12_v_t_13	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp12_v_t_13	lc_trk_g3_6
+!B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp12_v_t_14	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp12_v_t_14	lc_trk_g3_1
+B9[19]	buffer	sp12_v_t_14	sp4_v_t_9
+!B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_t_15	lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_t_15	lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp12_v_t_17	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp12_v_t_17	lc_trk_g3_2
+!B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_t_19	lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_t_19	lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_t_21	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_t_21	lc_trk_g3_6
+B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_t_3	lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_t_3	lc_trk_g3_4
+B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	sp12_v_t_4	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	sp12_v_t_4	lc_trk_g3_7
+B2[19]	buffer	sp12_v_t_4	sp4_v_t_2
+!B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_t_9	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp12_v_t_9	lc_trk_g3_2
+B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_h_l_0	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_h_l_0	lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_l_10	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_l_10	lc_trk_g1_7
+B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_l_11	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_l_11	lc_trk_g1_6
+B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_h_l_16	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_h_l_16	lc_trk_g3_5
+!B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_17	lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_17	lc_trk_g3_4
+B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_h_l_2	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_h_l_2	lc_trk_g1_7
+B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_21	lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_21	lc_trk_g3_0
+B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_l_22	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_l_22	lc_trk_g3_3
+B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_l_27	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_l_27	lc_trk_g3_6
+B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_h_l_28	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_h_l_28	lc_trk_g3_1
+B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_h_l_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_h_l_3	lc_trk_g1_6
+B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_l_31	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_l_31	lc_trk_g3_2
+B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_h_l_32	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_l_32	lc_trk_g3_5
+B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_l_34	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_l_34	lc_trk_g3_7
+B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_h_l_4	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_h_l_4	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_l_7	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_l_7	lc_trk_g1_2
+B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_l_9	lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_l_9	lc_trk_g1_4
+!B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_h_r_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_h_r_11	lc_trk_g1_3
+B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_12	lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_12	lc_trk_g1_4
+B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_16	lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_16	lc_trk_g1_0
+B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_19	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_19	lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_2	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_2	lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_r_21	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_r_21	lc_trk_g1_5
+!B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_24	lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_24	lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_r_25	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_r_25	lc_trk_g3_1
+!B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_26	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_26	lc_trk_g3_2
+!B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_27	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_27	lc_trk_g3_3
+!B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_3	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_3	lc_trk_g1_3
+!B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_30	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_30	lc_trk_g3_6
+!B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_r_31	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_r_31	lc_trk_g3_7
+B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_h_r_33	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_h_r_33	lc_trk_g3_1
+B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_h_r_34	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_h_r_34	lc_trk_g3_2
+B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_36	lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_36	lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_r_37	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_r_37	lc_trk_g3_5
+B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_r_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_r_39	lc_trk_g3_7
+!B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
+B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_40	lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_40	lc_trk_g3_0
+B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_43	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_43	lc_trk_g3_3
+B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_44	lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_44	lc_trk_g3_4
+B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_46	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_46	lc_trk_g3_6
+B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_6	lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_8	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_h_r_9	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_h_r_9	lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_0	lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_r_v_b_1	lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25]	buffer	sp4_r_v_b_10	lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21]	buffer	sp4_r_v_b_11	lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_12	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_r_v_b_13	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25]	buffer	sp4_r_v_b_14	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21]	buffer	sp4_r_v_b_15	lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_16	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_r_v_b_17	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25]	buffer	sp4_r_v_b_18	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21]	buffer	sp4_r_v_b_19	lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25]	buffer	sp4_r_v_b_2	lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_20	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_r_v_b_21	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25]	buffer	sp4_r_v_b_22	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21]	buffer	sp4_r_v_b_23	lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_24	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_24	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_r_v_b_25	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_r_v_b_25	lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25]	buffer	sp4_r_v_b_26	lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	sp4_r_v_b_26	lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21]	buffer	sp4_r_v_b_27	lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	sp4_r_v_b_27	lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	sp4_r_v_b_28	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_28	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_r_v_b_29	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_r_v_b_29	lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21]	buffer	sp4_r_v_b_3	lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	sp4_r_v_b_30	lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	sp4_r_v_b_30	lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	sp4_r_v_b_31	lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	sp4_r_v_b_31	lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	sp4_r_v_b_32	lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_32	lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	sp4_r_v_b_33	lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_r_v_b_33	lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_r_v_b_34	lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	sp4_r_v_b_34	lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_35	lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	sp4_r_v_b_35	lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_36	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_r_v_b_37	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	sp4_r_v_b_38	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	sp4_r_v_b_39	lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_4	lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_40	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_r_v_b_41	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	sp4_r_v_b_42	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	sp4_r_v_b_43	lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_44	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_r_v_b_45	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	sp4_r_v_b_46	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	sp4_r_v_b_47	lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_r_v_b_5	lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25]	buffer	sp4_r_v_b_6	lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21]	buffer	sp4_r_v_b_7	lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_8	lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_r_v_b_9	lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_0	lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_0	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_v_b_1	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_v_b_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp4_v_b_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp4_v_b_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp4_v_b_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp4_v_b_11	lc_trk_g1_3
+B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_12	lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_12	lc_trk_g1_4
+!B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_v_b_13	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_v_b_13	lc_trk_g1_5
+!B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_v_b_16	lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_v_b_16	lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_v_b_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_v_b_17	lc_trk_g1_1
+!B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_v_b_19	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_v_b_19	lc_trk_g1_3
+B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp4_v_b_2	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp4_v_b_2	lc_trk_g1_2
+B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp4_v_b_21	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_b_21	lc_trk_g1_5
+B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_b_24	lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_b_24	lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp4_v_b_26	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp4_v_b_26	lc_trk_g3_2
+!B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_v_b_29	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_v_b_29	lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp4_v_b_3	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp4_v_b_3	lc_trk_g1_3
+B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp4_v_b_30	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp4_v_b_30	lc_trk_g3_6
+B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp4_v_b_31	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp4_v_b_31	lc_trk_g3_7
+B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp4_v_b_35	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp4_v_b_35	lc_trk_g3_3
+!B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_v_b_37	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_v_b_37	lc_trk_g3_5
+B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp4_v_b_38	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp4_v_b_38	lc_trk_g3_6
+B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_4	lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_4	lc_trk_g1_4
+!B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_v_b_42	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_v_b_42	lc_trk_g3_2
+B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_v_b_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_v_b_45	lc_trk_g3_5
+!B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_v_b_5	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_v_b_5	lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp4_v_b_6	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp4_v_b_6	lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp4_v_b_7	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp4_v_b_7	lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_8	lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_8	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_v_b_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_v_b_9	lc_trk_g1_1
+!B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_v_t_10	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_v_t_10	lc_trk_g1_7
+!B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_v_t_11	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_v_t_11	lc_trk_g1_6
+!B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_v_t_12	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_v_t_12	lc_trk_g3_1
+B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp4_v_t_14	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp4_v_t_14	lc_trk_g3_3
+B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_t_17	lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_t_17	lc_trk_g3_4
+B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp4_v_t_2	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp4_v_t_2	lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_v_t_20	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_v_t_20	lc_trk_g3_1
+B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_t_21	lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_t_21	lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp4_v_t_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp4_v_t_23	lc_trk_g3_2
+B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_t_25	lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_t_25	lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp4_v_t_26	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp4_v_t_26	lc_trk_g3_7
+B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_v_t_28	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_v_t_28	lc_trk_g3_1
+!B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_v_t_29	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_v_t_29	lc_trk_g3_0
+B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp4_v_t_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp4_v_t_3	lc_trk_g1_6
+!B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_v_t_30	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_v_t_30	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_v_t_33	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_v_t_33	lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_v_t_34	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_v_t_34	lc_trk_g3_7
+!B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_v_t_35	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_v_t_35	lc_trk_g3_6
+!B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_v_t_7	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_v_t_7	lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_v_t_9	lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_v_t_9	lc_trk_g1_4
+!B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	tnl_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	tnl_op_4	lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	tnl_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	tnl_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	tnl_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	tnl_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	tnl_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	tnl_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	tnl_op_7	lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	tnr_op_0	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	tnr_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	tnr_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	tnr_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	tnr_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	tnr_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	tnr_op_3	lc_trk_g3_3
+!B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	tnr_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	tnr_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	tnr_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
+B4[47]	buffer	wire_mult/mult/O_10	sp12_h_l_11
+B4[52]	buffer	wire_mult/mult/O_10	sp12_v_t_19
+B4[51]	buffer	wire_mult/mult/O_10	sp12_v_t_3
+B4[46]	buffer	wire_mult/mult/O_10	sp4_h_l_9
+B5[47]	buffer	wire_mult/mult/O_10	sp4_h_r_36
+B5[46]	buffer	wire_mult/mult/O_10	sp4_h_r_4
+B4[53]	buffer	wire_mult/mult/O_10	sp4_r_v_b_21
+B5[53]	buffer	wire_mult/mult/O_10	sp4_r_v_b_37
+B5[52]	buffer	wire_mult/mult/O_10	sp4_r_v_b_5
+B4[48]	buffer	wire_mult/mult/O_10	sp4_v_b_4
+B5[51]	buffer	wire_mult/mult/O_10	sp4_v_t_25
+B5[48]	buffer	wire_mult/mult/O_10	sp4_v_t_9
+B6[47]	buffer	wire_mult/mult/O_11	sp12_h_l_13
+B6[51]	buffer	wire_mult/mult/O_11	sp12_v_b_6
+B6[52]	buffer	wire_mult/mult/O_11	sp12_v_t_21
+B6[46]	buffer	wire_mult/mult/O_11	sp4_h_l_11
+B7[47]	buffer	wire_mult/mult/O_11	sp4_h_l_27
+B7[46]	buffer	wire_mult/mult/O_11	sp4_h_r_6
+B6[53]	buffer	wire_mult/mult/O_11	sp4_r_v_b_23
+B7[53]	buffer	wire_mult/mult/O_11	sp4_r_v_b_39
+B7[52]	buffer	wire_mult/mult/O_11	sp4_r_v_b_7
+B7[51]	buffer	wire_mult/mult/O_11	sp4_v_b_38
+B6[48]	buffer	wire_mult/mult/O_11	sp4_v_b_6
+B7[48]	buffer	wire_mult/mult/O_11	sp4_v_t_11
+B8[48]	buffer	wire_mult/mult/O_12	sp12_h_l_15
+B8[47]	buffer	wire_mult/mult/O_12	sp12_h_r_0
+B8[52]	buffer	wire_mult/mult/O_12	sp12_v_b_8
+B8[46]	buffer	wire_mult/mult/O_12	sp4_h_r_24
+B9[47]	buffer	wire_mult/mult/O_12	sp4_h_r_40
+B9[46]	buffer	wire_mult/mult/O_12	sp4_h_r_8
+B8[53]	buffer	wire_mult/mult/O_12	sp4_r_v_b_25
+B9[53]	buffer	wire_mult/mult/O_12	sp4_r_v_b_41
+B9[52]	buffer	wire_mult/mult/O_12	sp4_r_v_b_9
+B9[51]	buffer	wire_mult/mult/O_12	sp4_v_b_24
+B9[48]	buffer	wire_mult/mult/O_12	sp4_v_b_8
+B8[51]	buffer	wire_mult/mult/O_12	sp4_v_t_29
+B10[48]	buffer	wire_mult/mult/O_13	sp12_h_r_18
+B10[47]	buffer	wire_mult/mult/O_13	sp12_h_r_2
+B10[52]	buffer	wire_mult/mult/O_13	sp12_v_t_9
+B11[47]	buffer	wire_mult/mult/O_13	sp4_h_l_31
+B11[46]	buffer	wire_mult/mult/O_13	sp4_h_r_10
+B10[46]	buffer	wire_mult/mult/O_13	sp4_h_r_26
+B11[52]	buffer	wire_mult/mult/O_13	sp4_r_v_b_11
+B10[53]	buffer	wire_mult/mult/O_13	sp4_r_v_b_27
+B11[53]	buffer	wire_mult/mult/O_13	sp4_r_v_b_43
+B11[48]	buffer	wire_mult/mult/O_13	sp4_v_b_10
+B11[51]	buffer	wire_mult/mult/O_13	sp4_v_b_26
+B10[51]	buffer	wire_mult/mult/O_13	sp4_v_b_42
+B12[48]	buffer	wire_mult/mult/O_14	sp12_h_l_19
+B12[47]	buffer	wire_mult/mult/O_14	sp12_h_l_3
+B12[52]	buffer	wire_mult/mult/O_14	sp12_v_b_12
+B12[46]	buffer	wire_mult/mult/O_14	sp4_h_l_17
+B13[46]	buffer	wire_mult/mult/O_14	sp4_h_r_12
+B13[47]	buffer	wire_mult/mult/O_14	sp4_h_r_44
+B13[52]	buffer	wire_mult/mult/O_14	sp4_r_v_b_13
+B12[53]	buffer	wire_mult/mult/O_14	sp4_r_v_b_29
+B13[53]	buffer	wire_mult/mult/O_14	sp4_r_v_b_45
+B13[48]	buffer	wire_mult/mult/O_14	sp4_v_b_12
+B13[51]	buffer	wire_mult/mult/O_14	sp4_v_t_17
+B12[51]	buffer	wire_mult/mult/O_14	sp4_v_t_33
+B14[47]	buffer	wire_mult/mult/O_15	sp12_h_l_5
+B14[48]	buffer	wire_mult/mult/O_15	sp12_h_r_22
+B14[52]	buffer	wire_mult/mult/O_15	sp12_v_t_13
+B15[46]	buffer	wire_mult/mult/O_15	sp4_h_l_3
+B14[46]	buffer	wire_mult/mult/O_15	sp4_h_r_30
+B15[47]	buffer	wire_mult/mult/O_15	sp4_h_r_46
+B15[52]	buffer	wire_mult/mult/O_15	sp4_r_v_b_15
+B14[53]	buffer	wire_mult/mult/O_15	sp4_r_v_b_31
+B15[53]	buffer	wire_mult/mult/O_15	sp4_r_v_b_47
+B15[51]	buffer	wire_mult/mult/O_15	sp4_v_b_30
+B15[48]	buffer	wire_mult/mult/O_15	sp4_v_t_3
+B14[51]	buffer	wire_mult/mult/O_15	sp4_v_t_35
+B0[47]	buffer	wire_mult/mult/O_8	sp12_h_r_8
+B0[51]	buffer	wire_mult/mult/O_8	sp12_v_b_0
+B0[52]	buffer	wire_mult/mult/O_8	sp12_v_t_15
+B1[47]	buffer	wire_mult/mult/O_8	sp4_h_l_21
+B1[46]	buffer	wire_mult/mult/O_8	sp4_h_r_0
+B0[46]	buffer	wire_mult/mult/O_8	sp4_h_r_16
+B1[52]	buffer	wire_mult/mult/O_8	sp4_r_v_b_1
+B0[53]	buffer	wire_mult/mult/O_8	sp4_r_v_b_17
+B1[53]	buffer	wire_mult/mult/O_8	sp4_r_v_b_33
+B0[48]	buffer	wire_mult/mult/O_8	sp4_v_b_0
+B1[48]	buffer	wire_mult/mult/O_8	sp4_v_b_16
+B1[51]	buffer	wire_mult/mult/O_8	sp4_v_t_21
+B2[47]	buffer	wire_mult/mult/O_9	sp12_h_l_9
+B2[51]	buffer	wire_mult/mult/O_9	sp12_v_b_2
+B2[52]	buffer	wire_mult/mult/O_9	sp12_v_t_17
+B2[46]	buffer	wire_mult/mult/O_9	sp4_h_l_7
+B3[46]	buffer	wire_mult/mult/O_9	sp4_h_r_2
+B3[47]	buffer	wire_mult/mult/O_9	sp4_h_r_34
+B2[53]	buffer	wire_mult/mult/O_9	sp4_r_v_b_19
+B3[52]	buffer	wire_mult/mult/O_9	sp4_r_v_b_3
+B3[53]	buffer	wire_mult/mult/O_9	sp4_r_v_b_35
+B2[48]	buffer	wire_mult/mult/O_9	sp4_v_b_2
+B3[51]	buffer	wire_mult/mult/O_9	sp4_v_t_23
+B3[48]	buffer	wire_mult/mult/O_9	sp4_v_t_7
+!B8[3],B9[3]	routing	sp12_h_l_22	sp12_v_b_1
+!B14[3],B15[3]	routing	sp12_h_l_22	sp12_v_t_22
+!B4[3],B5[3]	routing	sp12_h_l_23	sp12_h_r_0
+!B0[3],B1[3]	routing	sp12_h_l_23	sp12_v_b_0
+!B6[3],B7[3]	routing	sp12_h_l_23	sp12_v_t_23
+B2[3],B3[3]	routing	sp12_h_r_0	sp12_h_l_23
+B0[3],B1[3]	routing	sp12_h_r_0	sp12_v_b_0
+B6[3],B7[3]	routing	sp12_h_r_0	sp12_v_t_23
+B8[3],B9[3]	routing	sp12_h_r_1	sp12_v_b_1
+B14[3],B15[3]	routing	sp12_h_r_1	sp12_v_t_22
+!B2[3],B3[3]	routing	sp12_v_b_0	sp12_h_l_23
+B4[3],B5[3]	routing	sp12_v_b_0	sp12_h_r_0
+B6[3],!B7[3]	routing	sp12_v_b_0	sp12_v_t_23
+B11[3]	routing	sp12_v_b_1	sp12_h_l_22
+B12[3],B13[3]	routing	sp12_v_b_1	sp12_h_r_1
+B14[3],!B15[3]	routing	sp12_v_b_1	sp12_v_t_22
+B10[3]	routing	sp12_v_t_22	sp12_h_l_22
+B12[3],!B13[3]	routing	sp12_v_t_22	sp12_h_r_1
+B8[3],!B9[3]	routing	sp12_v_t_22	sp12_v_b_1
+B2[3],!B3[3]	routing	sp12_v_t_23	sp12_h_l_23
+B4[3],!B5[3]	routing	sp12_v_t_23	sp12_h_r_0
+B0[3],!B1[3]	routing	sp12_v_t_23	sp12_v_b_0
+!B12[5],B13[4],B13[6]	routing	sp4_h_l_36	sp4_h_r_9
+B1[8],B1[9],!B1[10]	routing	sp4_h_l_36	sp4_v_b_1
+B9[8],B9[9],B9[10]	routing	sp4_h_l_36	sp4_v_b_7
+B3[8],!B3[9],!B3[10]	routing	sp4_h_l_36	sp4_v_t_36
+!B10[4],B10[6],!B11[5]	routing	sp4_h_l_36	sp4_v_t_43
+!B0[5],!B1[4],B1[6]	routing	sp4_h_l_37	sp4_h_r_0
+!B8[12],B9[11],B9[13]	routing	sp4_h_l_37	sp4_h_r_8
+B0[4],!B0[6],B1[5]	routing	sp4_h_l_37	sp4_v_b_0
+B8[4],B8[6],B9[5]	routing	sp4_h_l_37	sp4_v_b_6
+!B2[4],!B2[6],B3[5]	routing	sp4_h_l_37	sp4_v_t_37
+B6[11],!B6[13],!B7[12]	routing	sp4_h_l_37	sp4_v_t_40
+B4[4],!B4[6],B5[5]	routing	sp4_h_l_38	sp4_v_b_3
+B12[4],B12[6],B13[5]	routing	sp4_h_l_38	sp4_v_b_9
+!B6[4],!B6[6],B7[5]	routing	sp4_h_l_38	sp4_v_t_38
+B10[11],!B10[13],!B11[12]	routing	sp4_h_l_38	sp4_v_t_45
+!B0[11],B0[13],B1[12]	routing	sp4_h_l_39	sp4_v_b_2
+B8[11],B8[13],B9[12]	routing	sp4_h_l_39	sp4_v_b_8
+!B2[11],!B2[13],B3[12]	routing	sp4_h_l_39	sp4_v_t_39
+!B11[8],!B11[9],B11[10]	routing	sp4_h_l_39	sp4_v_t_42
+B0[8],!B0[9],B0[10]	routing	sp4_h_l_40	sp4_h_r_1
+B8[12],!B9[11],B9[13]	routing	sp4_h_l_40	sp4_h_r_8
+B12[11],B12[13],B13[12]	routing	sp4_h_l_40	sp4_v_b_11
+!B4[11],B4[13],B5[12]	routing	sp4_h_l_40	sp4_v_b_5
+!B6[11],!B6[13],B7[12]	routing	sp4_h_l_40	sp4_v_t_40
+!B15[8],!B15[9],B15[10]	routing	sp4_h_l_40	sp4_v_t_47
+!B0[5],B1[4],B1[6]	routing	sp4_h_l_41	sp4_h_r_0
+!B8[8],B8[9],B8[10]	routing	sp4_h_l_41	sp4_h_r_7
+B13[8],B13[9],B13[10]	routing	sp4_h_l_41	sp4_v_b_10
+B5[8],B5[9],!B5[10]	routing	sp4_h_l_41	sp4_v_b_4
+B7[8],!B7[9],!B7[10]	routing	sp4_h_l_41	sp4_v_t_41
+!B14[4],B14[6],!B15[5]	routing	sp4_h_l_41	sp4_v_t_44
+B8[8],!B8[9],!B8[10]	routing	sp4_h_l_42	sp4_h_r_7
+B1[8],B1[9],B1[10]	routing	sp4_h_l_42	sp4_v_b_1
+B9[8],B9[9],!B9[10]	routing	sp4_h_l_42	sp4_v_b_7
+!B2[4],B2[6],!B3[5]	routing	sp4_h_l_42	sp4_v_t_37
+B11[8],!B11[9],!B11[10]	routing	sp4_h_l_42	sp4_v_t_42
+!B8[5],!B9[4],B9[6]	routing	sp4_h_l_43	sp4_h_r_6
+B0[4],B0[6],B1[5]	routing	sp4_h_l_43	sp4_v_b_0
+B8[4],!B8[6],B9[5]	routing	sp4_h_l_43	sp4_v_b_6
+!B10[4],!B10[6],B11[5]	routing	sp4_h_l_43	sp4_v_t_43
+B14[11],!B14[13],!B15[12]	routing	sp4_h_l_43	sp4_v_t_46
+B0[5],B1[4],!B1[6]	routing	sp4_h_l_44	sp4_h_r_0
+B4[4],B4[6],B5[5]	routing	sp4_h_l_44	sp4_v_b_3
+B12[4],!B12[6],B13[5]	routing	sp4_h_l_44	sp4_v_b_9
+B2[11],!B2[13],!B3[12]	routing	sp4_h_l_44	sp4_v_t_39
+!B14[4],!B14[6],B15[5]	routing	sp4_h_l_44	sp4_v_t_44
+B4[8],!B4[9],B4[10]	routing	sp4_h_l_45	sp4_h_r_4
+B0[11],B0[13],B1[12]	routing	sp4_h_l_45	sp4_v_b_2
+!B8[11],B8[13],B9[12]	routing	sp4_h_l_45	sp4_v_b_8
+!B3[8],!B3[9],B3[10]	routing	sp4_h_l_45	sp4_v_t_36
+!B10[11],!B10[13],B11[12]	routing	sp4_h_l_45	sp4_v_t_45
+!B12[11],B12[13],B13[12]	routing	sp4_h_l_46	sp4_v_b_11
+B4[11],B4[13],B5[12]	routing	sp4_h_l_46	sp4_v_b_5
+!B7[8],!B7[9],B7[10]	routing	sp4_h_l_46	sp4_v_t_41
+!B14[11],!B14[13],B15[12]	routing	sp4_h_l_46	sp4_v_t_46
+!B8[5],B9[4],B9[6]	routing	sp4_h_l_47	sp4_h_r_6
+B13[8],B13[9],!B13[10]	routing	sp4_h_l_47	sp4_v_b_10
+B5[8],B5[9],B5[10]	routing	sp4_h_l_47	sp4_v_b_4
+!B6[4],B6[6],!B7[5]	routing	sp4_h_l_47	sp4_v_t_38
+B15[8],!B15[9],!B15[10]	routing	sp4_h_l_47	sp4_v_t_47
+!B2[5],!B3[4],B3[6]	routing	sp4_h_r_0	sp4_h_l_37
+B6[5],B7[4],!B7[6]	routing	sp4_h_r_0	sp4_h_l_38
+!B10[12],B11[11],B11[13]	routing	sp4_h_r_0	sp4_h_l_45
+!B0[4],!B0[6],B1[5]	routing	sp4_h_r_0	sp4_v_b_0
+B4[11],!B4[13],!B5[12]	routing	sp4_h_r_0	sp4_v_b_5
+B2[4],!B2[6],B3[5]	routing	sp4_h_r_0	sp4_v_t_37
+B10[4],B10[6],B11[5]	routing	sp4_h_r_0	sp4_v_t_43
+B1[8],!B1[9],!B1[10]	routing	sp4_h_r_1	sp4_v_b_1
+!B8[4],B8[6],!B9[5]	routing	sp4_h_r_1	sp4_v_b_6
+B3[8],B3[9],!B3[10]	routing	sp4_h_r_1	sp4_v_t_36
+B11[8],B11[9],B11[10]	routing	sp4_h_r_1	sp4_v_t_42
+!B2[8],B2[9],B2[10]	routing	sp4_h_r_10	sp4_h_l_36
+!B10[5],B11[4],B11[6]	routing	sp4_h_r_10	sp4_h_l_43
+B14[8],!B14[9],!B14[10]	routing	sp4_h_r_10	sp4_h_l_47
+B13[8],!B13[9],!B13[10]	routing	sp4_h_r_10	sp4_v_b_10
+!B4[4],B4[6],!B5[5]	routing	sp4_h_r_10	sp4_v_b_3
+B7[8],B7[9],B7[10]	routing	sp4_h_r_10	sp4_v_t_41
+B15[8],B15[9],!B15[10]	routing	sp4_h_r_10	sp4_v_t_47
+B2[12],!B3[11],B3[13]	routing	sp4_h_r_11	sp4_h_l_39
+!B12[11],!B12[13],B13[12]	routing	sp4_h_r_11	sp4_v_b_11
+!B5[8],!B5[9],B5[10]	routing	sp4_h_r_11	sp4_v_b_4
+B6[11],B6[13],B7[12]	routing	sp4_h_r_11	sp4_v_t_40
+!B14[11],B14[13],B15[12]	routing	sp4_h_r_11	sp4_v_t_46
+!B2[12],B3[11],!B3[13]	routing	sp4_h_r_2	sp4_h_l_39
+B6[12],!B7[11],B7[13]	routing	sp4_h_r_2	sp4_h_l_40
+B14[8],!B14[9],B14[10]	routing	sp4_h_r_2	sp4_h_l_47
+!B0[11],!B0[13],B1[12]	routing	sp4_h_r_2	sp4_v_b_2
+!B9[8],!B9[9],B9[10]	routing	sp4_h_r_2	sp4_v_b_7
+!B2[11],B2[13],B3[12]	routing	sp4_h_r_2	sp4_v_t_39
+B10[11],B10[13],B11[12]	routing	sp4_h_r_2	sp4_v_t_45
+!B14[12],B15[11],B15[13]	routing	sp4_h_r_3	sp4_h_l_46
+!B4[4],!B4[6],B5[5]	routing	sp4_h_r_3	sp4_v_b_3
+B8[11],!B8[13],!B9[12]	routing	sp4_h_r_3	sp4_v_b_8
+B6[4],!B6[6],B7[5]	routing	sp4_h_r_3	sp4_v_t_38
+B14[4],B14[6],B15[5]	routing	sp4_h_r_3	sp4_v_t_44
+!B2[5],B3[4],B3[6]	routing	sp4_h_r_4	sp4_h_l_37
+B6[8],!B6[9],!B6[10]	routing	sp4_h_r_4	sp4_h_l_41
+!B10[8],B10[9],B10[10]	routing	sp4_h_r_4	sp4_h_l_42
+B5[8],!B5[9],!B5[10]	routing	sp4_h_r_4	sp4_v_b_4
+!B12[4],B12[6],!B13[5]	routing	sp4_h_r_4	sp4_v_b_9
+B7[8],B7[9],!B7[10]	routing	sp4_h_r_4	sp4_v_t_41
+B15[8],B15[9],B15[10]	routing	sp4_h_r_4	sp4_v_t_47
+!B13[8],!B13[9],B13[10]	routing	sp4_h_r_5	sp4_v_b_10
+!B4[11],!B4[13],B5[12]	routing	sp4_h_r_5	sp4_v_b_5
+!B6[11],B6[13],B7[12]	routing	sp4_h_r_5	sp4_v_t_40
+B14[11],B14[13],B15[12]	routing	sp4_h_r_5	sp4_v_t_46
+!B2[12],B3[11],B3[13]	routing	sp4_h_r_6	sp4_h_l_39
+!B10[5],!B11[4],B11[6]	routing	sp4_h_r_6	sp4_h_l_43
+B14[5],B15[4],!B15[6]	routing	sp4_h_r_6	sp4_h_l_44
+B12[11],!B12[13],!B13[12]	routing	sp4_h_r_6	sp4_v_b_11
+!B8[4],!B8[6],B9[5]	routing	sp4_h_r_6	sp4_v_b_6
+B2[4],B2[6],B3[5]	routing	sp4_h_r_6	sp4_v_t_37
+B10[4],!B10[6],B11[5]	routing	sp4_h_r_6	sp4_v_t_43
+!B0[4],B0[6],!B1[5]	routing	sp4_h_r_7	sp4_v_b_0
+B9[8],!B9[9],!B9[10]	routing	sp4_h_r_7	sp4_v_b_7
+B3[8],B3[9],B3[10]	routing	sp4_h_r_7	sp4_v_t_36
+B11[8],B11[9],!B11[10]	routing	sp4_h_r_7	sp4_v_t_42
+B6[8],!B6[9],B6[10]	routing	sp4_h_r_8	sp4_h_l_41
+!B10[12],B11[11],!B11[13]	routing	sp4_h_r_8	sp4_h_l_45
+B14[12],!B15[11],B15[13]	routing	sp4_h_r_8	sp4_h_l_46
+!B1[8],!B1[9],B1[10]	routing	sp4_h_r_8	sp4_v_b_1
+!B8[11],!B8[13],B9[12]	routing	sp4_h_r_8	sp4_v_b_8
+B2[11],B2[13],B3[12]	routing	sp4_h_r_8	sp4_v_t_39
+!B10[11],B10[13],B11[12]	routing	sp4_h_r_8	sp4_v_t_45
+B2[5],B3[4],!B3[6]	routing	sp4_h_r_9	sp4_h_l_37
+!B14[5],!B15[4],B15[6]	routing	sp4_h_r_9	sp4_h_l_44
+B0[11],!B0[13],!B1[12]	routing	sp4_h_r_9	sp4_v_b_2
+!B12[4],!B12[6],B13[5]	routing	sp4_h_r_9	sp4_v_b_9
+B6[4],B6[6],B7[5]	routing	sp4_h_r_9	sp4_v_t_38
+B14[4],!B14[6],B15[5]	routing	sp4_h_r_9	sp4_v_t_44
+B2[5],!B3[4],!B3[6]	routing	sp4_v_b_0	sp4_h_l_37
+!B6[12],!B7[11],B7[13]	routing	sp4_v_b_0	sp4_h_l_40
+B0[5],!B1[4],B1[6]	routing	sp4_v_b_0	sp4_h_r_0
+B8[5],B9[4],B9[6]	routing	sp4_v_b_0	sp4_h_r_6
+B2[4],!B2[6],!B3[5]	routing	sp4_v_b_0	sp4_v_t_37
+!B6[4],B6[6],B7[5]	routing	sp4_v_b_0	sp4_v_t_38
+B10[11],B10[13],!B11[12]	routing	sp4_v_b_0	sp4_v_t_45
+!B2[8],B2[9],!B2[10]	routing	sp4_v_b_1	sp4_h_l_36
+!B10[5],B11[4],!B11[6]	routing	sp4_v_b_1	sp4_h_l_43
+B0[8],B0[9],!B0[10]	routing	sp4_v_b_1	sp4_h_r_1
+B8[8],B8[9],B8[10]	routing	sp4_v_b_1	sp4_h_r_7
+!B3[8],B3[9],!B3[10]	routing	sp4_v_b_1	sp4_v_t_36
+B7[8],!B7[9],B7[10]	routing	sp4_v_b_1	sp4_v_t_41
+B14[4],B14[6],!B15[5]	routing	sp4_v_b_1	sp4_v_t_44
+!B6[5],B7[4],!B7[6]	routing	sp4_v_b_10	sp4_h_l_38
+!B14[8],B14[9],!B14[10]	routing	sp4_v_b_10	sp4_h_l_47
+B12[8],B12[9],!B12[10]	routing	sp4_v_b_10	sp4_h_r_10
+B4[8],B4[9],B4[10]	routing	sp4_v_b_10	sp4_h_r_4
+B3[8],!B3[9],B3[10]	routing	sp4_v_b_10	sp4_v_t_36
+B10[4],B10[6],!B11[5]	routing	sp4_v_b_10	sp4_v_t_43
+!B15[8],B15[9],!B15[10]	routing	sp4_v_b_10	sp4_v_t_47
+!B6[8],!B6[9],B6[10]	routing	sp4_v_b_11	sp4_h_l_41
+B14[12],!B15[11],!B15[13]	routing	sp4_v_b_11	sp4_h_l_46
+B12[12],B13[11],!B13[13]	routing	sp4_v_b_11	sp4_h_r_11
+B4[12],B5[11],B5[13]	routing	sp4_v_b_11	sp4_h_r_5
+B2[11],!B2[13],B3[12]	routing	sp4_v_b_11	sp4_v_t_39
+!B11[8],B11[9],B11[10]	routing	sp4_v_b_11	sp4_v_t_42
+!B14[11],B14[13],!B15[12]	routing	sp4_v_b_11	sp4_v_t_46
+B2[12],!B3[11],!B3[13]	routing	sp4_v_b_2	sp4_h_l_39
+!B10[8],!B10[9],B10[10]	routing	sp4_v_b_2	sp4_h_l_42
+B0[12],B1[11],!B1[13]	routing	sp4_v_b_2	sp4_h_r_2
+B8[12],B9[11],B9[13]	routing	sp4_v_b_2	sp4_h_r_8
+!B2[11],B2[13],!B3[12]	routing	sp4_v_b_2	sp4_v_t_39
+B6[11],!B6[13],B7[12]	routing	sp4_v_b_2	sp4_v_t_40
+!B15[8],B15[9],B15[10]	routing	sp4_v_b_2	sp4_v_t_47
+B6[5],!B7[4],!B7[6]	routing	sp4_v_b_3	sp4_h_l_38
+!B10[12],!B11[11],B11[13]	routing	sp4_v_b_3	sp4_h_l_45
+B4[5],!B5[4],B5[6]	routing	sp4_v_b_3	sp4_h_r_3
+B12[5],B13[4],B13[6]	routing	sp4_v_b_3	sp4_h_r_9
+B6[4],!B6[6],!B7[5]	routing	sp4_v_b_3	sp4_v_t_38
+!B10[4],B10[6],B11[5]	routing	sp4_v_b_3	sp4_v_t_43
+B14[11],B14[13],!B15[12]	routing	sp4_v_b_3	sp4_v_t_46
+!B6[8],B6[9],!B6[10]	routing	sp4_v_b_4	sp4_h_l_41
+!B14[5],B15[4],!B15[6]	routing	sp4_v_b_4	sp4_h_l_44
+B12[8],B12[9],B12[10]	routing	sp4_v_b_4	sp4_h_r_10
+B4[8],B4[9],!B4[10]	routing	sp4_v_b_4	sp4_h_r_4
+B2[4],B2[6],!B3[5]	routing	sp4_v_b_4	sp4_v_t_37
+!B7[8],B7[9],!B7[10]	routing	sp4_v_b_4	sp4_v_t_41
+B11[8],!B11[9],B11[10]	routing	sp4_v_b_4	sp4_v_t_42
+B6[12],!B7[11],!B7[13]	routing	sp4_v_b_5	sp4_h_l_40
+!B14[8],!B14[9],B14[10]	routing	sp4_v_b_5	sp4_h_l_47
+B12[12],B13[11],B13[13]	routing	sp4_v_b_5	sp4_h_r_11
+B4[12],B5[11],!B5[13]	routing	sp4_v_b_5	sp4_h_r_5
+!B3[8],B3[9],B3[10]	routing	sp4_v_b_5	sp4_v_t_36
+!B6[11],B6[13],!B7[12]	routing	sp4_v_b_5	sp4_v_t_40
+B10[11],!B10[13],B11[12]	routing	sp4_v_b_5	sp4_v_t_45
+B10[5],!B11[4],!B11[6]	routing	sp4_v_b_6	sp4_h_l_43
+!B14[12],!B15[11],B15[13]	routing	sp4_v_b_6	sp4_h_l_46
+B0[5],B1[4],B1[6]	routing	sp4_v_b_6	sp4_h_r_0
+B8[5],!B9[4],B9[6]	routing	sp4_v_b_6	sp4_h_r_6
+B2[11],B2[13],!B3[12]	routing	sp4_v_b_6	sp4_v_t_39
+B10[4],!B10[6],!B11[5]	routing	sp4_v_b_6	sp4_v_t_43
+!B14[4],B14[6],B15[5]	routing	sp4_v_b_6	sp4_v_t_44
+!B2[5],B3[4],!B3[6]	routing	sp4_v_b_7	sp4_h_l_37
+!B10[8],B10[9],!B10[10]	routing	sp4_v_b_7	sp4_h_l_42
+B0[8],B0[9],B0[10]	routing	sp4_v_b_7	sp4_h_r_1
+B8[8],B8[9],!B8[10]	routing	sp4_v_b_7	sp4_h_r_7
+B6[4],B6[6],!B7[5]	routing	sp4_v_b_7	sp4_v_t_38
+!B11[8],B11[9],!B11[10]	routing	sp4_v_b_7	sp4_v_t_42
+B15[8],!B15[9],B15[10]	routing	sp4_v_b_7	sp4_v_t_47
+!B2[8],!B2[9],B2[10]	routing	sp4_v_b_8	sp4_h_l_36
+B10[12],!B11[11],!B11[13]	routing	sp4_v_b_8	sp4_h_l_45
+B0[12],B1[11],B1[13]	routing	sp4_v_b_8	sp4_h_r_2
+B8[12],B9[11],!B9[13]	routing	sp4_v_b_8	sp4_h_r_8
+!B7[8],B7[9],B7[10]	routing	sp4_v_b_8	sp4_v_t_41
+!B10[11],B10[13],!B11[12]	routing	sp4_v_b_8	sp4_v_t_45
+B14[11],!B14[13],B15[12]	routing	sp4_v_b_8	sp4_v_t_46
+!B2[12],!B3[11],B3[13]	routing	sp4_v_b_9	sp4_h_l_39
+B14[5],!B15[4],!B15[6]	routing	sp4_v_b_9	sp4_h_l_44
+B4[5],B5[4],B5[6]	routing	sp4_v_b_9	sp4_h_r_3
+B12[5],!B13[4],B13[6]	routing	sp4_v_b_9	sp4_h_r_9
+!B2[4],B2[6],B3[5]	routing	sp4_v_b_9	sp4_v_t_37
+B6[11],B6[13],!B7[12]	routing	sp4_v_b_9	sp4_v_t_40
+B14[4],!B14[6],!B15[5]	routing	sp4_v_b_9	sp4_v_t_44
+B2[8],B2[9],!B2[10]	routing	sp4_v_t_36	sp4_h_l_36
+B10[8],B10[9],B10[10]	routing	sp4_v_t_36	sp4_h_l_42
+!B0[8],B0[9],!B0[10]	routing	sp4_v_t_36	sp4_h_r_1
+!B8[5],B9[4],!B9[6]	routing	sp4_v_t_36	sp4_h_r_6
+!B1[8],B1[9],!B1[10]	routing	sp4_v_t_36	sp4_v_b_1
+B5[8],!B5[9],B5[10]	routing	sp4_v_t_36	sp4_v_b_4
+B12[4],B12[6],!B13[5]	routing	sp4_v_t_36	sp4_v_b_9
+B2[5],!B3[4],B3[6]	routing	sp4_v_t_37	sp4_h_l_37
+B10[5],B11[4],B11[6]	routing	sp4_v_t_37	sp4_h_l_43
+B0[5],!B1[4],!B1[6]	routing	sp4_v_t_37	sp4_h_r_0
+!B4[12],!B5[11],B5[13]	routing	sp4_v_t_37	sp4_h_r_5
+B0[4],!B0[6],!B1[5]	routing	sp4_v_t_37	sp4_v_b_0
+!B4[4],B4[6],B5[5]	routing	sp4_v_t_37	sp4_v_b_3
+B8[11],B8[13],!B9[12]	routing	sp4_v_t_37	sp4_v_b_8
+B6[5],!B7[4],B7[6]	routing	sp4_v_t_38	sp4_h_l_38
+B14[5],B15[4],B15[6]	routing	sp4_v_t_38	sp4_h_l_44
+B4[5],!B5[4],!B5[6]	routing	sp4_v_t_38	sp4_h_r_3
+!B8[12],!B9[11],B9[13]	routing	sp4_v_t_38	sp4_h_r_8
+B12[11],B12[13],!B13[12]	routing	sp4_v_t_38	sp4_v_b_11
+B4[4],!B4[6],!B5[5]	routing	sp4_v_t_38	sp4_v_b_3
+!B8[4],B8[6],B9[5]	routing	sp4_v_t_38	sp4_v_b_6
+B2[12],B3[11],!B3[13]	routing	sp4_v_t_39	sp4_h_l_39
+B10[12],B11[11],B11[13]	routing	sp4_v_t_39	sp4_h_l_45
+B0[12],!B1[11],!B1[13]	routing	sp4_v_t_39	sp4_h_r_2
+!B8[8],!B8[9],B8[10]	routing	sp4_v_t_39	sp4_h_r_7
+!B13[8],B13[9],B13[10]	routing	sp4_v_t_39	sp4_v_b_10
+!B0[11],B0[13],!B1[12]	routing	sp4_v_t_39	sp4_v_b_2
+B4[11],!B4[13],B5[12]	routing	sp4_v_t_39	sp4_v_b_5
+B6[12],B7[11],!B7[13]	routing	sp4_v_t_40	sp4_h_l_40
+B14[12],B15[11],B15[13]	routing	sp4_v_t_40	sp4_h_l_46
+!B12[8],!B12[9],B12[10]	routing	sp4_v_t_40	sp4_h_r_10
+B4[12],!B5[11],!B5[13]	routing	sp4_v_t_40	sp4_h_r_5
+!B1[8],B1[9],B1[10]	routing	sp4_v_t_40	sp4_v_b_1
+!B4[11],B4[13],!B5[12]	routing	sp4_v_t_40	sp4_v_b_5
+B8[11],!B8[13],B9[12]	routing	sp4_v_t_40	sp4_v_b_8
+B6[8],B6[9],!B6[10]	routing	sp4_v_t_41	sp4_h_l_41
+B14[8],B14[9],B14[10]	routing	sp4_v_t_41	sp4_h_l_47
+!B4[8],B4[9],!B4[10]	routing	sp4_v_t_41	sp4_h_r_4
+!B12[5],B13[4],!B13[6]	routing	sp4_v_t_41	sp4_h_r_9
+B0[4],B0[6],!B1[5]	routing	sp4_v_t_41	sp4_v_b_0
+!B5[8],B5[9],!B5[10]	routing	sp4_v_t_41	sp4_v_b_4
+B9[8],!B9[9],B9[10]	routing	sp4_v_t_41	sp4_v_b_7
+B2[8],B2[9],B2[10]	routing	sp4_v_t_42	sp4_h_l_36
+B10[8],B10[9],!B10[10]	routing	sp4_v_t_42	sp4_h_l_42
+!B0[5],B1[4],!B1[6]	routing	sp4_v_t_42	sp4_h_r_0
+!B8[8],B8[9],!B8[10]	routing	sp4_v_t_42	sp4_h_r_7
+B13[8],!B13[9],B13[10]	routing	sp4_v_t_42	sp4_v_b_10
+B4[4],B4[6],!B5[5]	routing	sp4_v_t_42	sp4_v_b_3
+!B9[8],B9[9],!B9[10]	routing	sp4_v_t_42	sp4_v_b_7
+B2[5],B3[4],B3[6]	routing	sp4_v_t_43	sp4_h_l_37
+B10[5],!B11[4],B11[6]	routing	sp4_v_t_43	sp4_h_l_43
+!B12[12],!B13[11],B13[13]	routing	sp4_v_t_43	sp4_h_r_11
+B8[5],!B9[4],!B9[6]	routing	sp4_v_t_43	sp4_h_r_6
+B0[11],B0[13],!B1[12]	routing	sp4_v_t_43	sp4_v_b_2
+B8[4],!B8[6],!B9[5]	routing	sp4_v_t_43	sp4_v_b_6
+!B12[4],B12[6],B13[5]	routing	sp4_v_t_43	sp4_v_b_9
+B6[5],B7[4],B7[6]	routing	sp4_v_t_44	sp4_h_l_38
+B14[5],!B15[4],B15[6]	routing	sp4_v_t_44	sp4_h_l_44
+!B0[12],!B1[11],B1[13]	routing	sp4_v_t_44	sp4_h_r_2
+B12[5],!B13[4],!B13[6]	routing	sp4_v_t_44	sp4_h_r_9
+!B0[4],B0[6],B1[5]	routing	sp4_v_t_44	sp4_v_b_0
+B4[11],B4[13],!B5[12]	routing	sp4_v_t_44	sp4_v_b_5
+B12[4],!B12[6],!B13[5]	routing	sp4_v_t_44	sp4_v_b_9
+B2[12],B3[11],B3[13]	routing	sp4_v_t_45	sp4_h_l_39
+B10[12],B11[11],!B11[13]	routing	sp4_v_t_45	sp4_h_l_45
+!B0[8],!B0[9],B0[10]	routing	sp4_v_t_45	sp4_h_r_1
+B8[12],!B9[11],!B9[13]	routing	sp4_v_t_45	sp4_h_r_8
+B12[11],!B12[13],B13[12]	routing	sp4_v_t_45	sp4_v_b_11
+!B5[8],B5[9],B5[10]	routing	sp4_v_t_45	sp4_v_b_4
+!B8[11],B8[13],!B9[12]	routing	sp4_v_t_45	sp4_v_b_8
+B6[12],B7[11],B7[13]	routing	sp4_v_t_46	sp4_h_l_40
+B14[12],B15[11],!B15[13]	routing	sp4_v_t_46	sp4_h_l_46
+B12[12],!B13[11],!B13[13]	routing	sp4_v_t_46	sp4_h_r_11
+!B4[8],!B4[9],B4[10]	routing	sp4_v_t_46	sp4_h_r_4
+!B12[11],B12[13],!B13[12]	routing	sp4_v_t_46	sp4_v_b_11
+B0[11],!B0[13],B1[12]	routing	sp4_v_t_46	sp4_v_b_2
+!B9[8],B9[9],B9[10]	routing	sp4_v_t_46	sp4_v_b_7
+B6[8],B6[9],B6[10]	routing	sp4_v_t_47	sp4_h_l_41
+!B12[8],B12[9],!B12[10]	routing	sp4_v_t_47	sp4_h_r_10
+!B4[5],B5[4],!B5[6]	routing	sp4_v_t_47	sp4_h_r_3
+B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
+!B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
+B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
+"""
+database_dsp2_5k_txt = """
+B0[50]	Cascade	MULT2_LC00_inmux02_5
+B2[50]	Cascade	MULT2_LC01_inmux02_5
+B4[50]	Cascade	MULT2_LC02_inmux02_5
+B6[50]	Cascade	MULT2_LC03_inmux02_5
+B8[50]	Cascade	MULT2_LC04_inmux02_5
+B10[50]	Cascade	MULT2_LC05_inmux02_5
+B12[50]	Cascade	MULT2_LC06_inmux02_5
+B14[50]	Cascade	MULT2_LC07_inmux02_5
+B1[7]	IpConfig	CBIT_0
+B0[7]	IpConfig	CBIT_1
+B3[7]	IpConfig	CBIT_2
+B2[7]	IpConfig	CBIT_3
+B5[7]	IpConfig	CBIT_4
+B4[7]	IpConfig	CBIT_5
+B7[7]	IpConfig	CBIT_6
+B6[7]	IpConfig	CBIT_7
+B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43]	LC_0
+B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43]	LC_1
+B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43]	LC_2
+B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43]	LC_3
+B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43]	LC_4
+B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43]	LC_5
+B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43]	LC_6
+B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43]	LC_7
+B0[0]	NegClk
+B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	bnl_op_0	lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	bnl_op_0	lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	bnl_op_1	lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	bnl_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	bnl_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	bnl_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	bnl_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	bnl_op_3	lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	bnl_op_4	lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	bnl_op_4	lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	bnl_op_5	lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	bnl_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	bnl_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	bnl_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	bnl_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	bnl_op_7	lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	bnr_op_0	lc_trk_g0_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	bnr_op_1	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	bnr_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	bnr_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	bnr_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	bnr_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	bnr_op_3	lc_trk_g1_3
+B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	bnr_op_4	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	bnr_op_5	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	bnr_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	bnr_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	bnr_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	bnr_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	bnr_op_7	lc_trk_g1_7
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17]	buffer	glb2local_0	lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
+!B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_0	glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_0	glb2local_2
+!B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_0	wire_mult/lc_7/clk
+!B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_0	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
+!B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_1	glb2local_1
+!B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_1	glb2local_2
+!B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_1	glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_1	wire_mult/lc_7/clk
+B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_2	glb2local_0
+B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_2	glb2local_1
+B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_2	glb2local_2
+B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_2	glb2local_3
+B2[0],!B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_2	wire_mult/lc_7/clk
+!B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_2	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_3	glb2local_0
+B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_3	glb2local_1
+B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
+B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_3	glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_3	wire_mult/lc_7/clk
+!B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_4	glb2local_0
+!B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_4	glb2local_1
+!B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
+!B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_4	glb2local_3
+!B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_4	wire_mult/lc_7/clk
+B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
+!B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
+!B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_5	glb2local_2
+!B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
+!B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_5	wire_mult/lc_7/clk
+B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_6	glb2local_0
+B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_6	glb2local_1
+B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
+B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_6	glb2local_3
+B2[0],B2[1],B2[2],!B3[0],!B3[2]	buffer	glb_netwk_6	wire_mult/lc_7/clk
+B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_6	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_7	glb2local_0
+B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_7	glb2local_1
+B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_7	glb2local_2
+B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_7	glb2local_3
+B2[0],B2[1],B2[2],B3[0],!B3[2]	buffer	glb_netwk_7	wire_mult/lc_7/clk
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g0_0	wire_mult/lc_1/in_1
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g0_0	wire_mult/lc_3/in_1
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g0_0	wire_mult/lc_5/in_1
+!B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g0_0	wire_mult/lc_7/clk
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g0_0	wire_mult/lc_7/in_1
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g0_1	wire_mult/lc_0/in_1
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g0_1	wire_mult/lc_2/in_1
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_mult/lc_4/in_1
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g0_1	wire_mult/lc_6/in_1
+!B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_2	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_3
+!B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_3
+!B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g0_2	wire_mult/lc_7/cen
+!B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_3
+!B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_3
+!B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_4	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_3
+!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],!B7[31]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],!B11[31]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_3
+!B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g0_4	wire_mult/lc_7/s_r
+!B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_3
+!B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_3
+!B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_6	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_3
+!B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_3
+!B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_3
+!B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_3
+B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_1	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_3
+!B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g1_1	wire_mult/lc_7/clk
+B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_3
+!B4[0],B4[1],B5[0],B5[1]	buffer	lc_trk_g1_3	wire_mult/lc_7/cen
+B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_5	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_3
+!B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g1_5	wire_mult/lc_7/s_r
+B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_3
+B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_3
+B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_7	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_3
+B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_3
+!B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_3
+B2[0],!B2[1],B2[2],!B3[0],B3[2]	buffer	lc_trk_g2_0	wire_mult/lc_7/clk
+!B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_3
+!B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_2	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_3
+B4[0],B4[1],!B5[0],B5[1]	buffer	lc_trk_g2_2	wire_mult/lc_7/cen
+!B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_4	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_3
+B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g2_4	wire_mult/lc_7/s_r
+!B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_6	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_3
+!B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_3
+!B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_3
+!B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_3
+B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_1	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_3
+B2[0],!B2[1],B2[2],B3[0],B3[2]	buffer	lc_trk_g3_1	wire_mult/lc_7/clk
+B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_3	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_3
+B4[0],B4[1],B5[0],B5[1]	buffer	lc_trk_g3_3	wire_mult/lc_7/cen
+B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_5	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_3
+B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g3_5	wire_mult/lc_7/s_r
+B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_3
+B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_3
+B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_7	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_3
+B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_3
+B0[14],!B1[14],B1[15],!B1[16],B1[17]	buffer	lft_op_0	lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25]	buffer	lft_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	lft_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21]	buffer	lft_op_3	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21]	buffer	lft_op_3	lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	lft_op_4	lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17]	buffer	lft_op_4	lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18]	buffer	lft_op_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18]	buffer	lft_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25]	buffer	lft_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25]	buffer	lft_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	lft_op_7	lc_trk_g0_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	rgt_op_0	lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	rgt_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18]	buffer	rgt_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	rgt_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	rgt_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	rgt_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	rgt_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	rgt_op_3	lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	rgt_op_4	lc_trk_g2_4
+B14[15],!B14[16],B14[17],B14[18],!B15[18]	buffer	rgt_op_5	lc_trk_g3_5
+B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	rgt_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	rgt_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
+B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_l_0	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_l_0	lc_trk_g1_3
+!B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_l_11	lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_l_11	lc_trk_g1_4
+B4[2]	buffer	sp12_h_l_11	sp4_h_r_18
+!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_l_13	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_l_13	lc_trk_g1_6
+B6[2]	buffer	sp12_h_l_13	sp4_h_l_6
+!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_l_14	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_l_14	lc_trk_g1_1
+!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_l_18	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_l_18	lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_l_21	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_l_21	lc_trk_g1_6
+B14[2]	buffer	sp12_h_l_21	sp4_h_r_23
+B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_l_4	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_l_4	lc_trk_g1_7
+!B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp12_h_l_8	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp12_h_l_8	lc_trk_g1_3
+!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_l_9	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_l_9	lc_trk_g1_2
+B3[1]	buffer	sp12_h_l_9	sp4_h_r_17
+B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	sp12_h_r_0	lc_trk_g1_0
+B13[19]	buffer	sp12_h_r_0	sp4_h_r_12
+B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	sp12_h_r_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
+!B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_r_13	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_r_13	lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_r_15	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_r_15	lc_trk_g1_7
+!B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_16	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_16	lc_trk_g1_0
+B8[2]	buffer	sp12_h_r_16	sp4_h_l_9
+!B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_r_18	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_r_18	lc_trk_g1_2
+B10[2]	buffer	sp12_h_r_18	sp4_h_r_21
+!B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_r_19	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_r_19	lc_trk_g1_3
+B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_r_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_r_2	lc_trk_g1_2
+B12[19]	buffer	sp12_h_r_2	sp4_h_l_0
+!B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_20	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_20	lc_trk_g1_4
+B12[2]	buffer	sp12_h_r_20	sp4_h_r_22
+!B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_r_23	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_r_23	lc_trk_g1_7
+B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_r_4	lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17]	buffer	sp12_h_r_4	lc_trk_g1_4
+B15[19]	buffer	sp12_h_r_4	sp4_h_l_3
+B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_r_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_r_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_r_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_r_6	lc_trk_g1_6
+B14[19]	buffer	sp12_h_r_6	sp4_h_r_15
+!B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_8	lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_8	lc_trk_g1_0
+B0[2]	buffer	sp12_h_r_8	sp4_h_r_16
+!B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_r_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_r_9	lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
+B1[19]	buffer	sp12_v_b_1	sp4_v_t_1
+!B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_12	lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_12	lc_trk_g3_4
+!B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp12_v_b_13	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp12_v_b_13	lc_trk_g3_5
+B7[19]	buffer	sp12_v_b_13	sp4_v_b_18
+!B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp12_v_b_14	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp12_v_b_14	lc_trk_g3_6
+!B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_16	lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_b_16	lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp12_v_b_18	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp12_v_b_18	lc_trk_g3_2
+B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	sp12_v_b_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	sp12_v_b_2	lc_trk_g3_2
+!B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_b_22	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_b_22	lc_trk_g3_6
+!B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp12_v_b_23	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp12_v_b_23	lc_trk_g3_7
+B10[19]	buffer	sp12_v_b_23	sp4_v_b_23
+B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	sp12_v_b_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	sp12_v_b_3	lc_trk_g3_3
+B0[19]	buffer	sp12_v_b_3	sp4_v_t_0
+B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	sp12_v_b_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	sp12_v_b_5	lc_trk_g3_5
+B3[19]	buffer	sp12_v_b_5	sp4_v_b_14
+!B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_8	lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_b_8	lc_trk_g3_0
+!B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp12_v_b_9	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp12_v_b_9	lc_trk_g3_1
+B5[19]	buffer	sp12_v_b_9	sp4_v_b_16
+!B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp12_v_t_12	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp12_v_t_12	lc_trk_g3_7
+B6[19]	buffer	sp12_v_t_12	sp4_v_b_19
+!B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp12_v_t_14	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp12_v_t_14	lc_trk_g3_1
+B9[19]	buffer	sp12_v_t_14	sp4_v_b_20
+!B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp12_v_t_16	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp12_v_t_16	lc_trk_g3_3
+B8[19]	buffer	sp12_v_t_16	sp4_v_t_8
+!B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp12_v_t_18	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp12_v_t_18	lc_trk_g3_5
+B11[19]	buffer	sp12_v_t_18	sp4_v_t_11
+!B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_t_19	lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_t_19	lc_trk_g3_4
+B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_t_3	lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_t_3	lc_trk_g3_4
+B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	sp12_v_t_4	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	sp12_v_t_4	lc_trk_g3_7
+B2[19]	buffer	sp12_v_t_4	sp4_v_t_2
+B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	sp12_v_t_5	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	sp12_v_t_5	lc_trk_g3_6
+!B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp12_v_t_8	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_t_8	lc_trk_g3_3
+B4[19]	buffer	sp12_v_t_8	sp4_v_t_4
+!B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_t_9	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp12_v_t_9	lc_trk_g3_2
+B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_h_l_0	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_h_l_0	lc_trk_g1_5
+B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_l_12	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_l_12	lc_trk_g3_1
+!B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_13	lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_13	lc_trk_g3_0
+!B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_l_15	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_l_15	lc_trk_g3_2
+!B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_17	lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_17	lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_l_18	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_l_18	lc_trk_g3_7
+B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_h_l_20	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_h_l_20	lc_trk_g3_1
+B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_l_22	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_l_22	lc_trk_g3_3
+B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_h_l_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_h_l_23	lc_trk_g3_2
+B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_l_24	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_l_24	lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_l_27	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_l_27	lc_trk_g3_6
+B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_h_l_28	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_h_l_28	lc_trk_g3_1
+B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_h_l_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_h_l_3	lc_trk_g1_6
+B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_33	lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_33	lc_trk_g3_4
+B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_l_34	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_l_34	lc_trk_g3_7
+B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_l_6	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_l_6	lc_trk_g1_3
+B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_l_9	lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_l_9	lc_trk_g1_4
+!B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_h_r_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_h_r_11	lc_trk_g1_3
+B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_12	lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_12	lc_trk_g1_4
+B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_h_r_15	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_h_r_15	lc_trk_g1_7
+B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_16	lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_16	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_h_r_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_h_r_17	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_18	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_18	lc_trk_g1_2
+!B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_2	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_2	lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_r_21	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_r_21	lc_trk_g1_5
+B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_22	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_22	lc_trk_g1_6
+B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_23	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_23	lc_trk_g1_7
+!B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_27	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_27	lc_trk_g3_3
+B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_h_r_29	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_h_r_29	lc_trk_g3_5
+!B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_3	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_3	lc_trk_g1_3
+!B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_30	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_30	lc_trk_g3_6
+B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_32	lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_32	lc_trk_g3_0
+B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_r_36	lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_r_36	lc_trk_g3_4
+B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_r_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_r_39	lc_trk_g3_7
+!B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
+B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_40	lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_40	lc_trk_g3_0
+B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_42	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_42	lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_43	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_43	lc_trk_g3_3
+B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_h_r_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_r_45	lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_46	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_46	lc_trk_g3_6
+B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_6	lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_8	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_h_r_9	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_h_r_9	lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_0	lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_r_v_b_1	lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25]	buffer	sp4_r_v_b_10	lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21]	buffer	sp4_r_v_b_11	lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_12	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_r_v_b_13	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25]	buffer	sp4_r_v_b_14	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21]	buffer	sp4_r_v_b_15	lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_16	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_r_v_b_17	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25]	buffer	sp4_r_v_b_18	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21]	buffer	sp4_r_v_b_19	lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25]	buffer	sp4_r_v_b_2	lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_20	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_r_v_b_21	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25]	buffer	sp4_r_v_b_22	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21]	buffer	sp4_r_v_b_23	lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_24	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_24	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_r_v_b_25	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_r_v_b_25	lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25]	buffer	sp4_r_v_b_26	lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	sp4_r_v_b_26	lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21]	buffer	sp4_r_v_b_27	lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	sp4_r_v_b_27	lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	sp4_r_v_b_28	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_28	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_r_v_b_29	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_r_v_b_29	lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21]	buffer	sp4_r_v_b_3	lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	sp4_r_v_b_30	lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	sp4_r_v_b_30	lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	sp4_r_v_b_31	lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	sp4_r_v_b_31	lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	sp4_r_v_b_32	lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_32	lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	sp4_r_v_b_33	lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_r_v_b_33	lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_r_v_b_34	lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	sp4_r_v_b_34	lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_35	lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	sp4_r_v_b_35	lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_36	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_r_v_b_37	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	sp4_r_v_b_38	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	sp4_r_v_b_39	lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_4	lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_40	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_r_v_b_41	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	sp4_r_v_b_42	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	sp4_r_v_b_43	lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_44	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_r_v_b_45	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	sp4_r_v_b_46	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	sp4_r_v_b_47	lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_r_v_b_5	lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25]	buffer	sp4_r_v_b_6	lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21]	buffer	sp4_r_v_b_7	lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_8	lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_r_v_b_9	lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_0	lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_0	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_v_b_1	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_v_b_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp4_v_b_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp4_v_b_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp4_v_b_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp4_v_b_11	lc_trk_g1_3
+B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp4_v_b_14	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp4_v_b_14	lc_trk_g1_6
+!B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_v_b_16	lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_v_b_16	lc_trk_g1_0
+!B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_v_b_18	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_v_b_18	lc_trk_g1_2
+!B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_v_b_19	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_v_b_19	lc_trk_g1_3
+B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp4_v_b_2	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp4_v_b_2	lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_v_b_20	lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_v_b_20	lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_v_b_23	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_v_b_23	lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_v_b_25	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_v_b_25	lc_trk_g3_1
+B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp4_v_b_27	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp4_v_b_27	lc_trk_g3_3
+B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp4_v_b_3	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp4_v_b_3	lc_trk_g1_3
+B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_b_32	lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_b_32	lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp4_v_b_35	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp4_v_b_35	lc_trk_g3_3
+B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_b_36	lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_b_36	lc_trk_g3_4
+!B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_v_b_37	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_v_b_37	lc_trk_g3_5
+B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp4_v_b_38	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp4_v_b_38	lc_trk_g3_6
+B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_4	lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_4	lc_trk_g1_4
+B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_v_b_41	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_v_b_41	lc_trk_g3_1
+B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_v_b_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_v_b_45	lc_trk_g3_5
+!B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_v_b_47	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_v_b_47	lc_trk_g3_7
+!B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_v_b_5	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_v_b_5	lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp4_v_b_6	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp4_v_b_6	lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp4_v_b_7	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp4_v_b_7	lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_8	lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_8	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_v_b_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_v_b_9	lc_trk_g1_1
+!B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_v_t_0	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_v_t_0	lc_trk_g1_5
+B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_t_1	lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_t_1	lc_trk_g1_4
+!B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_v_t_11	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_v_t_11	lc_trk_g1_6
+B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_t_13	lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_t_13	lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp4_v_t_15	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp4_v_t_15	lc_trk_g3_2
+!B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_v_t_16	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_v_t_16	lc_trk_g3_5
+B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_t_17	lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_t_17	lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp4_v_t_18	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp4_v_t_18	lc_trk_g3_7
+B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp4_v_t_19	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp4_v_t_19	lc_trk_g3_6
+B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp4_v_t_2	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp4_v_t_2	lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_v_t_20	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_v_t_20	lc_trk_g3_1
+B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp4_v_t_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp4_v_t_23	lc_trk_g3_2
+B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp4_v_t_26	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp4_v_t_26	lc_trk_g3_7
+!B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_v_t_29	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_v_t_29	lc_trk_g3_0
+!B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_v_t_30	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_v_t_30	lc_trk_g3_3
+!B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_v_t_31	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_v_t_31	lc_trk_g3_2
+!B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_v_t_33	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_v_t_33	lc_trk_g3_4
+!B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_v_t_35	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_v_t_35	lc_trk_g3_6
+B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_v_t_4	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_v_t_4	lc_trk_g1_1
+B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp4_v_t_8	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_t_8	lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	tnl_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	tnl_op_4	lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	tnl_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	tnl_op_5	lc_trk_g2_5
+!B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	tnl_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	tnl_op_7	lc_trk_g2_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	tnr_op_0	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
+!B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	tnr_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	tnr_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	tnr_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	tnr_op_3	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	tnr_op_4	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	tnr_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	tnr_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	tnr_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
+B0[47]	buffer	wire_mult/mult/O_16	sp12_h_r_8
+B0[51]	buffer	wire_mult/mult/O_16	sp12_v_b_0
+B0[52]	buffer	wire_mult/mult/O_16	sp12_v_b_16
+B1[46]	buffer	wire_mult/mult/O_16	sp4_h_r_0
+B0[46]	buffer	wire_mult/mult/O_16	sp4_h_r_16
+B1[47]	buffer	wire_mult/mult/O_16	sp4_h_r_32
+B1[52]	buffer	wire_mult/mult/O_16	sp4_r_v_b_1
+B0[53]	buffer	wire_mult/mult/O_16	sp4_r_v_b_17
+B1[53]	buffer	wire_mult/mult/O_16	sp4_r_v_b_33
+B0[48]	buffer	wire_mult/mult/O_16	sp4_v_b_0
+B1[48]	buffer	wire_mult/mult/O_16	sp4_v_b_16
+B1[51]	buffer	wire_mult/mult/O_16	sp4_v_b_32
+B2[47]	buffer	wire_mult/mult/O_17	sp12_h_l_9
+B2[52]	buffer	wire_mult/mult/O_17	sp12_v_b_18
+B2[51]	buffer	wire_mult/mult/O_17	sp12_v_b_2
+B3[47]	buffer	wire_mult/mult/O_17	sp4_h_l_23
+B2[46]	buffer	wire_mult/mult/O_17	sp4_h_r_18
+B3[46]	buffer	wire_mult/mult/O_17	sp4_h_r_2
+B2[53]	buffer	wire_mult/mult/O_17	sp4_r_v_b_19
+B3[52]	buffer	wire_mult/mult/O_17	sp4_r_v_b_3
+B3[53]	buffer	wire_mult/mult/O_17	sp4_r_v_b_35
+B3[48]	buffer	wire_mult/mult/O_17	sp4_v_b_18
+B2[48]	buffer	wire_mult/mult/O_17	sp4_v_b_2
+B3[51]	buffer	wire_mult/mult/O_17	sp4_v_t_23
+B4[47]	buffer	wire_mult/mult/O_18	sp12_h_l_11
+B4[52]	buffer	wire_mult/mult/O_18	sp12_v_t_19
+B4[51]	buffer	wire_mult/mult/O_18	sp12_v_t_3
+B4[46]	buffer	wire_mult/mult/O_18	sp4_h_l_9
+B5[47]	buffer	wire_mult/mult/O_18	sp4_h_r_36
+B5[46]	buffer	wire_mult/mult/O_18	sp4_h_r_4
+B4[53]	buffer	wire_mult/mult/O_18	sp4_r_v_b_21
+B5[53]	buffer	wire_mult/mult/O_18	sp4_r_v_b_37
+B5[52]	buffer	wire_mult/mult/O_18	sp4_r_v_b_5
+B5[48]	buffer	wire_mult/mult/O_18	sp4_v_b_20
+B5[51]	buffer	wire_mult/mult/O_18	sp4_v_b_36
+B4[48]	buffer	wire_mult/mult/O_18	sp4_v_b_4
+B6[47]	buffer	wire_mult/mult/O_19	sp12_h_l_13
+B6[52]	buffer	wire_mult/mult/O_19	sp12_v_b_22
+B6[51]	buffer	wire_mult/mult/O_19	sp12_v_t_5
+B7[47]	buffer	wire_mult/mult/O_19	sp4_h_l_27
+B6[46]	buffer	wire_mult/mult/O_19	sp4_h_r_22
+B7[46]	buffer	wire_mult/mult/O_19	sp4_h_r_6
+B6[53]	buffer	wire_mult/mult/O_19	sp4_r_v_b_23
+B7[53]	buffer	wire_mult/mult/O_19	sp4_r_v_b_39
+B7[52]	buffer	wire_mult/mult/O_19	sp4_r_v_b_7
+B7[51]	buffer	wire_mult/mult/O_19	sp4_v_b_38
+B6[48]	buffer	wire_mult/mult/O_19	sp4_v_b_6
+B7[48]	buffer	wire_mult/mult/O_19	sp4_v_t_11
+B8[47]	buffer	wire_mult/mult/O_20	sp12_h_r_0
+B8[48]	buffer	wire_mult/mult/O_20	sp12_h_r_16
+B8[52]	buffer	wire_mult/mult/O_20	sp12_v_b_8
+B8[46]	buffer	wire_mult/mult/O_20	sp4_h_l_13
+B9[47]	buffer	wire_mult/mult/O_20	sp4_h_r_40
+B9[46]	buffer	wire_mult/mult/O_20	sp4_h_r_8
+B8[53]	buffer	wire_mult/mult/O_20	sp4_r_v_b_25
+B9[53]	buffer	wire_mult/mult/O_20	sp4_r_v_b_41
+B9[52]	buffer	wire_mult/mult/O_20	sp4_r_v_b_9
+B9[48]	buffer	wire_mult/mult/O_20	sp4_v_b_8
+B9[51]	buffer	wire_mult/mult/O_20	sp4_v_t_13
+B8[51]	buffer	wire_mult/mult/O_20	sp4_v_t_29
+B10[48]	buffer	wire_mult/mult/O_21	sp12_h_r_18
+B10[47]	buffer	wire_mult/mult/O_21	sp12_h_r_2
+B10[52]	buffer	wire_mult/mult/O_21	sp12_v_t_9
+B10[46]	buffer	wire_mult/mult/O_21	sp4_h_l_15
+B11[46]	buffer	wire_mult/mult/O_21	sp4_h_r_10
+B11[47]	buffer	wire_mult/mult/O_21	sp4_h_r_42
+B11[52]	buffer	wire_mult/mult/O_21	sp4_r_v_b_11
+B10[53]	buffer	wire_mult/mult/O_21	sp4_r_v_b_27
+B11[53]	buffer	wire_mult/mult/O_21	sp4_r_v_b_43
+B11[48]	buffer	wire_mult/mult/O_21	sp4_v_b_10
+B11[51]	buffer	wire_mult/mult/O_21	sp4_v_t_15
+B10[51]	buffer	wire_mult/mult/O_21	sp4_v_t_31
+B12[48]	buffer	wire_mult/mult/O_22	sp12_h_r_20
+B12[47]	buffer	wire_mult/mult/O_22	sp12_h_r_4
+B12[52]	buffer	wire_mult/mult/O_22	sp12_v_b_12
+B12[46]	buffer	wire_mult/mult/O_22	sp4_h_l_17
+B13[47]	buffer	wire_mult/mult/O_22	sp4_h_l_33
+B13[46]	buffer	wire_mult/mult/O_22	sp4_h_r_12
+B13[52]	buffer	wire_mult/mult/O_22	sp4_r_v_b_13
+B12[53]	buffer	wire_mult/mult/O_22	sp4_r_v_b_29
+B13[53]	buffer	wire_mult/mult/O_22	sp4_r_v_b_45
+B13[48]	buffer	wire_mult/mult/O_22	sp4_v_t_1
+B13[51]	buffer	wire_mult/mult/O_22	sp4_v_t_17
+B12[51]	buffer	wire_mult/mult/O_22	sp4_v_t_33
+B14[48]	buffer	wire_mult/mult/O_23	sp12_h_l_21
+B14[47]	buffer	wire_mult/mult/O_23	sp12_h_r_6
+B14[52]	buffer	wire_mult/mult/O_23	sp12_v_b_14
+B15[46]	buffer	wire_mult/mult/O_23	sp4_h_l_3
+B14[46]	buffer	wire_mult/mult/O_23	sp4_h_r_30
+B15[47]	buffer	wire_mult/mult/O_23	sp4_h_r_46
+B15[52]	buffer	wire_mult/mult/O_23	sp4_r_v_b_15
+B14[53]	buffer	wire_mult/mult/O_23	sp4_r_v_b_31
+B15[53]	buffer	wire_mult/mult/O_23	sp4_r_v_b_47
+B15[48]	buffer	wire_mult/mult/O_23	sp4_v_b_14
+B15[51]	buffer	wire_mult/mult/O_23	sp4_v_t_19
+B14[51]	buffer	wire_mult/mult/O_23	sp4_v_t_35
+!B12[3],B13[3]	routing	sp12_h_l_22	sp12_h_r_1
+!B8[3],B9[3]	routing	sp12_h_l_22	sp12_v_b_1
+!B14[3],B15[3]	routing	sp12_h_l_22	sp12_v_t_22
+!B4[3],B5[3]	routing	sp12_h_l_23	sp12_h_r_0
+!B0[3],B1[3]	routing	sp12_h_l_23	sp12_v_b_0
+!B6[3],B7[3]	routing	sp12_h_l_23	sp12_v_t_23
+B2[3],B3[3]	routing	sp12_h_r_0	sp12_h_l_23
+B0[3],B1[3]	routing	sp12_h_r_0	sp12_v_b_0
+B6[3],B7[3]	routing	sp12_h_r_0	sp12_v_t_23
+B8[3],B9[3]	routing	sp12_h_r_1	sp12_v_b_1
+B14[3],B15[3]	routing	sp12_h_r_1	sp12_v_t_22
+!B2[3],B3[3]	routing	sp12_v_b_0	sp12_h_l_23
+B4[3],B5[3]	routing	sp12_v_b_0	sp12_h_r_0
+B6[3],!B7[3]	routing	sp12_v_b_0	sp12_v_t_23
+B11[3]	routing	sp12_v_b_1	sp12_h_l_22
+B12[3],B13[3]	routing	sp12_v_b_1	sp12_h_r_1
+B14[3],!B15[3]	routing	sp12_v_b_1	sp12_v_t_22
+B10[3]	routing	sp12_v_t_22	sp12_h_l_22
+B12[3],!B13[3]	routing	sp12_v_t_22	sp12_h_r_1
+B8[3],!B9[3]	routing	sp12_v_t_22	sp12_v_b_1
+B2[3],!B3[3]	routing	sp12_v_t_23	sp12_h_l_23
+B4[3],!B5[3]	routing	sp12_v_t_23	sp12_h_r_0
+B0[3],!B1[3]	routing	sp12_v_t_23	sp12_v_b_0
+B1[8],B1[9],!B1[10]	routing	sp4_h_l_36	sp4_v_b_1
+B9[8],B9[9],B9[10]	routing	sp4_h_l_36	sp4_v_b_7
+B3[8],!B3[9],!B3[10]	routing	sp4_h_l_36	sp4_v_t_36
+!B10[4],B10[6],!B11[5]	routing	sp4_h_l_36	sp4_v_t_43
+B4[5],B5[4],!B5[6]	routing	sp4_h_l_37	sp4_h_r_3
+!B8[12],B9[11],B9[13]	routing	sp4_h_l_37	sp4_h_r_8
+B0[4],!B0[6],B1[5]	routing	sp4_h_l_37	sp4_v_b_0
+B8[4],B8[6],B9[5]	routing	sp4_h_l_37	sp4_v_b_6
+!B2[4],!B2[6],B3[5]	routing	sp4_h_l_37	sp4_v_t_37
+B6[11],!B6[13],!B7[12]	routing	sp4_h_l_37	sp4_v_t_40
+!B4[5],!B5[4],B5[6]	routing	sp4_h_l_38	sp4_h_r_3
+B8[5],B9[4],!B9[6]	routing	sp4_h_l_38	sp4_h_r_6
+B4[4],!B4[6],B5[5]	routing	sp4_h_l_38	sp4_v_b_3
+B12[4],B12[6],B13[5]	routing	sp4_h_l_38	sp4_v_b_9
+!B6[4],!B6[6],B7[5]	routing	sp4_h_l_38	sp4_v_t_38
+B10[11],!B10[13],!B11[12]	routing	sp4_h_l_38	sp4_v_t_45
+B12[8],!B12[9],B12[10]	routing	sp4_h_l_39	sp4_h_r_10
+!B0[12],B1[11],!B1[13]	routing	sp4_h_l_39	sp4_h_r_2
+!B0[11],B0[13],B1[12]	routing	sp4_h_l_39	sp4_v_b_2
+B8[11],B8[13],B9[12]	routing	sp4_h_l_39	sp4_v_b_8
+!B2[11],!B2[13],B3[12]	routing	sp4_h_l_39	sp4_v_t_39
+!B11[8],!B11[9],B11[10]	routing	sp4_h_l_39	sp4_v_t_42
+B0[8],!B0[9],B0[10]	routing	sp4_h_l_40	sp4_h_r_1
+!B4[12],B5[11],!B5[13]	routing	sp4_h_l_40	sp4_h_r_5
+B8[12],!B9[11],B9[13]	routing	sp4_h_l_40	sp4_h_r_8
+B12[11],B12[13],B13[12]	routing	sp4_h_l_40	sp4_v_b_11
+!B4[11],B4[13],B5[12]	routing	sp4_h_l_40	sp4_v_b_5
+!B6[11],!B6[13],B7[12]	routing	sp4_h_l_40	sp4_v_t_40
+!B15[8],!B15[9],B15[10]	routing	sp4_h_l_40	sp4_v_t_47
+B13[8],B13[9],B13[10]	routing	sp4_h_l_41	sp4_v_b_10
+B5[8],B5[9],!B5[10]	routing	sp4_h_l_41	sp4_v_b_4
+B7[8],!B7[9],!B7[10]	routing	sp4_h_l_41	sp4_v_t_41
+!B14[4],B14[6],!B15[5]	routing	sp4_h_l_41	sp4_v_t_44
+B1[8],B1[9],B1[10]	routing	sp4_h_l_42	sp4_v_b_1
+B9[8],B9[9],!B9[10]	routing	sp4_h_l_42	sp4_v_b_7
+!B2[4],B2[6],!B3[5]	routing	sp4_h_l_42	sp4_v_t_37
+B11[8],!B11[9],!B11[10]	routing	sp4_h_l_42	sp4_v_t_42
+!B0[12],B1[11],B1[13]	routing	sp4_h_l_43	sp4_h_r_2
+B0[4],B0[6],B1[5]	routing	sp4_h_l_43	sp4_v_b_0
+B8[4],!B8[6],B9[5]	routing	sp4_h_l_43	sp4_v_b_6
+!B10[4],!B10[6],B11[5]	routing	sp4_h_l_43	sp4_v_t_43
+B14[11],!B14[13],!B15[12]	routing	sp4_h_l_43	sp4_v_t_46
+!B4[12],B5[11],B5[13]	routing	sp4_h_l_44	sp4_h_r_5
+!B12[5],!B13[4],B13[6]	routing	sp4_h_l_44	sp4_h_r_9
+B4[4],B4[6],B5[5]	routing	sp4_h_l_44	sp4_v_b_3
+B12[4],!B12[6],B13[5]	routing	sp4_h_l_44	sp4_v_b_9
+B2[11],!B2[13],!B3[12]	routing	sp4_h_l_44	sp4_v_t_39
+!B14[4],!B14[6],B15[5]	routing	sp4_h_l_44	sp4_v_t_44
+B12[12],!B13[11],B13[13]	routing	sp4_h_l_45	sp4_h_r_11
+B4[8],!B4[9],B4[10]	routing	sp4_h_l_45	sp4_h_r_4
+B0[11],B0[13],B1[12]	routing	sp4_h_l_45	sp4_v_b_2
+!B8[11],B8[13],B9[12]	routing	sp4_h_l_45	sp4_v_b_8
+!B3[8],!B3[9],B3[10]	routing	sp4_h_l_45	sp4_v_t_36
+!B10[11],!B10[13],B11[12]	routing	sp4_h_l_45	sp4_v_t_45
+!B12[12],B13[11],!B13[13]	routing	sp4_h_l_46	sp4_h_r_11
+B0[12],!B1[11],B1[13]	routing	sp4_h_l_46	sp4_h_r_2
+!B12[11],B12[13],B13[12]	routing	sp4_h_l_46	sp4_v_b_11
+B4[11],B4[13],B5[12]	routing	sp4_h_l_46	sp4_v_b_5
+!B7[8],!B7[9],B7[10]	routing	sp4_h_l_46	sp4_v_t_41
+!B14[11],!B14[13],B15[12]	routing	sp4_h_l_46	sp4_v_t_46
+B12[8],!B12[9],!B12[10]	routing	sp4_h_l_47	sp4_h_r_10
+B13[8],B13[9],!B13[10]	routing	sp4_h_l_47	sp4_v_b_10
+B5[8],B5[9],B5[10]	routing	sp4_h_l_47	sp4_v_b_4
+!B6[4],B6[6],!B7[5]	routing	sp4_h_l_47	sp4_v_t_38
+B15[8],!B15[9],!B15[10]	routing	sp4_h_l_47	sp4_v_t_47
+!B2[5],!B3[4],B3[6]	routing	sp4_h_r_0	sp4_h_l_37
+B6[5],B7[4],!B7[6]	routing	sp4_h_r_0	sp4_h_l_38
+!B10[12],B11[11],B11[13]	routing	sp4_h_r_0	sp4_h_l_45
+!B0[4],!B0[6],B1[5]	routing	sp4_h_r_0	sp4_v_b_0
+B4[11],!B4[13],!B5[12]	routing	sp4_h_r_0	sp4_v_b_5
+B2[4],!B2[6],B3[5]	routing	sp4_h_r_0	sp4_v_t_37
+B10[4],B10[6],B11[5]	routing	sp4_h_r_0	sp4_v_t_43
+B1[8],!B1[9],!B1[10]	routing	sp4_h_r_1	sp4_v_b_1
+!B8[4],B8[6],!B9[5]	routing	sp4_h_r_1	sp4_v_b_6
+B3[8],B3[9],!B3[10]	routing	sp4_h_r_1	sp4_v_t_36
+B11[8],B11[9],B11[10]	routing	sp4_h_r_1	sp4_v_t_42
+!B2[8],B2[9],B2[10]	routing	sp4_h_r_10	sp4_h_l_36
+!B10[5],B11[4],B11[6]	routing	sp4_h_r_10	sp4_h_l_43
+B14[8],!B14[9],!B14[10]	routing	sp4_h_r_10	sp4_h_l_47
+B13[8],!B13[9],!B13[10]	routing	sp4_h_r_10	sp4_v_b_10
+!B4[4],B4[6],!B5[5]	routing	sp4_h_r_10	sp4_v_b_3
+B7[8],B7[9],B7[10]	routing	sp4_h_r_10	sp4_v_t_41
+B15[8],B15[9],!B15[10]	routing	sp4_h_r_10	sp4_v_t_47
+!B12[11],!B12[13],B13[12]	routing	sp4_h_r_11	sp4_v_b_11
+!B5[8],!B5[9],B5[10]	routing	sp4_h_r_11	sp4_v_b_4
+B6[11],B6[13],B7[12]	routing	sp4_h_r_11	sp4_v_t_40
+!B14[11],B14[13],B15[12]	routing	sp4_h_r_11	sp4_v_t_46
+!B2[12],B3[11],!B3[13]	routing	sp4_h_r_2	sp4_h_l_39
+B6[12],!B7[11],B7[13]	routing	sp4_h_r_2	sp4_h_l_40
+B14[8],!B14[9],B14[10]	routing	sp4_h_r_2	sp4_h_l_47
+!B0[11],!B0[13],B1[12]	routing	sp4_h_r_2	sp4_v_b_2
+!B9[8],!B9[9],B9[10]	routing	sp4_h_r_2	sp4_v_b_7
+!B2[11],B2[13],B3[12]	routing	sp4_h_r_2	sp4_v_t_39
+B10[11],B10[13],B11[12]	routing	sp4_h_r_2	sp4_v_t_45
+B10[5],B11[4],!B11[6]	routing	sp4_h_r_3	sp4_h_l_43
+!B4[4],!B4[6],B5[5]	routing	sp4_h_r_3	sp4_v_b_3
+B8[11],!B8[13],!B9[12]	routing	sp4_h_r_3	sp4_v_b_8
+B6[4],!B6[6],B7[5]	routing	sp4_h_r_3	sp4_v_t_38
+B14[4],B14[6],B15[5]	routing	sp4_h_r_3	sp4_v_t_44
+!B2[5],B3[4],B3[6]	routing	sp4_h_r_4	sp4_h_l_37
+B6[8],!B6[9],!B6[10]	routing	sp4_h_r_4	sp4_h_l_41
+!B10[8],B10[9],B10[10]	routing	sp4_h_r_4	sp4_h_l_42
+B5[8],!B5[9],!B5[10]	routing	sp4_h_r_4	sp4_v_b_4
+!B12[4],B12[6],!B13[5]	routing	sp4_h_r_4	sp4_v_b_9
+B7[8],B7[9],!B7[10]	routing	sp4_h_r_4	sp4_v_t_41
+B15[8],B15[9],B15[10]	routing	sp4_h_r_4	sp4_v_t_47
+!B13[8],!B13[9],B13[10]	routing	sp4_h_r_5	sp4_v_b_10
+!B4[11],!B4[13],B5[12]	routing	sp4_h_r_5	sp4_v_b_5
+!B6[11],B6[13],B7[12]	routing	sp4_h_r_5	sp4_v_t_40
+B14[11],B14[13],B15[12]	routing	sp4_h_r_5	sp4_v_t_46
+!B2[12],B3[11],B3[13]	routing	sp4_h_r_6	sp4_h_l_39
+!B10[5],!B11[4],B11[6]	routing	sp4_h_r_6	sp4_h_l_43
+B14[5],B15[4],!B15[6]	routing	sp4_h_r_6	sp4_h_l_44
+B12[11],!B12[13],!B13[12]	routing	sp4_h_r_6	sp4_v_b_11
+!B8[4],!B8[6],B9[5]	routing	sp4_h_r_6	sp4_v_b_6
+B2[4],B2[6],B3[5]	routing	sp4_h_r_6	sp4_v_t_37
+B10[4],!B10[6],B11[5]	routing	sp4_h_r_6	sp4_v_t_43
+!B0[4],B0[6],!B1[5]	routing	sp4_h_r_7	sp4_v_b_0
+B9[8],!B9[9],!B9[10]	routing	sp4_h_r_7	sp4_v_b_7
+B3[8],B3[9],B3[10]	routing	sp4_h_r_7	sp4_v_t_36
+B11[8],B11[9],!B11[10]	routing	sp4_h_r_7	sp4_v_t_42
+B6[8],!B6[9],B6[10]	routing	sp4_h_r_8	sp4_h_l_41
+!B10[12],B11[11],!B11[13]	routing	sp4_h_r_8	sp4_h_l_45
+B14[12],!B15[11],B15[13]	routing	sp4_h_r_8	sp4_h_l_46
+!B1[8],!B1[9],B1[10]	routing	sp4_h_r_8	sp4_v_b_1
+!B8[11],!B8[13],B9[12]	routing	sp4_h_r_8	sp4_v_b_8
+B2[11],B2[13],B3[12]	routing	sp4_h_r_8	sp4_v_t_39
+!B10[11],B10[13],B11[12]	routing	sp4_h_r_8	sp4_v_t_45
+!B6[12],B7[11],B7[13]	routing	sp4_h_r_9	sp4_h_l_40
+B0[11],!B0[13],!B1[12]	routing	sp4_h_r_9	sp4_v_b_2
+!B12[4],!B12[6],B13[5]	routing	sp4_h_r_9	sp4_v_b_9
+B6[4],B6[6],B7[5]	routing	sp4_h_r_9	sp4_v_t_38
+B14[4],!B14[6],B15[5]	routing	sp4_h_r_9	sp4_v_t_44
+B2[5],!B3[4],!B3[6]	routing	sp4_v_b_0	sp4_h_l_37
+!B6[12],!B7[11],B7[13]	routing	sp4_v_b_0	sp4_h_l_40
+B0[5],!B1[4],B1[6]	routing	sp4_v_b_0	sp4_h_r_0
+B8[5],B9[4],B9[6]	routing	sp4_v_b_0	sp4_h_r_6
+B2[4],!B2[6],!B3[5]	routing	sp4_v_b_0	sp4_v_t_37
+!B6[4],B6[6],B7[5]	routing	sp4_v_b_0	sp4_v_t_38
+B10[11],B10[13],!B11[12]	routing	sp4_v_b_0	sp4_v_t_45
+!B2[8],B2[9],!B2[10]	routing	sp4_v_b_1	sp4_h_l_36
+!B10[5],B11[4],!B11[6]	routing	sp4_v_b_1	sp4_h_l_43
+B0[8],B0[9],!B0[10]	routing	sp4_v_b_1	sp4_h_r_1
+B8[8],B8[9],B8[10]	routing	sp4_v_b_1	sp4_h_r_7
+!B3[8],B3[9],!B3[10]	routing	sp4_v_b_1	sp4_v_t_36
+B7[8],!B7[9],B7[10]	routing	sp4_v_b_1	sp4_v_t_41
+B14[4],B14[6],!B15[5]	routing	sp4_v_b_1	sp4_v_t_44
+!B6[5],B7[4],!B7[6]	routing	sp4_v_b_10	sp4_h_l_38
+!B14[8],B14[9],!B14[10]	routing	sp4_v_b_10	sp4_h_l_47
+B12[8],B12[9],!B12[10]	routing	sp4_v_b_10	sp4_h_r_10
+B4[8],B4[9],B4[10]	routing	sp4_v_b_10	sp4_h_r_4
+B3[8],!B3[9],B3[10]	routing	sp4_v_b_10	sp4_v_t_36
+B10[4],B10[6],!B11[5]	routing	sp4_v_b_10	sp4_v_t_43
+!B15[8],B15[9],!B15[10]	routing	sp4_v_b_10	sp4_v_t_47
+!B6[8],!B6[9],B6[10]	routing	sp4_v_b_11	sp4_h_l_41
+B14[12],!B15[11],!B15[13]	routing	sp4_v_b_11	sp4_h_l_46
+B12[12],B13[11],!B13[13]	routing	sp4_v_b_11	sp4_h_r_11
+B4[12],B5[11],B5[13]	routing	sp4_v_b_11	sp4_h_r_5
+B2[11],!B2[13],B3[12]	routing	sp4_v_b_11	sp4_v_t_39
+!B11[8],B11[9],B11[10]	routing	sp4_v_b_11	sp4_v_t_42
+!B14[11],B14[13],!B15[12]	routing	sp4_v_b_11	sp4_v_t_46
+B2[12],!B3[11],!B3[13]	routing	sp4_v_b_2	sp4_h_l_39
+!B10[8],!B10[9],B10[10]	routing	sp4_v_b_2	sp4_h_l_42
+B0[12],B1[11],!B1[13]	routing	sp4_v_b_2	sp4_h_r_2
+B8[12],B9[11],B9[13]	routing	sp4_v_b_2	sp4_h_r_8
+!B2[11],B2[13],!B3[12]	routing	sp4_v_b_2	sp4_v_t_39
+B6[11],!B6[13],B7[12]	routing	sp4_v_b_2	sp4_v_t_40
+!B15[8],B15[9],B15[10]	routing	sp4_v_b_2	sp4_v_t_47
+B6[5],!B7[4],!B7[6]	routing	sp4_v_b_3	sp4_h_l_38
+!B10[12],!B11[11],B11[13]	routing	sp4_v_b_3	sp4_h_l_45
+B4[5],!B5[4],B5[6]	routing	sp4_v_b_3	sp4_h_r_3
+B12[5],B13[4],B13[6]	routing	sp4_v_b_3	sp4_h_r_9
+B6[4],!B6[6],!B7[5]	routing	sp4_v_b_3	sp4_v_t_38
+!B10[4],B10[6],B11[5]	routing	sp4_v_b_3	sp4_v_t_43
+B14[11],B14[13],!B15[12]	routing	sp4_v_b_3	sp4_v_t_46
+!B6[8],B6[9],!B6[10]	routing	sp4_v_b_4	sp4_h_l_41
+!B14[5],B15[4],!B15[6]	routing	sp4_v_b_4	sp4_h_l_44
+B12[8],B12[9],B12[10]	routing	sp4_v_b_4	sp4_h_r_10
+B4[8],B4[9],!B4[10]	routing	sp4_v_b_4	sp4_h_r_4
+B2[4],B2[6],!B3[5]	routing	sp4_v_b_4	sp4_v_t_37
+!B7[8],B7[9],!B7[10]	routing	sp4_v_b_4	sp4_v_t_41
+B11[8],!B11[9],B11[10]	routing	sp4_v_b_4	sp4_v_t_42
+B6[12],!B7[11],!B7[13]	routing	sp4_v_b_5	sp4_h_l_40
+!B14[8],!B14[9],B14[10]	routing	sp4_v_b_5	sp4_h_l_47
+B12[12],B13[11],B13[13]	routing	sp4_v_b_5	sp4_h_r_11
+B4[12],B5[11],!B5[13]	routing	sp4_v_b_5	sp4_h_r_5
+!B3[8],B3[9],B3[10]	routing	sp4_v_b_5	sp4_v_t_36
+!B6[11],B6[13],!B7[12]	routing	sp4_v_b_5	sp4_v_t_40
+B10[11],!B10[13],B11[12]	routing	sp4_v_b_5	sp4_v_t_45
+B10[5],!B11[4],!B11[6]	routing	sp4_v_b_6	sp4_h_l_43
+!B14[12],!B15[11],B15[13]	routing	sp4_v_b_6	sp4_h_l_46
+B0[5],B1[4],B1[6]	routing	sp4_v_b_6	sp4_h_r_0
+B8[5],!B9[4],B9[6]	routing	sp4_v_b_6	sp4_h_r_6
+B2[11],B2[13],!B3[12]	routing	sp4_v_b_6	sp4_v_t_39
+B10[4],!B10[6],!B11[5]	routing	sp4_v_b_6	sp4_v_t_43
+!B14[4],B14[6],B15[5]	routing	sp4_v_b_6	sp4_v_t_44
+!B2[5],B3[4],!B3[6]	routing	sp4_v_b_7	sp4_h_l_37
+!B10[8],B10[9],!B10[10]	routing	sp4_v_b_7	sp4_h_l_42
+B0[8],B0[9],B0[10]	routing	sp4_v_b_7	sp4_h_r_1
+B8[8],B8[9],!B8[10]	routing	sp4_v_b_7	sp4_h_r_7
+B6[4],B6[6],!B7[5]	routing	sp4_v_b_7	sp4_v_t_38
+!B11[8],B11[9],!B11[10]	routing	sp4_v_b_7	sp4_v_t_42
+B15[8],!B15[9],B15[10]	routing	sp4_v_b_7	sp4_v_t_47
+!B2[8],!B2[9],B2[10]	routing	sp4_v_b_8	sp4_h_l_36
+B10[12],!B11[11],!B11[13]	routing	sp4_v_b_8	sp4_h_l_45
+B0[12],B1[11],B1[13]	routing	sp4_v_b_8	sp4_h_r_2
+B8[12],B9[11],!B9[13]	routing	sp4_v_b_8	sp4_h_r_8
+!B7[8],B7[9],B7[10]	routing	sp4_v_b_8	sp4_v_t_41
+!B10[11],B10[13],!B11[12]	routing	sp4_v_b_8	sp4_v_t_45
+B14[11],!B14[13],B15[12]	routing	sp4_v_b_8	sp4_v_t_46
+!B2[12],!B3[11],B3[13]	routing	sp4_v_b_9	sp4_h_l_39
+B14[5],!B15[4],!B15[6]	routing	sp4_v_b_9	sp4_h_l_44
+B4[5],B5[4],B5[6]	routing	sp4_v_b_9	sp4_h_r_3
+B12[5],!B13[4],B13[6]	routing	sp4_v_b_9	sp4_h_r_9
+!B2[4],B2[6],B3[5]	routing	sp4_v_b_9	sp4_v_t_37
+B6[11],B6[13],!B7[12]	routing	sp4_v_b_9	sp4_v_t_40
+B14[4],!B14[6],!B15[5]	routing	sp4_v_b_9	sp4_v_t_44
+B2[8],B2[9],!B2[10]	routing	sp4_v_t_36	sp4_h_l_36
+B10[8],B10[9],B10[10]	routing	sp4_v_t_36	sp4_h_l_42
+!B0[8],B0[9],!B0[10]	routing	sp4_v_t_36	sp4_h_r_1
+!B8[5],B9[4],!B9[6]	routing	sp4_v_t_36	sp4_h_r_6
+!B1[8],B1[9],!B1[10]	routing	sp4_v_t_36	sp4_v_b_1
+B5[8],!B5[9],B5[10]	routing	sp4_v_t_36	sp4_v_b_4
+B12[4],B12[6],!B13[5]	routing	sp4_v_t_36	sp4_v_b_9
+B2[5],!B3[4],B3[6]	routing	sp4_v_t_37	sp4_h_l_37
+B10[5],B11[4],B11[6]	routing	sp4_v_t_37	sp4_h_l_43
+B0[5],!B1[4],!B1[6]	routing	sp4_v_t_37	sp4_h_r_0
+!B4[12],!B5[11],B5[13]	routing	sp4_v_t_37	sp4_h_r_5
+B0[4],!B0[6],!B1[5]	routing	sp4_v_t_37	sp4_v_b_0
+!B4[4],B4[6],B5[5]	routing	sp4_v_t_37	sp4_v_b_3
+B8[11],B8[13],!B9[12]	routing	sp4_v_t_37	sp4_v_b_8
+B6[5],!B7[4],B7[6]	routing	sp4_v_t_38	sp4_h_l_38
+B14[5],B15[4],B15[6]	routing	sp4_v_t_38	sp4_h_l_44
+B4[5],!B5[4],!B5[6]	routing	sp4_v_t_38	sp4_h_r_3
+!B8[12],!B9[11],B9[13]	routing	sp4_v_t_38	sp4_h_r_8
+B12[11],B12[13],!B13[12]	routing	sp4_v_t_38	sp4_v_b_11
+B4[4],!B4[6],!B5[5]	routing	sp4_v_t_38	sp4_v_b_3
+!B8[4],B8[6],B9[5]	routing	sp4_v_t_38	sp4_v_b_6
+B2[12],B3[11],!B3[13]	routing	sp4_v_t_39	sp4_h_l_39
+B10[12],B11[11],B11[13]	routing	sp4_v_t_39	sp4_h_l_45
+B0[12],!B1[11],!B1[13]	routing	sp4_v_t_39	sp4_h_r_2
+!B8[8],!B8[9],B8[10]	routing	sp4_v_t_39	sp4_h_r_7
+!B13[8],B13[9],B13[10]	routing	sp4_v_t_39	sp4_v_b_10
+!B0[11],B0[13],!B1[12]	routing	sp4_v_t_39	sp4_v_b_2
+B4[11],!B4[13],B5[12]	routing	sp4_v_t_39	sp4_v_b_5
+B6[12],B7[11],!B7[13]	routing	sp4_v_t_40	sp4_h_l_40
+B14[12],B15[11],B15[13]	routing	sp4_v_t_40	sp4_h_l_46
+!B12[8],!B12[9],B12[10]	routing	sp4_v_t_40	sp4_h_r_10
+B4[12],!B5[11],!B5[13]	routing	sp4_v_t_40	sp4_h_r_5
+!B1[8],B1[9],B1[10]	routing	sp4_v_t_40	sp4_v_b_1
+!B4[11],B4[13],!B5[12]	routing	sp4_v_t_40	sp4_v_b_5
+B8[11],!B8[13],B9[12]	routing	sp4_v_t_40	sp4_v_b_8
+B6[8],B6[9],!B6[10]	routing	sp4_v_t_41	sp4_h_l_41
+B14[8],B14[9],B14[10]	routing	sp4_v_t_41	sp4_h_l_47
+!B4[8],B4[9],!B4[10]	routing	sp4_v_t_41	sp4_h_r_4
+!B12[5],B13[4],!B13[6]	routing	sp4_v_t_41	sp4_h_r_9
+B0[4],B0[6],!B1[5]	routing	sp4_v_t_41	sp4_v_b_0
+!B5[8],B5[9],!B5[10]	routing	sp4_v_t_41	sp4_v_b_4
+B9[8],!B9[9],B9[10]	routing	sp4_v_t_41	sp4_v_b_7
+B2[8],B2[9],B2[10]	routing	sp4_v_t_42	sp4_h_l_36
+B10[8],B10[9],!B10[10]	routing	sp4_v_t_42	sp4_h_l_42
+!B0[5],B1[4],!B1[6]	routing	sp4_v_t_42	sp4_h_r_0
+!B8[8],B8[9],!B8[10]	routing	sp4_v_t_42	sp4_h_r_7
+B13[8],!B13[9],B13[10]	routing	sp4_v_t_42	sp4_v_b_10
+B4[4],B4[6],!B5[5]	routing	sp4_v_t_42	sp4_v_b_3
+!B9[8],B9[9],!B9[10]	routing	sp4_v_t_42	sp4_v_b_7
+B2[5],B3[4],B3[6]	routing	sp4_v_t_43	sp4_h_l_37
+B10[5],!B11[4],B11[6]	routing	sp4_v_t_43	sp4_h_l_43
+!B12[12],!B13[11],B13[13]	routing	sp4_v_t_43	sp4_h_r_11
+B8[5],!B9[4],!B9[6]	routing	sp4_v_t_43	sp4_h_r_6
+B0[11],B0[13],!B1[12]	routing	sp4_v_t_43	sp4_v_b_2
+B8[4],!B8[6],!B9[5]	routing	sp4_v_t_43	sp4_v_b_6
+!B12[4],B12[6],B13[5]	routing	sp4_v_t_43	sp4_v_b_9
+B6[5],B7[4],B7[6]	routing	sp4_v_t_44	sp4_h_l_38
+B14[5],!B15[4],B15[6]	routing	sp4_v_t_44	sp4_h_l_44
+!B0[12],!B1[11],B1[13]	routing	sp4_v_t_44	sp4_h_r_2
+B12[5],!B13[4],!B13[6]	routing	sp4_v_t_44	sp4_h_r_9
+!B0[4],B0[6],B1[5]	routing	sp4_v_t_44	sp4_v_b_0
+B4[11],B4[13],!B5[12]	routing	sp4_v_t_44	sp4_v_b_5
+B12[4],!B12[6],!B13[5]	routing	sp4_v_t_44	sp4_v_b_9
+B2[12],B3[11],B3[13]	routing	sp4_v_t_45	sp4_h_l_39
+B10[12],B11[11],!B11[13]	routing	sp4_v_t_45	sp4_h_l_45
+!B0[8],!B0[9],B0[10]	routing	sp4_v_t_45	sp4_h_r_1
+B8[12],!B9[11],!B9[13]	routing	sp4_v_t_45	sp4_h_r_8
+B12[11],!B12[13],B13[12]	routing	sp4_v_t_45	sp4_v_b_11
+!B5[8],B5[9],B5[10]	routing	sp4_v_t_45	sp4_v_b_4
+!B8[11],B8[13],!B9[12]	routing	sp4_v_t_45	sp4_v_b_8
+B6[12],B7[11],B7[13]	routing	sp4_v_t_46	sp4_h_l_40
+B14[12],B15[11],!B15[13]	routing	sp4_v_t_46	sp4_h_l_46
+B12[12],!B13[11],!B13[13]	routing	sp4_v_t_46	sp4_h_r_11
+!B4[8],!B4[9],B4[10]	routing	sp4_v_t_46	sp4_h_r_4
+!B12[11],B12[13],!B13[12]	routing	sp4_v_t_46	sp4_v_b_11
+B0[11],!B0[13],B1[12]	routing	sp4_v_t_46	sp4_v_b_2
+!B9[8],B9[9],B9[10]	routing	sp4_v_t_46	sp4_v_b_7
+B6[8],B6[9],B6[10]	routing	sp4_v_t_47	sp4_h_l_41
+B14[8],B14[9],!B14[10]	routing	sp4_v_t_47	sp4_h_l_47
+!B12[8],B12[9],!B12[10]	routing	sp4_v_t_47	sp4_h_r_10
+!B4[5],B5[4],!B5[6]	routing	sp4_v_t_47	sp4_h_r_3
+B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
+!B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
+B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
+"""
+database_dsp3_5k_txt = """
+B0[50]	Cascade	MULT3_LC00_inmux02_5
+B2[50]	Cascade	MULT3_LC01_inmux02_5
+B4[50]	Cascade	MULT3_LC02_inmux02_5
+B6[50]	Cascade	MULT3_LC03_inmux02_5
+B8[50]	Cascade	MULT3_LC04_inmux02_5
+B10[50]	Cascade	MULT3_LC05_inmux02_5
+B12[50]	Cascade	MULT3_LC06_inmux02_5
+B14[50]	Cascade	MULT3_LC07_inmux02_5
+B9[7]	ColBufCtrl	8k_glb_netwk_0
+B8[7]	ColBufCtrl	8k_glb_netwk_1
+B11[7]	ColBufCtrl	8k_glb_netwk_2
+B10[7]	ColBufCtrl	8k_glb_netwk_3
+B13[7]	ColBufCtrl	8k_glb_netwk_4
+B12[7]	ColBufCtrl	8k_glb_netwk_5
+B15[7]	ColBufCtrl	8k_glb_netwk_6
+B14[7]	ColBufCtrl	8k_glb_netwk_7
+B1[7]	IpConfig	CBIT_0
+B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43]	LC_0
+B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43]	LC_1
+B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43]	LC_2
+B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43]	LC_3
+B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43]	LC_4
+B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43]	LC_5
+B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43]	LC_6
+B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43]	LC_7
+B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	bnl_op_0	lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	bnl_op_0	lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	bnl_op_1	lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	bnl_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	bnl_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	bnl_op_2	lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	bnl_op_3	lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	bnl_op_3	lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	bnl_op_4	lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	bnl_op_4	lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	bnl_op_5	lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	bnl_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	bnl_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	bnl_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	bnl_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	bnl_op_7	lc_trk_g3_7
+B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	bnr_op_0	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	bnr_op_1	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	bnr_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	bnr_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	bnr_op_2	lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	bnr_op_3	lc_trk_g0_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	bnr_op_4	lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	bnr_op_4	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	bnr_op_5	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	bnr_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	bnr_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	bnr_op_6	lc_trk_g1_6
+B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	bnr_op_7	lc_trk_g1_7
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17]	buffer	glb2local_0	lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18]	buffer	glb2local_1	lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25]	buffer	glb2local_2	lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21]	buffer	glb2local_3	lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1]	buffer	glb_netwk_0	glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_0	glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_0	glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_0	glb2local_3
+!B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_0	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_1	glb2local_0
+!B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_1	glb2local_1
+!B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_1	glb2local_2
+!B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_1	glb2local_3
+B8[0],B8[1],!B9[0],!B9[1]	buffer	glb_netwk_2	glb2local_1
+B10[0],B10[1],!B11[0],!B11[1]	buffer	glb_netwk_2	glb2local_2
+B12[0],B12[1],!B13[0],!B13[1]	buffer	glb_netwk_2	glb2local_3
+!B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_2	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],!B7[1]	buffer	glb_netwk_3	glb2local_0
+B8[0],B8[1],B9[0],!B9[1]	buffer	glb_netwk_3	glb2local_1
+B10[0],B10[1],B11[0],!B11[1]	buffer	glb_netwk_3	glb2local_2
+B12[0],B12[1],B13[0],!B13[1]	buffer	glb_netwk_3	glb2local_3
+!B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_4	glb2local_0
+!B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_4	glb2local_1
+!B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_4	glb2local_2
+!B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_4	glb2local_3
+B14[0],B14[1],!B15[0],!B15[1]	buffer	glb_netwk_4	wire_mult/lc_7/s_r
+!B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_5	glb2local_0
+!B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_5	glb2local_1
+!B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_5	glb2local_2
+!B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_5	glb2local_3
+B6[0],B6[1],!B7[0],B7[1]	buffer	glb_netwk_6	glb2local_0
+B8[0],B8[1],!B9[0],B9[1]	buffer	glb_netwk_6	glb2local_1
+B10[0],B10[1],!B11[0],B11[1]	buffer	glb_netwk_6	glb2local_2
+B12[0],B12[1],!B13[0],B13[1]	buffer	glb_netwk_6	glb2local_3
+B14[0],B14[1],B15[0],!B15[1]	buffer	glb_netwk_6	wire_mult/lc_7/s_r
+B6[0],B6[1],B7[0],B7[1]	buffer	glb_netwk_7	glb2local_0
+B8[0],B8[1],B9[0],B9[1]	buffer	glb_netwk_7	glb2local_1
+B10[0],B10[1],B11[0],B11[1]	buffer	glb_netwk_7	glb2local_2
+B12[0],B12[1],B13[0],B13[1]	buffer	glb_netwk_7	glb2local_3
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_0	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g0_0	wire_mult/lc_1/in_1
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_0	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g0_0	wire_mult/lc_3/in_1
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g0_0	wire_mult/lc_5/in_1
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g0_0	wire_mult/lc_7/in_1
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g0_1	wire_mult/lc_0/in_1
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_1	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g0_1	wire_mult/lc_2/in_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_1	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g0_1	wire_mult/lc_4/in_1
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g0_1	wire_mult/lc_6/in_1
+!B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_2	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_2	wire_mult/lc_1/in_3
+!B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_2	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_2	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_2	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_2	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_3	wire_mult/lc_0/in_3
+!B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_3	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_3	wire_mult/lc_2/in_3
+!B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_3	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_3	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_4	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],!B3[31]	buffer	lc_trk_g0_4	wire_mult/lc_1/in_3
+B4[26],!B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_4	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],!B7[31]	buffer	lc_trk_g0_4	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],!B11[31]	buffer	lc_trk_g0_4	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],!B15[31]	buffer	lc_trk_g0_4	wire_mult/lc_7/in_3
+!B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g0_4	wire_mult/lc_7/s_r
+!B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],!B1[31]	buffer	lc_trk_g0_5	wire_mult/lc_0/in_3
+B2[26],!B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_5	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],!B5[31]	buffer	lc_trk_g0_5	wire_mult/lc_2/in_3
+B6[26],!B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_5	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],!B9[31]	buffer	lc_trk_g0_5	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],!B13[31]	buffer	lc_trk_g0_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],!B1[28],B1[29]	buffer	lc_trk_g0_6	wire_mult/lc_0/in_0
+!B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],!B2[34],B3[31]	buffer	lc_trk_g0_6	wire_mult/lc_1/in_3
+B4[26],B5[26],!B5[27],!B5[28],B5[29]	buffer	lc_trk_g0_6	wire_mult/lc_2/in_0
+!B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],!B6[34],B7[31]	buffer	lc_trk_g0_6	wire_mult/lc_3/in_3
+!B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],!B10[34],B11[31]	buffer	lc_trk_g0_6	wire_mult/lc_5/in_3
+!B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],!B14[34],B15[31]	buffer	lc_trk_g0_6	wire_mult/lc_7/in_3
+!B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],!B0[34],B1[31]	buffer	lc_trk_g0_7	wire_mult/lc_0/in_3
+B2[26],B3[26],!B3[27],!B3[28],B3[29]	buffer	lc_trk_g0_7	wire_mult/lc_1/in_0
+!B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],!B4[34],B5[31]	buffer	lc_trk_g0_7	wire_mult/lc_2/in_3
+B6[26],B7[26],!B7[27],!B7[28],B7[29]	buffer	lc_trk_g0_7	wire_mult/lc_3/in_0
+!B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],!B8[34],B9[31]	buffer	lc_trk_g0_7	wire_mult/lc_4/in_3
+!B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],!B12[34],B13[31]	buffer	lc_trk_g0_7	wire_mult/lc_6/in_3
+B0[27],!B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_0	wire_mult/lc_0/in_3
+!B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_0	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_0	wire_mult/lc_2/in_3
+!B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_0	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_0	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_1	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_1	wire_mult/lc_1/in_3
+!B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_1	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_1	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_1	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_1	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_2	wire_mult/lc_0/in_3
+!B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_2	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_2	wire_mult/lc_2/in_3
+!B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_2	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_2	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_3	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_3	wire_mult/lc_1/in_3
+!B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_3	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_3	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_3	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_3	wire_mult/lc_7/in_3
+B0[27],!B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],!B1[31]	buffer	lc_trk_g1_4	wire_mult/lc_0/in_3
+B2[26],!B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_4	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],!B5[31]	buffer	lc_trk_g1_4	wire_mult/lc_2/in_3
+B6[26],!B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_4	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],!B9[31]	buffer	lc_trk_g1_4	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],!B13[31]	buffer	lc_trk_g1_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_5	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],!B3[31]	buffer	lc_trk_g1_5	wire_mult/lc_1/in_3
+B4[26],!B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_5	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],!B7[31]	buffer	lc_trk_g1_5	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],!B11[31]	buffer	lc_trk_g1_5	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],!B15[31]	buffer	lc_trk_g1_5	wire_mult/lc_7/in_3
+!B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g1_5	wire_mult/lc_7/s_r
+B0[27],!B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_1
+B0[31],B0[32],!B0[33],B0[34],B1[31]	buffer	lc_trk_g1_6	wire_mult/lc_0/in_3
+B2[26],B3[26],B3[27],!B3[28],B3[29]	buffer	lc_trk_g1_6	wire_mult/lc_1/in_0
+B4[27],!B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_1
+B4[31],B4[32],!B4[33],B4[34],B5[31]	buffer	lc_trk_g1_6	wire_mult/lc_2/in_3
+B6[26],B7[26],B7[27],!B7[28],B7[29]	buffer	lc_trk_g1_6	wire_mult/lc_3/in_0
+B8[27],!B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_1
+B8[31],B8[32],!B8[33],B8[34],B9[31]	buffer	lc_trk_g1_6	wire_mult/lc_4/in_3
+B12[27],!B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_1
+B12[31],B12[32],!B12[33],B12[34],B13[31]	buffer	lc_trk_g1_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],!B1[28],B1[29]	buffer	lc_trk_g1_7	wire_mult/lc_0/in_0
+B2[27],!B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_1
+B2[31],B2[32],!B2[33],B2[34],B3[31]	buffer	lc_trk_g1_7	wire_mult/lc_1/in_3
+B4[26],B5[26],B5[27],!B5[28],B5[29]	buffer	lc_trk_g1_7	wire_mult/lc_2/in_0
+B6[27],!B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_1
+B6[31],B6[32],!B6[33],B6[34],B7[31]	buffer	lc_trk_g1_7	wire_mult/lc_3/in_3
+B10[27],!B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_1
+B10[31],B10[32],!B10[33],B10[34],B11[31]	buffer	lc_trk_g1_7	wire_mult/lc_5/in_3
+B14[27],!B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_1
+B14[31],B14[32],!B14[33],B14[34],B15[31]	buffer	lc_trk_g1_7	wire_mult/lc_7/in_3
+!B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_0	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_0	wire_mult/lc_1/in_3
+!B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_0	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_0	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_0	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_0	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_1	wire_mult/lc_0/in_3
+!B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_1	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_1	wire_mult/lc_2/in_3
+!B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_1	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_1	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_1	wire_mult/lc_6/in_3
+!B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_2	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_2	wire_mult/lc_1/in_3
+!B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_2	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_2	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_2	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_2	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_3	wire_mult/lc_0/in_3
+!B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_3	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_3	wire_mult/lc_2/in_3
+!B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_3	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_3	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_3	wire_mult/lc_6/in_3
+B0[26],!B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_4	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],!B3[31]	buffer	lc_trk_g2_4	wire_mult/lc_1/in_3
+B4[26],!B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_4	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],!B7[31]	buffer	lc_trk_g2_4	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],!B11[31]	buffer	lc_trk_g2_4	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],!B15[31]	buffer	lc_trk_g2_4	wire_mult/lc_7/in_3
+B14[0],B14[1],!B15[0],B15[1]	buffer	lc_trk_g2_4	wire_mult/lc_7/s_r
+!B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],!B1[31]	buffer	lc_trk_g2_5	wire_mult/lc_0/in_3
+B2[26],!B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_5	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],!B5[31]	buffer	lc_trk_g2_5	wire_mult/lc_2/in_3
+B6[26],!B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_5	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],!B9[31]	buffer	lc_trk_g2_5	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],!B13[31]	buffer	lc_trk_g2_5	wire_mult/lc_6/in_3
+B0[26],B1[26],!B1[27],B1[28],B1[29]	buffer	lc_trk_g2_6	wire_mult/lc_0/in_0
+!B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],!B2[34],B3[31]	buffer	lc_trk_g2_6	wire_mult/lc_1/in_3
+B4[26],B5[26],!B5[27],B5[28],B5[29]	buffer	lc_trk_g2_6	wire_mult/lc_2/in_0
+!B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],!B6[34],B7[31]	buffer	lc_trk_g2_6	wire_mult/lc_3/in_3
+!B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],!B10[34],B11[31]	buffer	lc_trk_g2_6	wire_mult/lc_5/in_3
+!B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],!B14[34],B15[31]	buffer	lc_trk_g2_6	wire_mult/lc_7/in_3
+!B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],!B0[34],B1[31]	buffer	lc_trk_g2_7	wire_mult/lc_0/in_3
+B2[26],B3[26],!B3[27],B3[28],B3[29]	buffer	lc_trk_g2_7	wire_mult/lc_1/in_0
+!B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],!B4[34],B5[31]	buffer	lc_trk_g2_7	wire_mult/lc_2/in_3
+B6[26],B7[26],!B7[27],B7[28],B7[29]	buffer	lc_trk_g2_7	wire_mult/lc_3/in_0
+!B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],!B8[34],B9[31]	buffer	lc_trk_g2_7	wire_mult/lc_4/in_3
+!B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],!B12[34],B13[31]	buffer	lc_trk_g2_7	wire_mult/lc_6/in_3
+B0[27],B0[28],B0[29],!B0[30],!B1[30]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_0	wire_mult/lc_0/in_3
+!B2[26],!B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_0	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],!B4[30],!B5[30]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_0	wire_mult/lc_2/in_3
+!B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_0	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],!B8[30],!B9[30]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_0	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],!B13[30]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_0	wire_mult/lc_6/in_3
+!B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_1	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],!B3[30]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_1	wire_mult/lc_1/in_3
+!B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_1	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],!B6[30],!B7[30]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_1	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],!B10[30],!B11[30]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_1	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],!B14[30],!B15[30]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_1	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],!B0[30],B1[30]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_1
+!B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_2	wire_mult/lc_0/in_3
+!B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_2	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],!B4[30],B5[30]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_1
+!B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_2	wire_mult/lc_2/in_3
+!B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_2	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],!B8[30],B9[30]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_1
+!B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_2	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],!B12[30],B13[30]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_1
+!B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_2	wire_mult/lc_6/in_3
+!B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_3	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],!B2[30],B3[30]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_1
+!B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_3	wire_mult/lc_1/in_3
+!B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_3	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],!B6[30],B7[30]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_1
+!B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_3	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],!B10[30],B11[30]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_1
+!B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_3	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],!B14[30],B15[30]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_1
+!B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_3	wire_mult/lc_7/in_3
+B0[27],B0[28],B0[29],B0[30],!B1[30]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],!B1[31]	buffer	lc_trk_g3_4	wire_mult/lc_0/in_3
+B2[26],!B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_4	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],B4[30],!B5[30]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],!B5[31]	buffer	lc_trk_g3_4	wire_mult/lc_2/in_3
+B6[26],!B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_4	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],B8[30],!B9[30]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],!B9[31]	buffer	lc_trk_g3_4	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],!B13[30]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],!B13[31]	buffer	lc_trk_g3_4	wire_mult/lc_6/in_3
+B0[26],!B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_5	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],!B3[30]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],!B3[31]	buffer	lc_trk_g3_5	wire_mult/lc_1/in_3
+B4[26],!B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_5	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],B6[30],!B7[30]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],!B7[31]	buffer	lc_trk_g3_5	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],B10[30],!B11[30]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],!B11[31]	buffer	lc_trk_g3_5	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],!B15[30]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],!B15[31]	buffer	lc_trk_g3_5	wire_mult/lc_7/in_3
+B14[0],B14[1],B15[0],B15[1]	buffer	lc_trk_g3_5	wire_mult/lc_7/s_r
+B0[27],B0[28],B0[29],B0[30],B1[30]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_1
+B0[31],B0[32],B0[33],B0[34],B1[31]	buffer	lc_trk_g3_6	wire_mult/lc_0/in_3
+B2[26],B3[26],B3[27],B3[28],B3[29]	buffer	lc_trk_g3_6	wire_mult/lc_1/in_0
+B4[27],B4[28],B4[29],B4[30],B5[30]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_1
+B4[31],B4[32],B4[33],B4[34],B5[31]	buffer	lc_trk_g3_6	wire_mult/lc_2/in_3
+B6[26],B7[26],B7[27],B7[28],B7[29]	buffer	lc_trk_g3_6	wire_mult/lc_3/in_0
+B8[27],B8[28],B8[29],B8[30],B9[30]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_1
+B8[31],B8[32],B8[33],B8[34],B9[31]	buffer	lc_trk_g3_6	wire_mult/lc_4/in_3
+B12[27],B12[28],B12[29],B12[30],B13[30]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_1
+B12[31],B12[32],B12[33],B12[34],B13[31]	buffer	lc_trk_g3_6	wire_mult/lc_6/in_3
+B0[26],B1[26],B1[27],B1[28],B1[29]	buffer	lc_trk_g3_7	wire_mult/lc_0/in_0
+B2[27],B2[28],B2[29],B2[30],B3[30]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_1
+B2[31],B2[32],B2[33],B2[34],B3[31]	buffer	lc_trk_g3_7	wire_mult/lc_1/in_3
+B4[26],B5[26],B5[27],B5[28],B5[29]	buffer	lc_trk_g3_7	wire_mult/lc_2/in_0
+B6[27],B6[28],B6[29],B6[30],B7[30]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_1
+B6[31],B6[32],B6[33],B6[34],B7[31]	buffer	lc_trk_g3_7	wire_mult/lc_3/in_3
+B10[27],B10[28],B10[29],B10[30],B11[30]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_1
+B10[31],B10[32],B10[33],B10[34],B11[31]	buffer	lc_trk_g3_7	wire_mult/lc_5/in_3
+B14[27],B14[28],B14[29],B14[30],B15[30]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_1
+B14[31],B14[32],B14[33],B14[34],B15[31]	buffer	lc_trk_g3_7	wire_mult/lc_7/in_3
+B4[14],!B5[14],B5[15],!B5[16],B5[17]	buffer	lft_op_0	lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18]	buffer	lft_op_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18]	buffer	lft_op_1	lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25]	buffer	lft_op_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25]	buffer	lft_op_2	lc_trk_g1_2
+B4[21],B4[22],!B4[23],B4[24],!B5[21]	buffer	lft_op_3	lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17]	buffer	lft_op_4	lc_trk_g0_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18]	buffer	lft_op_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18]	buffer	lft_op_5	lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25]	buffer	lft_op_6	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25]	buffer	lft_op_6	lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21]	buffer	lft_op_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21]	buffer	lft_op_7	lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	rgt_op_0	lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	rgt_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18]	buffer	rgt_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18]	buffer	rgt_op_1	lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	rgt_op_2	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	rgt_op_2	lc_trk_g3_2
+B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	rgt_op_3	lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	rgt_op_4	lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	rgt_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18]	buffer	rgt_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18]	buffer	rgt_op_5	lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	rgt_op_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	rgt_op_6	lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	rgt_op_7	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	rgt_op_7	lc_trk_g3_7
+B0[21],B0[22],!B0[23],B0[24],B1[21]	buffer	sp12_h_l_0	lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21]	buffer	sp12_h_l_0	lc_trk_g1_3
+!B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp12_h_l_10	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp12_h_l_10	lc_trk_g1_5
+!B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_l_11	lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_l_11	lc_trk_g1_4
+B4[2]	buffer	sp12_h_l_11	sp4_h_l_7
+!B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp12_h_l_14	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp12_h_l_14	lc_trk_g1_1
+!B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp12_h_l_17	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp12_h_l_17	lc_trk_g1_2
+B10[2]	buffer	sp12_h_l_17	sp4_h_r_21
+!B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp12_h_l_20	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp12_h_l_20	lc_trk_g1_7
+B2[25],B3[22],!B3[23],B3[24],B3[25]	buffer	sp12_h_l_5	lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25]	buffer	sp12_h_l_5	lc_trk_g1_6
+B14[19]	buffer	sp12_h_l_5	sp4_h_r_15
+!B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp12_h_l_8	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp12_h_l_8	lc_trk_g1_3
+!B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp12_h_l_9	lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp12_h_l_9	lc_trk_g1_2
+B3[1]	buffer	sp12_h_l_9	sp4_h_r_17
+B0[14],B1[14],B1[15],!B1[16],B1[17]	buffer	sp12_h_r_0	lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17]	buffer	sp12_h_r_0	lc_trk_g1_0
+B13[19]	buffer	sp12_h_r_0	sp4_h_r_12
+B0[15],!B0[16],B0[17],B0[18],B1[18]	buffer	sp12_h_r_1	lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18]	buffer	sp12_h_r_1	lc_trk_g1_1
+!B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp12_h_r_14	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp12_h_r_14	lc_trk_g1_6
+B6[2]	buffer	sp12_h_r_14	sp4_h_l_6
+!B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp12_h_r_15	lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp12_h_r_15	lc_trk_g1_7
+!B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_16	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_16	lc_trk_g1_0
+B8[2]	buffer	sp12_h_r_16	sp4_h_r_20
+!B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp12_h_r_19	lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp12_h_r_19	lc_trk_g1_3
+B0[25],B1[22],!B1[23],B1[24],B1[25]	buffer	sp12_h_r_2	lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25]	buffer	sp12_h_r_2	lc_trk_g1_2
+B12[19]	buffer	sp12_h_r_2	sp4_h_l_0
+!B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp12_h_r_20	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp12_h_r_20	lc_trk_g1_4
+B12[2]	buffer	sp12_h_r_20	sp4_h_l_11
+!B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp12_h_r_21	lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp12_h_r_21	lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp12_h_r_22	lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp12_h_r_22	lc_trk_g1_6
+B14[2]	buffer	sp12_h_r_22	sp4_h_r_23
+B2[14],B3[14],B3[15],!B3[16],B3[17]	buffer	sp12_h_r_4	lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17]	buffer	sp12_h_r_4	lc_trk_g1_4
+B15[19]	buffer	sp12_h_r_4	sp4_h_l_3
+B2[15],!B2[16],B2[17],B2[18],B3[18]	buffer	sp12_h_r_5	lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18]	buffer	sp12_h_r_5	lc_trk_g1_5
+B2[21],B2[22],!B2[23],B2[24],B3[21]	buffer	sp12_h_r_7	lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21]	buffer	sp12_h_r_7	lc_trk_g1_7
+!B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp12_h_r_8	lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp12_h_r_8	lc_trk_g1_0
+B0[2]	buffer	sp12_h_r_8	sp4_h_l_5
+!B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp12_h_r_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp12_h_r_9	lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	sp12_v_b_0	lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	sp12_v_b_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18]	buffer	sp12_v_b_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18]	buffer	sp12_v_b_1	lc_trk_g3_1
+B1[19]	buffer	sp12_v_b_1	sp4_v_t_1
+!B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_12	lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_12	lc_trk_g3_4
+!B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_b_16	lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_b_16	lc_trk_g3_0
+!B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp12_v_b_20	lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp12_v_b_20	lc_trk_g3_4
+!B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp12_v_b_21	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp12_v_b_21	lc_trk_g3_5
+B11[19]	buffer	sp12_v_b_21	sp4_v_b_22
+!B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp12_v_b_22	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp12_v_b_22	lc_trk_g3_6
+B10[15],!B10[16],B10[17],B10[18],B11[18]	buffer	sp12_v_b_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18]	buffer	sp12_v_b_5	lc_trk_g3_5
+B3[19]	buffer	sp12_v_b_5	sp4_v_b_14
+B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	sp12_v_b_6	lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	sp12_v_b_6	lc_trk_g3_6
+!B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp12_v_b_9	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp12_v_b_9	lc_trk_g3_1
+B5[19]	buffer	sp12_v_b_9	sp4_v_t_5
+B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	sp12_v_t_0	lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	sp12_v_t_0	lc_trk_g3_3
+B0[19]	buffer	sp12_v_t_0	sp4_v_t_0
+B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	sp12_v_t_1	lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	sp12_v_t_1	lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp12_v_t_10	lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp12_v_t_10	lc_trk_g3_5
+B7[19]	buffer	sp12_v_t_10	sp4_v_b_18
+!B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp12_v_t_12	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp12_v_t_12	lc_trk_g3_7
+B6[19]	buffer	sp12_v_t_12	sp4_v_b_19
+!B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp12_v_t_13	lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp12_v_t_13	lc_trk_g3_6
+!B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp12_v_t_14	lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp12_v_t_14	lc_trk_g3_1
+B9[19]	buffer	sp12_v_t_14	sp4_v_b_20
+!B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp12_v_t_16	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp12_v_t_16	lc_trk_g3_3
+B8[19]	buffer	sp12_v_t_16	sp4_v_t_8
+!B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp12_v_t_17	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp12_v_t_17	lc_trk_g3_2
+!B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp12_v_t_20	lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp12_v_t_20	lc_trk_g3_7
+B10[19]	buffer	sp12_v_t_20	sp4_v_t_10
+B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	sp12_v_t_3	lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	sp12_v_t_3	lc_trk_g3_4
+B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	sp12_v_t_4	lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	sp12_v_t_4	lc_trk_g3_7
+B2[19]	buffer	sp12_v_t_4	sp4_v_b_15
+!B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp12_v_t_7	lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp12_v_t_7	lc_trk_g3_0
+!B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp12_v_t_8	lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp12_v_t_8	lc_trk_g3_3
+B4[19]	buffer	sp12_v_t_8	sp4_v_b_17
+!B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp12_v_t_9	lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp12_v_t_9	lc_trk_g3_2
+B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_h_l_0	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_h_l_0	lc_trk_g1_5
+B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_l_11	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_l_11	lc_trk_g1_6
+!B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_l_13	lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_l_13	lc_trk_g3_0
+!B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_l_15	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_l_15	lc_trk_g3_2
+!B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_17	lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_17	lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_l_18	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_l_18	lc_trk_g3_7
+B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_h_l_20	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_h_l_20	lc_trk_g3_1
+B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_h_l_24	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_h_l_24	lc_trk_g3_5
+B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_25	lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_25	lc_trk_g3_4
+B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_h_l_27	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_h_l_27	lc_trk_g3_6
+B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_h_l_3	lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_h_l_3	lc_trk_g1_6
+B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_l_30	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_l_30	lc_trk_g3_3
+B10[14],B11[14],B11[15],B11[16],B11[17]	buffer	sp4_h_l_33	lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17]	buffer	sp4_h_l_33	lc_trk_g3_4
+B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_l_5	lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_l_5	lc_trk_g1_0
+B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_l_6	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_l_6	lc_trk_g1_3
+B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_l_7	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_l_7	lc_trk_g1_2
+!B0[14],B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_0	lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_0	lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_h_r_1	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_h_r_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_h_r_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_h_r_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_h_r_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_h_r_11	lc_trk_g1_3
+B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_12	lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_12	lc_trk_g1_4
+B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_h_r_15	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_h_r_15	lc_trk_g1_7
+B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_h_r_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_h_r_17	lc_trk_g1_1
+!B0[25],B1[22],B1[23],B1[24],B1[25]	buffer	sp4_h_r_2	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25]	buffer	sp4_h_r_2	lc_trk_g1_2
+B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_20	lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_20	lc_trk_g1_4
+B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_h_r_21	lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_h_r_21	lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_23	lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_23	lc_trk_g1_7
+B8[15],B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_h_r_25	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_h_r_25	lc_trk_g3_1
+!B8[21],B8[22],B8[23],B8[24],B9[21]	buffer	sp4_h_r_27	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21]	buffer	sp4_h_r_27	lc_trk_g3_3
+B10[15],B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_h_r_29	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_h_r_29	lc_trk_g3_5
+!B0[21],B0[22],B0[23],B0[24],B1[21]	buffer	sp4_h_r_3	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21]	buffer	sp4_h_r_3	lc_trk_g1_3
+!B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_30	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_30	lc_trk_g3_6
+B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_32	lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_32	lc_trk_g3_0
+B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_h_r_34	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_h_r_34	lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_h_r_35	lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_h_r_35	lc_trk_g3_3
+B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_h_r_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_h_r_39	lc_trk_g3_7
+!B2[14],B3[14],B3[15],B3[16],B3[17]	buffer	sp4_h_r_4	lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17]	buffer	sp4_h_r_4	lc_trk_g1_4
+B8[14],B9[14],B9[15],B9[16],B9[17]	buffer	sp4_h_r_40	lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17]	buffer	sp4_h_r_40	lc_trk_g3_0
+B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_h_r_41	lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_h_r_41	lc_trk_g3_1
+B8[25],B9[22],B9[23],B9[24],B9[25]	buffer	sp4_h_r_42	lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25]	buffer	sp4_h_r_42	lc_trk_g3_2
+B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_h_r_45	lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_h_r_45	lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],B11[25]	buffer	sp4_h_r_46	lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25]	buffer	sp4_h_r_46	lc_trk_g3_6
+B10[21],B10[22],B10[23],B10[24],B11[21]	buffer	sp4_h_r_47	lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21]	buffer	sp4_h_r_47	lc_trk_g3_7
+B2[15],B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_h_r_5	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_h_r_5	lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25]	buffer	sp4_h_r_6	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25]	buffer	sp4_h_r_6	lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21]	buffer	sp4_h_r_7	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21]	buffer	sp4_h_r_7	lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_h_r_8	lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_h_r_8	lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_h_r_9	lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_h_r_9	lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_0	lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_r_v_b_1	lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25]	buffer	sp4_r_v_b_10	lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21]	buffer	sp4_r_v_b_11	lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_12	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_r_v_b_13	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25]	buffer	sp4_r_v_b_14	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21]	buffer	sp4_r_v_b_15	lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_16	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_r_v_b_17	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25]	buffer	sp4_r_v_b_18	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21]	buffer	sp4_r_v_b_19	lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25]	buffer	sp4_r_v_b_2	lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_20	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_r_v_b_21	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25]	buffer	sp4_r_v_b_22	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21]	buffer	sp4_r_v_b_23	lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_24	lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17]	buffer	sp4_r_v_b_24	lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_r_v_b_25	lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18]	buffer	sp4_r_v_b_25	lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25]	buffer	sp4_r_v_b_26	lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25]	buffer	sp4_r_v_b_26	lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21]	buffer	sp4_r_v_b_27	lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21]	buffer	sp4_r_v_b_27	lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17]	buffer	sp4_r_v_b_28	lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_28	lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18]	buffer	sp4_r_v_b_29	lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18]	buffer	sp4_r_v_b_29	lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21]	buffer	sp4_r_v_b_3	lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25]	buffer	sp4_r_v_b_30	lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25]	buffer	sp4_r_v_b_30	lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21]	buffer	sp4_r_v_b_31	lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21]	buffer	sp4_r_v_b_31	lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21]	buffer	sp4_r_v_b_32	lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_32	lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25]	buffer	sp4_r_v_b_33	lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	sp4_r_v_b_33	lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18]	buffer	sp4_r_v_b_34	lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25]	buffer	sp4_r_v_b_34	lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17]	buffer	sp4_r_v_b_35	lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21]	buffer	sp4_r_v_b_35	lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17]	buffer	sp4_r_v_b_36	lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	sp4_r_v_b_37	lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25]	buffer	sp4_r_v_b_38	lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21]	buffer	sp4_r_v_b_39	lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17]	buffer	sp4_r_v_b_4	lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17]	buffer	sp4_r_v_b_40	lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	sp4_r_v_b_41	lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25]	buffer	sp4_r_v_b_42	lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21]	buffer	sp4_r_v_b_43	lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17]	buffer	sp4_r_v_b_44	lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	sp4_r_v_b_45	lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25]	buffer	sp4_r_v_b_46	lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21]	buffer	sp4_r_v_b_47	lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_r_v_b_5	lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25]	buffer	sp4_r_v_b_6	lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21]	buffer	sp4_r_v_b_7	lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17]	buffer	sp4_r_v_b_8	lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_r_v_b_9	lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_0	lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_0	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18]	buffer	sp4_v_b_1	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18]	buffer	sp4_v_b_1	lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25]	buffer	sp4_v_b_10	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25]	buffer	sp4_v_b_10	lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21]	buffer	sp4_v_b_11	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21]	buffer	sp4_v_b_11	lc_trk_g1_3
+B2[25],B3[22],B3[23],!B3[24],B3[25]	buffer	sp4_v_b_14	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25]	buffer	sp4_v_b_14	lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],B3[21]	buffer	sp4_v_b_15	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21]	buffer	sp4_v_b_15	lc_trk_g1_7
+B0[15],B0[16],B0[17],!B0[18],!B1[18]	buffer	sp4_v_b_17	lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18]	buffer	sp4_v_b_17	lc_trk_g1_1
+!B0[25],B1[22],B1[23],B1[24],!B1[25]	buffer	sp4_v_b_18	lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25]	buffer	sp4_v_b_18	lc_trk_g1_2
+!B0[21],B0[22],B0[23],B0[24],!B1[21]	buffer	sp4_v_b_19	lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21]	buffer	sp4_v_b_19	lc_trk_g1_3
+B0[25],B1[22],B1[23],!B1[24],!B1[25]	buffer	sp4_v_b_2	lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25]	buffer	sp4_v_b_2	lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17]	buffer	sp4_v_b_20	lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17]	buffer	sp4_v_b_20	lc_trk_g1_4
+!B2[25],B3[22],B3[23],B3[24],!B3[25]	buffer	sp4_v_b_22	lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25]	buffer	sp4_v_b_22	lc_trk_g1_6
+B8[25],B9[22],B9[23],!B9[24],!B9[25]	buffer	sp4_v_b_26	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25]	buffer	sp4_v_b_26	lc_trk_g3_2
+B8[21],B8[22],B8[23],!B8[24],!B9[21]	buffer	sp4_v_b_27	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21]	buffer	sp4_v_b_27	lc_trk_g3_3
+B10[14],!B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_b_28	lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_b_28	lc_trk_g3_4
+B0[21],B0[22],B0[23],!B0[24],!B1[21]	buffer	sp4_v_b_3	lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21]	buffer	sp4_v_b_3	lc_trk_g1_3
+B10[21],B10[22],B10[23],!B10[24],!B11[21]	buffer	sp4_v_b_31	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21]	buffer	sp4_v_b_31	lc_trk_g3_7
+B8[14],B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_b_32	lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_b_32	lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],B9[21]	buffer	sp4_v_b_35	lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21]	buffer	sp4_v_b_35	lc_trk_g3_3
+!B10[15],B10[16],B10[17],B10[18],B11[18]	buffer	sp4_v_b_37	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18]	buffer	sp4_v_b_37	lc_trk_g3_5
+B10[21],B10[22],B10[23],!B10[24],B11[21]	buffer	sp4_v_b_39	lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21]	buffer	sp4_v_b_39	lc_trk_g3_7
+B2[14],!B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_b_4	lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_b_4	lc_trk_g1_4
+B8[15],B8[16],B8[17],!B8[18],!B9[18]	buffer	sp4_v_b_41	lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18]	buffer	sp4_v_b_41	lc_trk_g3_1
+!B8[21],B8[22],B8[23],B8[24],!B9[21]	buffer	sp4_v_b_43	lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21]	buffer	sp4_v_b_43	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],B11[16],B11[17]	buffer	sp4_v_b_44	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17]	buffer	sp4_v_b_44	lc_trk_g3_4
+!B10[25],B11[22],B11[23],B11[24],!B11[25]	buffer	sp4_v_b_46	lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25]	buffer	sp4_v_b_46	lc_trk_g3_6
+!B2[15],B2[16],B2[17],B2[18],!B3[18]	buffer	sp4_v_b_5	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18]	buffer	sp4_v_b_5	lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25]	buffer	sp4_v_b_6	lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25]	buffer	sp4_v_b_6	lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21]	buffer	sp4_v_b_7	lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21]	buffer	sp4_v_b_7	lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17]	buffer	sp4_v_b_8	lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17]	buffer	sp4_v_b_8	lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18]	buffer	sp4_v_b_9	lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18]	buffer	sp4_v_b_9	lc_trk_g1_1
+!B2[15],B2[16],B2[17],B2[18],B3[18]	buffer	sp4_v_t_0	lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18]	buffer	sp4_v_t_0	lc_trk_g1_5
+B2[14],B3[14],!B3[15],B3[16],B3[17]	buffer	sp4_v_t_1	lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17]	buffer	sp4_v_t_1	lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21]	buffer	sp4_v_t_10	lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21]	buffer	sp4_v_t_10	lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],!B9[18]	buffer	sp4_v_t_12	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18]	buffer	sp4_v_t_12	lc_trk_g3_1
+B8[14],!B9[14],!B9[15],B9[16],B9[17]	buffer	sp4_v_t_13	lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17]	buffer	sp4_v_t_13	lc_trk_g3_0
+!B10[15],B10[16],B10[17],B10[18],!B11[18]	buffer	sp4_v_t_16	lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18]	buffer	sp4_v_t_16	lc_trk_g3_5
+B10[25],B11[22],B11[23],!B11[24],!B11[25]	buffer	sp4_v_t_19	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25]	buffer	sp4_v_t_19	lc_trk_g3_6
+!B8[15],B8[16],B8[17],B8[18],B9[18]	buffer	sp4_v_t_20	lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18]	buffer	sp4_v_t_20	lc_trk_g3_1
+B8[25],B9[22],B9[23],!B9[24],B9[25]	buffer	sp4_v_t_23	lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25]	buffer	sp4_v_t_23	lc_trk_g3_2
+B10[14],B11[14],!B11[15],B11[16],B11[17]	buffer	sp4_v_t_25	lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17]	buffer	sp4_v_t_25	lc_trk_g3_4
+B10[25],B11[22],B11[23],!B11[24],B11[25]	buffer	sp4_v_t_27	lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25]	buffer	sp4_v_t_27	lc_trk_g3_6
+!B8[14],!B9[14],B9[15],B9[16],B9[17]	buffer	sp4_v_t_29	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17]	buffer	sp4_v_t_29	lc_trk_g3_0
+!B8[25],B9[22],B9[23],B9[24],!B9[25]	buffer	sp4_v_t_31	lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25]	buffer	sp4_v_t_31	lc_trk_g3_2
+B10[15],B10[16],B10[17],!B10[18],!B11[18]	buffer	sp4_v_t_32	lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18]	buffer	sp4_v_t_32	lc_trk_g3_5
+!B10[21],B10[22],B10[23],B10[24],!B11[21]	buffer	sp4_v_t_34	lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21]	buffer	sp4_v_t_34	lc_trk_g3_7
+!B0[14],!B1[14],B1[15],B1[16],B1[17]	buffer	sp4_v_t_5	lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17]	buffer	sp4_v_t_5	lc_trk_g1_0
+B2[15],B2[16],B2[17],!B2[18],!B3[18]	buffer	sp4_v_t_8	lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18]	buffer	sp4_v_t_8	lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17]	buffer	tnl_op_0	lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17]	buffer	tnl_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18]	buffer	tnl_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18]	buffer	tnl_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25]	buffer	tnl_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25]	buffer	tnl_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21]	buffer	tnl_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21]	buffer	tnl_op_3	lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17]	buffer	tnl_op_4	lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17]	buffer	tnl_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18]	buffer	tnl_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18]	buffer	tnl_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25]	buffer	tnl_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25]	buffer	tnl_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21]	buffer	tnl_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21]	buffer	tnl_op_7	lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17]	buffer	tnr_op_0	lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17]	buffer	tnr_op_0	lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18]	buffer	tnr_op_1	lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18]	buffer	tnr_op_1	lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25]	buffer	tnr_op_2	lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25]	buffer	tnr_op_2	lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21]	buffer	tnr_op_3	lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21]	buffer	tnr_op_3	lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17]	buffer	tnr_op_4	lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17]	buffer	tnr_op_4	lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18]	buffer	tnr_op_5	lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18]	buffer	tnr_op_5	lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25]	buffer	tnr_op_6	lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25]	buffer	tnr_op_6	lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21]	buffer	tnr_op_7	lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21]	buffer	tnr_op_7	lc_trk_g3_7
+B0[47]	buffer	wire_mult/mult/O_24	sp12_h_r_8
+B0[51]	buffer	wire_mult/mult/O_24	sp12_v_b_0
+B0[52]	buffer	wire_mult/mult/O_24	sp12_v_b_16
+B0[46]	buffer	wire_mult/mult/O_24	sp4_h_l_5
+B1[46]	buffer	wire_mult/mult/O_24	sp4_h_r_0
+B1[47]	buffer	wire_mult/mult/O_24	sp4_h_r_32
+B1[52]	buffer	wire_mult/mult/O_24	sp4_r_v_b_1
+B0[53]	buffer	wire_mult/mult/O_24	sp4_r_v_b_17
+B1[53]	buffer	wire_mult/mult/O_24	sp4_r_v_b_33
+B0[48]	buffer	wire_mult/mult/O_24	sp4_v_b_0
+B1[51]	buffer	wire_mult/mult/O_24	sp4_v_b_32
+B1[48]	buffer	wire_mult/mult/O_24	sp4_v_t_5
+B2[47]	buffer	wire_mult/mult/O_25	sp12_h_l_9
+B2[51]	buffer	wire_mult/mult/O_25	sp12_v_t_1
+B2[52]	buffer	wire_mult/mult/O_25	sp12_v_t_17
+B2[46]	buffer	wire_mult/mult/O_25	sp4_h_l_7
+B3[46]	buffer	wire_mult/mult/O_25	sp4_h_r_2
+B3[47]	buffer	wire_mult/mult/O_25	sp4_h_r_34
+B2[53]	buffer	wire_mult/mult/O_25	sp4_r_v_b_19
+B3[52]	buffer	wire_mult/mult/O_25	sp4_r_v_b_3
+B3[53]	buffer	wire_mult/mult/O_25	sp4_r_v_b_35
+B3[48]	buffer	wire_mult/mult/O_25	sp4_v_b_18
+B2[48]	buffer	wire_mult/mult/O_25	sp4_v_b_2
+B3[51]	buffer	wire_mult/mult/O_25	sp4_v_t_23
+B4[47]	buffer	wire_mult/mult/O_26	sp12_h_l_11
+B4[52]	buffer	wire_mult/mult/O_26	sp12_v_b_20
+B4[51]	buffer	wire_mult/mult/O_26	sp12_v_t_3
+B5[47]	buffer	wire_mult/mult/O_26	sp4_h_l_25
+B4[46]	buffer	wire_mult/mult/O_26	sp4_h_r_20
+B5[46]	buffer	wire_mult/mult/O_26	sp4_h_r_4
+B4[53]	buffer	wire_mult/mult/O_26	sp4_r_v_b_21
+B5[53]	buffer	wire_mult/mult/O_26	sp4_r_v_b_37
+B5[52]	buffer	wire_mult/mult/O_26	sp4_r_v_b_5
+B5[48]	buffer	wire_mult/mult/O_26	sp4_v_b_20
+B4[48]	buffer	wire_mult/mult/O_26	sp4_v_b_4
+B5[51]	buffer	wire_mult/mult/O_26	sp4_v_t_25
+B6[47]	buffer	wire_mult/mult/O_27	sp12_h_r_14
+B6[52]	buffer	wire_mult/mult/O_27	sp12_v_b_22
+B6[51]	buffer	wire_mult/mult/O_27	sp12_v_b_6
+B6[46]	buffer	wire_mult/mult/O_27	sp4_h_l_11
+B7[47]	buffer	wire_mult/mult/O_27	sp4_h_l_27
+B7[46]	buffer	wire_mult/mult/O_27	sp4_h_r_6
+B6[53]	buffer	wire_mult/mult/O_27	sp4_r_v_b_23
+B7[53]	buffer	wire_mult/mult/O_27	sp4_r_v_b_39
+B7[52]	buffer	wire_mult/mult/O_27	sp4_r_v_b_7
+B7[48]	buffer	wire_mult/mult/O_27	sp4_v_b_22
+B6[48]	buffer	wire_mult/mult/O_27	sp4_v_b_6
+B7[51]	buffer	wire_mult/mult/O_27	sp4_v_t_27
+B8[47]	buffer	wire_mult/mult/O_28	sp12_h_r_0
+B8[48]	buffer	wire_mult/mult/O_28	sp12_h_r_16
+B8[52]	buffer	wire_mult/mult/O_28	sp12_v_t_7
+B8[46]	buffer	wire_mult/mult/O_28	sp4_h_l_13
+B9[47]	buffer	wire_mult/mult/O_28	sp4_h_r_40
+B9[46]	buffer	wire_mult/mult/O_28	sp4_h_r_8
+B8[53]	buffer	wire_mult/mult/O_28	sp4_r_v_b_25
+B9[53]	buffer	wire_mult/mult/O_28	sp4_r_v_b_41
+B9[52]	buffer	wire_mult/mult/O_28	sp4_r_v_b_9
+B9[48]	buffer	wire_mult/mult/O_28	sp4_v_b_8
+B9[51]	buffer	wire_mult/mult/O_28	sp4_v_t_13
+B8[51]	buffer	wire_mult/mult/O_28	sp4_v_t_29
+B10[48]	buffer	wire_mult/mult/O_29	sp12_h_l_17
+B10[47]	buffer	wire_mult/mult/O_29	sp12_h_r_2
+B10[52]	buffer	wire_mult/mult/O_29	sp12_v_t_9
+B10[46]	buffer	wire_mult/mult/O_29	sp4_h_l_15
+B11[46]	buffer	wire_mult/mult/O_29	sp4_h_r_10
+B11[47]	buffer	wire_mult/mult/O_29	sp4_h_r_42
+B11[52]	buffer	wire_mult/mult/O_29	sp4_r_v_b_11
+B10[53]	buffer	wire_mult/mult/O_29	sp4_r_v_b_27
+B11[53]	buffer	wire_mult/mult/O_29	sp4_r_v_b_43
+B11[48]	buffer	wire_mult/mult/O_29	sp4_v_b_10
+B11[51]	buffer	wire_mult/mult/O_29	sp4_v_b_26
+B10[51]	buffer	wire_mult/mult/O_29	sp4_v_t_31
+B12[48]	buffer	wire_mult/mult/O_30	sp12_h_r_20
+B12[47]	buffer	wire_mult/mult/O_30	sp12_h_r_4
+B12[52]	buffer	wire_mult/mult/O_30	sp12_v_b_12
+B12[46]	buffer	wire_mult/mult/O_30	sp4_h_l_17
+B13[47]	buffer	wire_mult/mult/O_30	sp4_h_l_33
+B13[46]	buffer	wire_mult/mult/O_30	sp4_h_r_12
+B13[52]	buffer	wire_mult/mult/O_30	sp4_r_v_b_13
+B12[53]	buffer	wire_mult/mult/O_30	sp4_r_v_b_29
+B13[53]	buffer	wire_mult/mult/O_30	sp4_r_v_b_45
+B13[51]	buffer	wire_mult/mult/O_30	sp4_v_b_28
+B12[51]	buffer	wire_mult/mult/O_30	sp4_v_b_44
+B13[48]	buffer	wire_mult/mult/O_30	sp4_v_t_1
+B14[47]	buffer	wire_mult/mult/O_31	sp12_h_l_5
+B14[48]	buffer	wire_mult/mult/O_31	sp12_h_r_22
+B14[52]	buffer	wire_mult/mult/O_31	sp12_v_t_13
+B15[46]	buffer	wire_mult/mult/O_31	sp4_h_l_3
+B14[46]	buffer	wire_mult/mult/O_31	sp4_h_r_30
+B15[47]	buffer	wire_mult/mult/O_31	sp4_h_r_46
+B15[52]	buffer	wire_mult/mult/O_31	sp4_r_v_b_15
+B14[53]	buffer	wire_mult/mult/O_31	sp4_r_v_b_31
+B15[53]	buffer	wire_mult/mult/O_31	sp4_r_v_b_47
+B15[48]	buffer	wire_mult/mult/O_31	sp4_v_b_14
+B14[51]	buffer	wire_mult/mult/O_31	sp4_v_b_46
+B15[51]	buffer	wire_mult/mult/O_31	sp4_v_t_19
+!B12[3],B13[3]	routing	sp12_h_l_22	sp12_h_r_1
+!B8[3],B9[3]	routing	sp12_h_l_22	sp12_v_b_1
+!B14[3],B15[3]	routing	sp12_h_l_22	sp12_v_t_22
+!B4[3],B5[3]	routing	sp12_h_l_23	sp12_h_r_0
+!B0[3],B1[3]	routing	sp12_h_l_23	sp12_v_b_0
+!B6[3],B7[3]	routing	sp12_h_l_23	sp12_v_t_23
+B2[3],B3[3]	routing	sp12_h_r_0	sp12_h_l_23
+B0[3],B1[3]	routing	sp12_h_r_0	sp12_v_b_0
+B6[3],B7[3]	routing	sp12_h_r_0	sp12_v_t_23
+B8[3],B9[3]	routing	sp12_h_r_1	sp12_v_b_1
+B14[3],B15[3]	routing	sp12_h_r_1	sp12_v_t_22
+!B2[3],B3[3]	routing	sp12_v_b_0	sp12_h_l_23
+B4[3],B5[3]	routing	sp12_v_b_0	sp12_h_r_0
+B6[3],!B7[3]	routing	sp12_v_b_0	sp12_v_t_23
+B11[3]	routing	sp12_v_b_1	sp12_h_l_22
+B12[3],B13[3]	routing	sp12_v_b_1	sp12_h_r_1
+B14[3],!B15[3]	routing	sp12_v_b_1	sp12_v_t_22
+B10[3]	routing	sp12_v_t_22	sp12_h_l_22
+B12[3],!B13[3]	routing	sp12_v_t_22	sp12_h_r_1
+B8[3],!B9[3]	routing	sp12_v_t_22	sp12_v_b_1
+B2[3],!B3[3]	routing	sp12_v_t_23	sp12_h_l_23
+B4[3],!B5[3]	routing	sp12_v_t_23	sp12_h_r_0
+B0[3],!B1[3]	routing	sp12_v_t_23	sp12_v_b_0
+B1[8],B1[9],!B1[10]	routing	sp4_h_l_36	sp4_v_b_1
+B9[8],B9[9],B9[10]	routing	sp4_h_l_36	sp4_v_b_7
+B3[8],!B3[9],!B3[10]	routing	sp4_h_l_36	sp4_v_t_36
+!B10[4],B10[6],!B11[5]	routing	sp4_h_l_36	sp4_v_t_43
+!B8[12],B9[11],B9[13]	routing	sp4_h_l_37	sp4_h_r_8
+B0[4],!B0[6],B1[5]	routing	sp4_h_l_37	sp4_v_b_0
+B8[4],B8[6],B9[5]	routing	sp4_h_l_37	sp4_v_b_6
+!B2[4],!B2[6],B3[5]	routing	sp4_h_l_37	sp4_v_t_37
+B6[11],!B6[13],!B7[12]	routing	sp4_h_l_37	sp4_v_t_40
+B4[4],!B4[6],B5[5]	routing	sp4_h_l_38	sp4_v_b_3
+B12[4],B12[6],B13[5]	routing	sp4_h_l_38	sp4_v_b_9
+!B6[4],!B6[6],B7[5]	routing	sp4_h_l_38	sp4_v_t_38
+B10[11],!B10[13],!B11[12]	routing	sp4_h_l_38	sp4_v_t_45
+!B0[11],B0[13],B1[12]	routing	sp4_h_l_39	sp4_v_b_2
+B8[11],B8[13],B9[12]	routing	sp4_h_l_39	sp4_v_b_8
+!B2[11],!B2[13],B3[12]	routing	sp4_h_l_39	sp4_v_t_39
+!B11[8],!B11[9],B11[10]	routing	sp4_h_l_39	sp4_v_t_42
+B0[8],!B0[9],B0[10]	routing	sp4_h_l_40	sp4_h_r_1
+!B4[12],B5[11],!B5[13]	routing	sp4_h_l_40	sp4_h_r_5
+B8[12],!B9[11],B9[13]	routing	sp4_h_l_40	sp4_h_r_8
+B12[11],B12[13],B13[12]	routing	sp4_h_l_40	sp4_v_b_11
+!B4[11],B4[13],B5[12]	routing	sp4_h_l_40	sp4_v_b_5
+!B6[11],!B6[13],B7[12]	routing	sp4_h_l_40	sp4_v_t_40
+!B15[8],!B15[9],B15[10]	routing	sp4_h_l_40	sp4_v_t_47
+!B0[5],B1[4],B1[6]	routing	sp4_h_l_41	sp4_h_r_0
+!B8[8],B8[9],B8[10]	routing	sp4_h_l_41	sp4_h_r_7
+B13[8],B13[9],B13[10]	routing	sp4_h_l_41	sp4_v_b_10
+B5[8],B5[9],!B5[10]	routing	sp4_h_l_41	sp4_v_b_4
+B7[8],!B7[9],!B7[10]	routing	sp4_h_l_41	sp4_v_t_41
+!B14[4],B14[6],!B15[5]	routing	sp4_h_l_41	sp4_v_t_44
+!B12[8],B12[9],B12[10]	routing	sp4_h_l_42	sp4_h_r_10
+B1[8],B1[9],B1[10]	routing	sp4_h_l_42	sp4_v_b_1
+B9[8],B9[9],!B9[10]	routing	sp4_h_l_42	sp4_v_b_7
+!B2[4],B2[6],!B3[5]	routing	sp4_h_l_42	sp4_v_t_37
+B11[8],!B11[9],!B11[10]	routing	sp4_h_l_42	sp4_v_t_42
+B0[4],B0[6],B1[5]	routing	sp4_h_l_43	sp4_v_b_0
+B8[4],!B8[6],B9[5]	routing	sp4_h_l_43	sp4_v_b_6
+!B10[4],!B10[6],B11[5]	routing	sp4_h_l_43	sp4_v_t_43
+B14[11],!B14[13],!B15[12]	routing	sp4_h_l_43	sp4_v_t_46
+!B4[12],B5[11],B5[13]	routing	sp4_h_l_44	sp4_h_r_5
+B4[4],B4[6],B5[5]	routing	sp4_h_l_44	sp4_v_b_3
+B12[4],!B12[6],B13[5]	routing	sp4_h_l_44	sp4_v_b_9
+B2[11],!B2[13],!B3[12]	routing	sp4_h_l_44	sp4_v_t_39
+!B14[4],!B14[6],B15[5]	routing	sp4_h_l_44	sp4_v_t_44
+B4[8],!B4[9],B4[10]	routing	sp4_h_l_45	sp4_h_r_4
+B0[11],B0[13],B1[12]	routing	sp4_h_l_45	sp4_v_b_2
+!B8[11],B8[13],B9[12]	routing	sp4_h_l_45	sp4_v_b_8
+!B3[8],!B3[9],B3[10]	routing	sp4_h_l_45	sp4_v_t_36
+!B10[11],!B10[13],B11[12]	routing	sp4_h_l_45	sp4_v_t_45
+!B12[12],B13[11],!B13[13]	routing	sp4_h_l_46	sp4_h_r_11
+B0[12],!B1[11],B1[13]	routing	sp4_h_l_46	sp4_h_r_2
+B8[8],!B8[9],B8[10]	routing	sp4_h_l_46	sp4_h_r_7
+!B12[11],B12[13],B13[12]	routing	sp4_h_l_46	sp4_v_b_11
+B4[11],B4[13],B5[12]	routing	sp4_h_l_46	sp4_v_b_5
+!B7[8],!B7[9],B7[10]	routing	sp4_h_l_46	sp4_v_t_41
+!B14[11],!B14[13],B15[12]	routing	sp4_h_l_46	sp4_v_t_46
+B13[8],B13[9],!B13[10]	routing	sp4_h_l_47	sp4_v_b_10
+B5[8],B5[9],B5[10]	routing	sp4_h_l_47	sp4_v_b_4
+!B6[4],B6[6],!B7[5]	routing	sp4_h_l_47	sp4_v_t_38
+B15[8],!B15[9],!B15[10]	routing	sp4_h_l_47	sp4_v_t_47
+!B2[5],!B3[4],B3[6]	routing	sp4_h_r_0	sp4_h_l_37
+B6[5],B7[4],!B7[6]	routing	sp4_h_r_0	sp4_h_l_38
+!B10[12],B11[11],B11[13]	routing	sp4_h_r_0	sp4_h_l_45
+!B0[4],!B0[6],B1[5]	routing	sp4_h_r_0	sp4_v_b_0
+B4[11],!B4[13],!B5[12]	routing	sp4_h_r_0	sp4_v_b_5
+B2[4],!B2[6],B3[5]	routing	sp4_h_r_0	sp4_v_t_37
+B10[4],B10[6],B11[5]	routing	sp4_h_r_0	sp4_v_t_43
+B2[8],!B2[9],!B2[10]	routing	sp4_h_r_1	sp4_h_l_36
+!B14[5],B15[4],B15[6]	routing	sp4_h_r_1	sp4_h_l_44
+B1[8],!B1[9],!B1[10]	routing	sp4_h_r_1	sp4_v_b_1
+!B8[4],B8[6],!B9[5]	routing	sp4_h_r_1	sp4_v_b_6
+B3[8],B3[9],!B3[10]	routing	sp4_h_r_1	sp4_v_t_36
+B11[8],B11[9],B11[10]	routing	sp4_h_r_1	sp4_v_t_42
+!B2[8],B2[9],B2[10]	routing	sp4_h_r_10	sp4_h_l_36
+!B10[5],B11[4],B11[6]	routing	sp4_h_r_10	sp4_h_l_43
+B14[8],!B14[9],!B14[10]	routing	sp4_h_r_10	sp4_h_l_47
+B13[8],!B13[9],!B13[10]	routing	sp4_h_r_10	sp4_v_b_10
+!B4[4],B4[6],!B5[5]	routing	sp4_h_r_10	sp4_v_b_3
+B7[8],B7[9],B7[10]	routing	sp4_h_r_10	sp4_v_t_41
+B15[8],B15[9],!B15[10]	routing	sp4_h_r_10	sp4_v_t_47
+!B12[11],!B12[13],B13[12]	routing	sp4_h_r_11	sp4_v_b_11
+!B5[8],!B5[9],B5[10]	routing	sp4_h_r_11	sp4_v_b_4
+B6[11],B6[13],B7[12]	routing	sp4_h_r_11	sp4_v_t_40
+!B14[11],B14[13],B15[12]	routing	sp4_h_r_11	sp4_v_t_46
+!B2[12],B3[11],!B3[13]	routing	sp4_h_r_2	sp4_h_l_39
+B6[12],!B7[11],B7[13]	routing	sp4_h_r_2	sp4_h_l_40
+B14[8],!B14[9],B14[10]	routing	sp4_h_r_2	sp4_h_l_47
+!B0[11],!B0[13],B1[12]	routing	sp4_h_r_2	sp4_v_b_2
+!B9[8],!B9[9],B9[10]	routing	sp4_h_r_2	sp4_v_b_7
+!B2[11],B2[13],B3[12]	routing	sp4_h_r_2	sp4_v_t_39
+B10[11],B10[13],B11[12]	routing	sp4_h_r_2	sp4_v_t_45
+!B14[12],B15[11],B15[13]	routing	sp4_h_r_3	sp4_h_l_46
+!B4[4],!B4[6],B5[5]	routing	sp4_h_r_3	sp4_v_b_3
+B8[11],!B8[13],!B9[12]	routing	sp4_h_r_3	sp4_v_b_8
+B6[4],!B6[6],B7[5]	routing	sp4_h_r_3	sp4_v_t_38
+B14[4],B14[6],B15[5]	routing	sp4_h_r_3	sp4_v_t_44
+!B2[5],B3[4],B3[6]	routing	sp4_h_r_4	sp4_h_l_37
+B6[8],!B6[9],!B6[10]	routing	sp4_h_r_4	sp4_h_l_41
+!B10[8],B10[9],B10[10]	routing	sp4_h_r_4	sp4_h_l_42
+B5[8],!B5[9],!B5[10]	routing	sp4_h_r_4	sp4_v_b_4
+!B12[4],B12[6],!B13[5]	routing	sp4_h_r_4	sp4_v_b_9
+B7[8],B7[9],!B7[10]	routing	sp4_h_r_4	sp4_v_t_41
+B15[8],B15[9],B15[10]	routing	sp4_h_r_4	sp4_v_t_47
+!B13[8],!B13[9],B13[10]	routing	sp4_h_r_5	sp4_v_b_10
+!B4[11],!B4[13],B5[12]	routing	sp4_h_r_5	sp4_v_b_5
+!B6[11],B6[13],B7[12]	routing	sp4_h_r_5	sp4_v_t_40
+B14[11],B14[13],B15[12]	routing	sp4_h_r_5	sp4_v_t_46
+!B2[12],B3[11],B3[13]	routing	sp4_h_r_6	sp4_h_l_39
+!B10[5],!B11[4],B11[6]	routing	sp4_h_r_6	sp4_h_l_43
+B14[5],B15[4],!B15[6]	routing	sp4_h_r_6	sp4_h_l_44
+B12[11],!B12[13],!B13[12]	routing	sp4_h_r_6	sp4_v_b_11
+!B8[4],!B8[6],B9[5]	routing	sp4_h_r_6	sp4_v_b_6
+B2[4],B2[6],B3[5]	routing	sp4_h_r_6	sp4_v_t_37
+B10[4],!B10[6],B11[5]	routing	sp4_h_r_6	sp4_v_t_43
+!B0[4],B0[6],!B1[5]	routing	sp4_h_r_7	sp4_v_b_0
+B9[8],!B9[9],!B9[10]	routing	sp4_h_r_7	sp4_v_b_7
+B3[8],B3[9],B3[10]	routing	sp4_h_r_7	sp4_v_t_36
+B11[8],B11[9],!B11[10]	routing	sp4_h_r_7	sp4_v_t_42
+B6[8],!B6[9],B6[10]	routing	sp4_h_r_8	sp4_h_l_41
+!B10[12],B11[11],!B11[13]	routing	sp4_h_r_8	sp4_h_l_45
+B14[12],!B15[11],B15[13]	routing	sp4_h_r_8	sp4_h_l_46
+!B1[8],!B1[9],B1[10]	routing	sp4_h_r_8	sp4_v_b_1
+!B8[11],!B8[13],B9[12]	routing	sp4_h_r_8	sp4_v_b_8
+B2[11],B2[13],B3[12]	routing	sp4_h_r_8	sp4_v_t_39
+!B10[11],B10[13],B11[12]	routing	sp4_h_r_8	sp4_v_t_45
+B0[11],!B0[13],!B1[12]	routing	sp4_h_r_9	sp4_v_b_2
+B6[4],B6[6],B7[5]	routing	sp4_h_r_9	sp4_v_t_38
+B14[4],!B14[6],B15[5]	routing	sp4_h_r_9	sp4_v_t_44
+B2[5],!B3[4],!B3[6]	routing	sp4_v_b_0	sp4_h_l_37
+!B6[12],!B7[11],B7[13]	routing	sp4_v_b_0	sp4_h_l_40
+B0[5],!B1[4],B1[6]	routing	sp4_v_b_0	sp4_h_r_0
+B8[5],B9[4],B9[6]	routing	sp4_v_b_0	sp4_h_r_6
+B2[4],!B2[6],!B3[5]	routing	sp4_v_b_0	sp4_v_t_37
+!B6[4],B6[6],B7[5]	routing	sp4_v_b_0	sp4_v_t_38
+B10[11],B10[13],!B11[12]	routing	sp4_v_b_0	sp4_v_t_45
+!B2[8],B2[9],!B2[10]	routing	sp4_v_b_1	sp4_h_l_36
+!B10[5],B11[4],!B11[6]	routing	sp4_v_b_1	sp4_h_l_43
+B0[8],B0[9],!B0[10]	routing	sp4_v_b_1	sp4_h_r_1
+B8[8],B8[9],B8[10]	routing	sp4_v_b_1	sp4_h_r_7
+!B3[8],B3[9],!B3[10]	routing	sp4_v_b_1	sp4_v_t_36
+B7[8],!B7[9],B7[10]	routing	sp4_v_b_1	sp4_v_t_41
+B14[4],B14[6],!B15[5]	routing	sp4_v_b_1	sp4_v_t_44
+!B6[5],B7[4],!B7[6]	routing	sp4_v_b_10	sp4_h_l_38
+!B14[8],B14[9],!B14[10]	routing	sp4_v_b_10	sp4_h_l_47
+B12[8],B12[9],!B12[10]	routing	sp4_v_b_10	sp4_h_r_10
+B4[8],B4[9],B4[10]	routing	sp4_v_b_10	sp4_h_r_4
+B3[8],!B3[9],B3[10]	routing	sp4_v_b_10	sp4_v_t_36
+B10[4],B10[6],!B11[5]	routing	sp4_v_b_10	sp4_v_t_43
+!B15[8],B15[9],!B15[10]	routing	sp4_v_b_10	sp4_v_t_47
+!B6[8],!B6[9],B6[10]	routing	sp4_v_b_11	sp4_h_l_41
+B14[12],!B15[11],!B15[13]	routing	sp4_v_b_11	sp4_h_l_46
+B12[12],B13[11],!B13[13]	routing	sp4_v_b_11	sp4_h_r_11
+B4[12],B5[11],B5[13]	routing	sp4_v_b_11	sp4_h_r_5
+B2[11],!B2[13],B3[12]	routing	sp4_v_b_11	sp4_v_t_39
+!B11[8],B11[9],B11[10]	routing	sp4_v_b_11	sp4_v_t_42
+!B14[11],B14[13],!B15[12]	routing	sp4_v_b_11	sp4_v_t_46
+B2[12],!B3[11],!B3[13]	routing	sp4_v_b_2	sp4_h_l_39
+!B10[8],!B10[9],B10[10]	routing	sp4_v_b_2	sp4_h_l_42
+B0[12],B1[11],!B1[13]	routing	sp4_v_b_2	sp4_h_r_2
+B8[12],B9[11],B9[13]	routing	sp4_v_b_2	sp4_h_r_8
+!B2[11],B2[13],!B3[12]	routing	sp4_v_b_2	sp4_v_t_39
+B6[11],!B6[13],B7[12]	routing	sp4_v_b_2	sp4_v_t_40
+!B15[8],B15[9],B15[10]	routing	sp4_v_b_2	sp4_v_t_47
+B6[5],!B7[4],!B7[6]	routing	sp4_v_b_3	sp4_h_l_38
+!B10[12],!B11[11],B11[13]	routing	sp4_v_b_3	sp4_h_l_45
+B4[5],!B5[4],B5[6]	routing	sp4_v_b_3	sp4_h_r_3
+B12[5],B13[4],B13[6]	routing	sp4_v_b_3	sp4_h_r_9
+B6[4],!B6[6],!B7[5]	routing	sp4_v_b_3	sp4_v_t_38
+!B10[4],B10[6],B11[5]	routing	sp4_v_b_3	sp4_v_t_43
+B14[11],B14[13],!B15[12]	routing	sp4_v_b_3	sp4_v_t_46
+!B6[8],B6[9],!B6[10]	routing	sp4_v_b_4	sp4_h_l_41
+!B14[5],B15[4],!B15[6]	routing	sp4_v_b_4	sp4_h_l_44
+B12[8],B12[9],B12[10]	routing	sp4_v_b_4	sp4_h_r_10
+B4[8],B4[9],!B4[10]	routing	sp4_v_b_4	sp4_h_r_4
+B2[4],B2[6],!B3[5]	routing	sp4_v_b_4	sp4_v_t_37
+!B7[8],B7[9],!B7[10]	routing	sp4_v_b_4	sp4_v_t_41
+B11[8],!B11[9],B11[10]	routing	sp4_v_b_4	sp4_v_t_42
+B6[12],!B7[11],!B7[13]	routing	sp4_v_b_5	sp4_h_l_40
+!B14[8],!B14[9],B14[10]	routing	sp4_v_b_5	sp4_h_l_47
+B12[12],B13[11],B13[13]	routing	sp4_v_b_5	sp4_h_r_11
+B4[12],B5[11],!B5[13]	routing	sp4_v_b_5	sp4_h_r_5
+!B3[8],B3[9],B3[10]	routing	sp4_v_b_5	sp4_v_t_36
+!B6[11],B6[13],!B7[12]	routing	sp4_v_b_5	sp4_v_t_40
+B10[11],!B10[13],B11[12]	routing	sp4_v_b_5	sp4_v_t_45
+B10[5],!B11[4],!B11[6]	routing	sp4_v_b_6	sp4_h_l_43
+!B14[12],!B15[11],B15[13]	routing	sp4_v_b_6	sp4_h_l_46
+B0[5],B1[4],B1[6]	routing	sp4_v_b_6	sp4_h_r_0
+B8[5],!B9[4],B9[6]	routing	sp4_v_b_6	sp4_h_r_6
+B2[11],B2[13],!B3[12]	routing	sp4_v_b_6	sp4_v_t_39
+B10[4],!B10[6],!B11[5]	routing	sp4_v_b_6	sp4_v_t_43
+!B14[4],B14[6],B15[5]	routing	sp4_v_b_6	sp4_v_t_44
+!B2[5],B3[4],!B3[6]	routing	sp4_v_b_7	sp4_h_l_37
+!B10[8],B10[9],!B10[10]	routing	sp4_v_b_7	sp4_h_l_42
+B0[8],B0[9],B0[10]	routing	sp4_v_b_7	sp4_h_r_1
+B8[8],B8[9],!B8[10]	routing	sp4_v_b_7	sp4_h_r_7
+B6[4],B6[6],!B7[5]	routing	sp4_v_b_7	sp4_v_t_38
+!B11[8],B11[9],!B11[10]	routing	sp4_v_b_7	sp4_v_t_42
+B15[8],!B15[9],B15[10]	routing	sp4_v_b_7	sp4_v_t_47
+!B2[8],!B2[9],B2[10]	routing	sp4_v_b_8	sp4_h_l_36
+B10[12],!B11[11],!B11[13]	routing	sp4_v_b_8	sp4_h_l_45
+B0[12],B1[11],B1[13]	routing	sp4_v_b_8	sp4_h_r_2
+B8[12],B9[11],!B9[13]	routing	sp4_v_b_8	sp4_h_r_8
+!B7[8],B7[9],B7[10]	routing	sp4_v_b_8	sp4_v_t_41
+!B10[11],B10[13],!B11[12]	routing	sp4_v_b_8	sp4_v_t_45
+B14[11],!B14[13],B15[12]	routing	sp4_v_b_8	sp4_v_t_46
+!B2[12],!B3[11],B3[13]	routing	sp4_v_b_9	sp4_h_l_39
+B14[5],!B15[4],!B15[6]	routing	sp4_v_b_9	sp4_h_l_44
+B4[5],B5[4],B5[6]	routing	sp4_v_b_9	sp4_h_r_3
+B12[5],!B13[4],B13[6]	routing	sp4_v_b_9	sp4_h_r_9
+!B2[4],B2[6],B3[5]	routing	sp4_v_b_9	sp4_v_t_37
+B6[11],B6[13],!B7[12]	routing	sp4_v_b_9	sp4_v_t_40
+B14[4],!B14[6],!B15[5]	routing	sp4_v_b_9	sp4_v_t_44
+B10[8],B10[9],B10[10]	routing	sp4_v_t_36	sp4_h_l_42
+!B0[8],B0[9],!B0[10]	routing	sp4_v_t_36	sp4_h_r_1
+!B8[5],B9[4],!B9[6]	routing	sp4_v_t_36	sp4_h_r_6
+!B1[8],B1[9],!B1[10]	routing	sp4_v_t_36	sp4_v_b_1
+B5[8],!B5[9],B5[10]	routing	sp4_v_t_36	sp4_v_b_4
+B12[4],B12[6],!B13[5]	routing	sp4_v_t_36	sp4_v_b_9
+B2[5],!B3[4],B3[6]	routing	sp4_v_t_37	sp4_h_l_37
+B10[5],B11[4],B11[6]	routing	sp4_v_t_37	sp4_h_l_43
+!B4[12],!B5[11],B5[13]	routing	sp4_v_t_37	sp4_h_r_5
+B0[4],!B0[6],!B1[5]	routing	sp4_v_t_37	sp4_v_b_0
+!B4[4],B4[6],B5[5]	routing	sp4_v_t_37	sp4_v_b_3
+B8[11],B8[13],!B9[12]	routing	sp4_v_t_37	sp4_v_b_8
+B6[5],!B7[4],B7[6]	routing	sp4_v_t_38	sp4_h_l_38
+B14[5],B15[4],B15[6]	routing	sp4_v_t_38	sp4_h_l_44
+B4[5],!B5[4],!B5[6]	routing	sp4_v_t_38	sp4_h_r_3
+!B8[12],!B9[11],B9[13]	routing	sp4_v_t_38	sp4_h_r_8
+B12[11],B12[13],!B13[12]	routing	sp4_v_t_38	sp4_v_b_11
+B4[4],!B4[6],!B5[5]	routing	sp4_v_t_38	sp4_v_b_3
+!B8[4],B8[6],B9[5]	routing	sp4_v_t_38	sp4_v_b_6
+B2[12],B3[11],!B3[13]	routing	sp4_v_t_39	sp4_h_l_39
+B10[12],B11[11],B11[13]	routing	sp4_v_t_39	sp4_h_l_45
+B0[12],!B1[11],!B1[13]	routing	sp4_v_t_39	sp4_h_r_2
+!B8[8],!B8[9],B8[10]	routing	sp4_v_t_39	sp4_h_r_7
+!B13[8],B13[9],B13[10]	routing	sp4_v_t_39	sp4_v_b_10
+!B0[11],B0[13],!B1[12]	routing	sp4_v_t_39	sp4_v_b_2
+B4[11],!B4[13],B5[12]	routing	sp4_v_t_39	sp4_v_b_5
+B6[12],B7[11],!B7[13]	routing	sp4_v_t_40	sp4_h_l_40
+B14[12],B15[11],B15[13]	routing	sp4_v_t_40	sp4_h_l_46
+!B12[8],!B12[9],B12[10]	routing	sp4_v_t_40	sp4_h_r_10
+B4[12],!B5[11],!B5[13]	routing	sp4_v_t_40	sp4_h_r_5
+!B1[8],B1[9],B1[10]	routing	sp4_v_t_40	sp4_v_b_1
+!B4[11],B4[13],!B5[12]	routing	sp4_v_t_40	sp4_v_b_5
+B8[11],!B8[13],B9[12]	routing	sp4_v_t_40	sp4_v_b_8
+B6[8],B6[9],!B6[10]	routing	sp4_v_t_41	sp4_h_l_41
+B14[8],B14[9],B14[10]	routing	sp4_v_t_41	sp4_h_l_47
+!B4[8],B4[9],!B4[10]	routing	sp4_v_t_41	sp4_h_r_4
+!B12[5],B13[4],!B13[6]	routing	sp4_v_t_41	sp4_h_r_9
+B0[4],B0[6],!B1[5]	routing	sp4_v_t_41	sp4_v_b_0
+!B5[8],B5[9],!B5[10]	routing	sp4_v_t_41	sp4_v_b_4
+B9[8],!B9[9],B9[10]	routing	sp4_v_t_41	sp4_v_b_7
+B2[8],B2[9],B2[10]	routing	sp4_v_t_42	sp4_h_l_36
+B10[8],B10[9],!B10[10]	routing	sp4_v_t_42	sp4_h_l_42
+!B0[5],B1[4],!B1[6]	routing	sp4_v_t_42	sp4_h_r_0
+!B8[8],B8[9],!B8[10]	routing	sp4_v_t_42	sp4_h_r_7
+B13[8],!B13[9],B13[10]	routing	sp4_v_t_42	sp4_v_b_10
+B4[4],B4[6],!B5[5]	routing	sp4_v_t_42	sp4_v_b_3
+!B9[8],B9[9],!B9[10]	routing	sp4_v_t_42	sp4_v_b_7
+B2[5],B3[4],B3[6]	routing	sp4_v_t_43	sp4_h_l_37
+B10[5],!B11[4],B11[6]	routing	sp4_v_t_43	sp4_h_l_43
+!B12[12],!B13[11],B13[13]	routing	sp4_v_t_43	sp4_h_r_11
+B8[5],!B9[4],!B9[6]	routing	sp4_v_t_43	sp4_h_r_6
+B0[11],B0[13],!B1[12]	routing	sp4_v_t_43	sp4_v_b_2
+B8[4],!B8[6],!B9[5]	routing	sp4_v_t_43	sp4_v_b_6
+!B12[4],B12[6],B13[5]	routing	sp4_v_t_43	sp4_v_b_9
+B6[5],B7[4],B7[6]	routing	sp4_v_t_44	sp4_h_l_38
+!B0[12],!B1[11],B1[13]	routing	sp4_v_t_44	sp4_h_r_2
+B12[5],!B13[4],!B13[6]	routing	sp4_v_t_44	sp4_h_r_9
+!B0[4],B0[6],B1[5]	routing	sp4_v_t_44	sp4_v_b_0
+B4[11],B4[13],!B5[12]	routing	sp4_v_t_44	sp4_v_b_5
+B12[4],!B12[6],!B13[5]	routing	sp4_v_t_44	sp4_v_b_9
+B2[12],B3[11],B3[13]	routing	sp4_v_t_45	sp4_h_l_39
+B10[12],B11[11],!B11[13]	routing	sp4_v_t_45	sp4_h_l_45
+!B0[8],!B0[9],B0[10]	routing	sp4_v_t_45	sp4_h_r_1
+B8[12],!B9[11],!B9[13]	routing	sp4_v_t_45	sp4_h_r_8
+B12[11],!B12[13],B13[12]	routing	sp4_v_t_45	sp4_v_b_11
+!B5[8],B5[9],B5[10]	routing	sp4_v_t_45	sp4_v_b_4
+!B8[11],B8[13],!B9[12]	routing	sp4_v_t_45	sp4_v_b_8
+B6[12],B7[11],B7[13]	routing	sp4_v_t_46	sp4_h_l_40
+B14[12],B15[11],!B15[13]	routing	sp4_v_t_46	sp4_h_l_46
+B12[12],!B13[11],!B13[13]	routing	sp4_v_t_46	sp4_h_r_11
+!B4[8],!B4[9],B4[10]	routing	sp4_v_t_46	sp4_h_r_4
+!B12[11],B12[13],!B13[12]	routing	sp4_v_t_46	sp4_v_b_11
+B0[11],!B0[13],B1[12]	routing	sp4_v_t_46	sp4_v_b_2
+!B9[8],B9[9],B9[10]	routing	sp4_v_t_46	sp4_v_b_7
+B6[8],B6[9],B6[10]	routing	sp4_v_t_47	sp4_h_l_41
+B14[8],B14[9],!B14[10]	routing	sp4_v_t_47	sp4_h_l_47
+!B12[8],B12[9],!B12[10]	routing	sp4_v_t_47	sp4_h_r_10
+!B4[5],B5[4],!B5[6]	routing	sp4_v_t_47	sp4_h_r_3
+B1[8],!B1[9],B1[10]	routing	sp4_v_t_47	sp4_v_b_1
+!B13[8],B13[9],!B13[10]	routing	sp4_v_t_47	sp4_v_b_10
+B8[4],B8[6],!B9[5]	routing	sp4_v_t_47	sp4_v_b_6
+"""