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| author | David Williams <david@davidthings.com> | 2021-02-05 07:35:50 -0800 |
|---|---|---|
| committer | David Williams <david@davidthings.com> | 2021-02-05 07:35:50 -0800 |
| commit | e368f15a7f71fcd066318400b7867b5d1595ae39 (patch) | |
| tree | c7ac525d0bf2c84c4cbacfc26af1a6bab0745fbd /icepll | |
| parent | 7afc64b480212c9ac2ce7cb1622731a69a7d212c (diff) | |
| download | icestorm-e368f15a7f71fcd066318400b7867b5d1595ae39.tar.gz icestorm-e368f15a7f71fcd066318400b7867b5d1595ae39.tar.bz2 icestorm-e368f15a7f71fcd066318400b7867b5d1595ae39.zip | |
Add an option (-p) to force use of SB_PLL40_PAD
When a clock is applied to a dedicated clock pin, SB_PLL40_CORE is no longer the correct primitive to use.
Also the name of the clock input must be PACKAGEPIN (rather than REFERENCECLK)
Diffstat (limited to 'icepll')
| -rw-r--r-- | icepll/icepll.cc | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/icepll/icepll.cc b/icepll/icepll.cc index 398b545..b27d184 100644 --- a/icepll/icepll.cc +++ b/icepll/icepll.cc @@ -48,6 +48,9 @@ void help(const char *cmd) printf(" -o <output_freq_mhz>\n"); printf(" PLL Output Frequency (default: 60 MHz)\n"); printf("\n"); + printf(" -p\n"); + printf(" Clock source is an input pad rather than FPGA routing\n"); + printf("\n"); printf(" -S\n"); printf(" Disable SIMPLE feedback path mode\n"); printf("\n"); @@ -204,6 +207,7 @@ int main(int argc, char **argv) double f_pllin = 12; double f_pllout = 60; + bool pad = false; bool simple_feedback = true; const char* filename = NULL; bool file_stdout = false; @@ -214,7 +218,7 @@ int main(int argc, char **argv) bool quiet = false; int opt; - while ((opt = getopt(argc, argv, "i:o:Smf:n:bB:q")) != -1) + while ((opt = getopt(argc, argv, "i:o:pSmf:n:bB:q")) != -1) { switch (opt) { @@ -224,6 +228,9 @@ int main(int argc, char **argv) case 'o': f_pllout = atof(optarg); break; + case 'p': + pad = true; + break; case 'S': simple_feedback = false; break; @@ -395,7 +402,7 @@ int main(int argc, char **argv) ); // save iCE40 PLL tile configuration - fprintf(f, "SB_PLL40_CORE #(\n"); + fprintf(f, "%s #(\n", (pad ? "SB_PLL40_PAD" : "SB_PLL40_CORE")); fprintf(f, "\t\t.FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE")); fprintf(f, "\t\t.DIVR(4'b%s),\t\t" "// DIVR = %2d\n", binstr(best_divr, 4), best_divr); fprintf(f, "\t\t.DIVF(7'b%s),\t" "// DIVF = %2d\n", binstr(best_divf, 7), best_divf); @@ -405,9 +412,9 @@ int main(int argc, char **argv) "\t\t.LOCK(locked),\n" "\t\t.RESETB(1'b1),\n" "\t\t.BYPASS(1'b0),\n" - "\t\t.REFERENCECLK(clock_in),\n" + "\t\t.%s(clock_in),\n" "\t\t.PLLOUTCORE(clock_out)\n" - "\t\t);\n\n" + "\t\t);\n\n", (pad ? "PACKAGEPIN":"REFERENCECLK") ); fprintf(f, "endmodule\n"); |