icetime progress

2 files changed, 93 insertions, 19 deletions

diff --git a/icetime/icetime.cc b/icetime/icetime.cc
index e6f1167..e0c3df7 100644
--- a/icetime/icetime.cc
+++ b/icetime/icetime.cc
@@ -56,12 +56,16 @@ int iconn_cell_cnt = 0;
 
 // netlist_cells[cell_name][port_name] = port_expr
 std::map<std::string, std::map<std::string, std::string>> netlist_cells;
+std::map<std::string, std::map<std::string, std::string>> netlist_cell_params;
 std::map<std::string, std::string> netlist_cell_types;
 
 std::set<std::string> extra_wires;
 std::vector<std::string> extra_vlog;
 std::set<int> declared_nets;
 
+std::map<std::string, std::vector<std::pair<int, int>>> logic_tile_bits,
+		io_tile_bits, ramb_tile_bits, ramt_tile_bits;
+
 std::string vstringf(const char *fmt, va_list ap)
 {
 	std::string string;
@@ -331,6 +335,27 @@ void read_chipdb()
 				gbufpin.push_back(items);
 		}
 
+		if (mode == ".logic_tile_bits" || mode == ".io_tile_bits" || mode == ".ramb_tile_bits" || mode == ".ramt_tile_bits") {
+			std::vector<std::pair<int, int>> items;
+			while (1) {
+				const char *s = strtok(nullptr, " \t\r\n");
+				if (s == nullptr)
+					break;
+				std::pair<int, int> item;
+				int rc = sscanf(s, "B%d[%d]", &item.first, &item.second);
+				assert(rc == 2);
+				items.push_back(item);
+			}
+			if (mode == ".logic_tile_bits")
+				logic_tile_bits[tok] = items;
+			if (mode == ".io_tile_bits")
+				io_tile_bits[tok] = items;
+			if (mode == ".ramb_tile_bits")
+				ramb_tile_bits[tok] = items;
+			if (mode == ".ramt_tile_bits")
+				ramt_tile_bits[tok] = items;
+		}
+
 		if (mode == ".extra_bits") {
 			int b = atoi(strtok(nullptr, " \t\r\n"));
 			int x = atoi(strtok(nullptr, " \t\r\n"));
@@ -453,6 +478,20 @@ std::string make_seg_pre_io(int x, int y, int z)
 	netlist_cells[cell]["DIN1"] = "";
 	netlist_cells[cell]["DIN0"] = "";
 
+	std::string pintype;
+	std::pair<int, int> bitpos;
+
+	for (int i = 0; i < 6; i++) {
+		bitpos = io_tile_bits[stringf("IOB_%d.PINTYPE_%d", z, 5-i)][0];
+		pintype.push_back(config_bits[x][y][bitpos.first][bitpos.second] ? '1' : '0');
+	}
+
+	bitpos = io_tile_bits["NegClk"][0];
+	char negclk = config_bits[x][y][bitpos.first][bitpos.second] ? '1' : '0';
+
+	netlist_cell_params[cell]["NEG_TRIGGER"] = stringf("1'b%c", negclk);
+	netlist_cell_params[cell]["PIN_TYPE"] = stringf("6'b%s", pintype.c_str());
+
 	std::string io_name;
 	std::tuple<int, int, int> key(x, y, z);
 
@@ -498,6 +537,21 @@ std::string make_lc40(int x, int y, int z)
 	netlist_cells[cell]["lcout"] = "";
 	netlist_cells[cell]["ltout"] = "";
 
+	char lcbits[20];
+	auto &lcbits_pos = logic_tile_bits[stringf("LC_%d", z)];
+
+	for (int i = 0; i < 20; i++)
+		lcbits[i] = config_bits[x][y][lcbits_pos[i].first][lcbits_pos[i].second] ? '1' : '0';
+
+	// FIXME: fill in the '0'
+	netlist_cell_params[cell]["C_ON"] = stringf("1'b%c", '0');
+	netlist_cell_params[cell]["SEQ_MODE"] = stringf("4'b%c%c%c%c", lcbits[9], '0', '0', '0');
+	netlist_cell_params[cell]["LUT_INIT"] = stringf("16'b%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+			lcbits[0], lcbits[10], lcbits[11], lcbits[1],
+			lcbits[2], lcbits[12], lcbits[13], lcbits[3],
+			lcbits[7], lcbits[17], lcbits[16], lcbits[6],
+			lcbits[5], lcbits[15], lcbits[14], lcbits[4]);
+
 	return cell;
 }
 
@@ -617,6 +671,13 @@ void make_seg_cell(int net, const net_segment_t &seg)
 		return;
 	}
 
+	if (sscanf(seg.name.c_str(), "lutff_%d/cou%c", &a, &c) == 2 && c == 't')
+	{
+		auto cell = make_lc40(seg.x, seg.y, a);
+		netlist_cells[cell]["carryout"] = net_name(net);
+		return;
+	}
+
 	if (seg.name == "lutff_global/clk")
 	{
 		for (int i = 0; i < 8; i++)
@@ -958,7 +1019,17 @@ int main(int argc, char **argv)
 
 	for (auto it : netlist_cell_types) {
 		const char *sep = "";
-		fprintf(fout, "  %s %s (", it.second.c_str(), it.first.c_str());
+		fprintf(fout, "  %s ", it.second.c_str());
+		if (netlist_cell_params.count(it.first)) {
+			fprintf(fout, "#(");
+			for (auto port : netlist_cell_params[it.first]) {
+				fprintf(fout, "%s\n    .%s(%s)", sep, port.first.c_str(), port.second.c_str());
+				sep = ",";
+			}
+			fprintf(fout, "\n  ) ");
+			sep = "";
+		}
+		fprintf(fout, "%s (", it.first.c_str());
 		for (auto port : netlist_cells[it.first]) {
 			fprintf(fout, "%s\n    .%s(%s)", sep, port.first.c_str(), port.second.c_str());
 			sep = ",";
diff --git a/icetime/mktest.py b/icetime/mktest.py
index a2a1e0c..5d888f4 100644
--- a/icetime/mktest.py
+++ b/icetime/mktest.py
@@ -10,24 +10,30 @@ pins = np.random.permutation("""
     112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144
 """.split())
 
+io_names = None
+mode = "test0" # sys.argv[1]
+
 with open("%s.v" % sys.argv[1], "w") as f:
-    print("module top(input clk, i0, i1, i2, i3, output o0, o1, o2, o3);", file=f)
-    print("  reg [15:0] din, dout;", file=f)
-    print("  always @(posedge clk) din <= {din, i3, i2, i1, i0};", file=f)
-    print("  always @(posedge clk) dout <= din + {din[7:0], din[15:8]};", file=f)
-    print("  assign {o3, o2, o1, o0} = dout >> din;", file=f)
-    print("endmodule", file=f)
+    if mode == "test0":
+        io_names = [ "clk", "i0", "o0", "o1", "o2" ]
+        print("module top(input clk, i0, output o0, o1, o2);", file=f)
+        print("  reg [3:0] state;", file=f)
+        # print("  always @(posedge clk) state <= (state << 7) ^ (state >> 13) ^ i0;", file=f)
+        print("  always @(posedge clk) state <= (state << 1) ^ i0;", file=f)
+        print("  assign o0 = ^state, o1 = |state, o2 = &state;", file=f)
+        print("endmodule", file=f)
+    if mode == "test1":
+        io_names = [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3" ]
+        print("module top(input clk, i0, i1, i2, i3, output o0, o1, o2, o3);", file=f)
+        print("  reg [15:0] din, dout;", file=f)
+        print("  always @(posedge clk) din <= {din, i3, i2, i1, i0};", file=f)
+        print("  always @(posedge clk) dout <= din + {din[7:0], din[15:8]};", file=f)
+        print("  assign {o3, o2, o1, o0} = dout >> din;", file=f)
+        print("endmodule", file=f)
 
 with open("%s.pcf" % sys.argv[1], "w") as f:
-    print("set_io clk %s" % pins[0], file=f)
-    print("set_io i0 %s" % pins[1], file=f)
-    print("set_io i1 %s" % pins[2], file=f)
-    print("set_io i2 %s" % pins[3], file=f)
-    print("set_io i3 %s" % pins[4], file=f)
-    print("set_io o0 %s" % pins[5], file=f)
-    print("set_io o1 %s" % pins[6], file=f)
-    print("set_io o2 %s" % pins[7], file=f)
-    print("set_io o3 %s" % pins[8], file=f)
+    for i, name in enumerate(io_names):
+        print("set_io %s %s" % (name, pins[i]), file=f)
 
 with open("%s.ys" % sys.argv[1], "w") as f:
     print("echo on", file=f)
@@ -48,9 +54,6 @@ os.rename("%s.v" % sys.argv[1], "%s_in.v" % sys.argv[1])
 
 with open("%s_ref.v" % sys.argv[1], "w") as f:
     for line in open("%s.vsb" % sys.argv[1], "r"):
-        if line.find("defparam") >= 0:
-            continue
-
         line = line.replace(" Span4Mux_s0_h ",   " Span4Mux_h0 ")  # " Span4Mux_h0 ")
         line = line.replace(" Span4Mux_s1_h ",   " Span4Mux_h0 ")  # " Span4Mux_h1 ")
         line = line.replace(" Span4Mux_s2_h ",   " Span4Mux_h0 ")  # " Span4Mux_h2 ")