diff options
Diffstat (limited to 'icefuzz/tests/sb_pll40_core.v')
| -rw-r--r-- | icefuzz/tests/sb_pll40_core.v | 24 |
1 files changed, 7 insertions, 17 deletions
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_core.v index 298fb73..9954eca 100644 --- a/icefuzz/tests/sb_pll40_core.v +++ b/icefuzz/tests/sb_pll40_core.v @@ -1,7 +1,7 @@ module top( input REFERENCECLK, - output [1:0] PLLOUTCORE, - output [1:0] PLLOUTGLOBAL, + output PLLOUTCORE, + output PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, @@ -14,7 +14,7 @@ module top( input SDI, input SCLK ); - SB_PLL40_2F_CORE #( + SB_PLL40_CORE #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), @@ -26,10 +26,7 @@ module top( .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), - .PLLOUT_SELECT_PORTA("GENCLK"), - .PLLOUT_SELECT_PORTB("GENCLK"), - - // .PLLOUT_SELECT("GENCLK"), + .PLLOUT_SELECT("GENCLK"), // .PLLOUT_SELECT("GENCLK_HALF"), // .PLLOUT_SELECT("SHIFTREG_90deg"), // .PLLOUT_SELECT("SHIFTREG_0deg"), @@ -41,19 +38,12 @@ module top( .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), - // .ENABLE_ICEGATE(1'b0), - .ENABLE_ICEGATE_PORTA(1'b0), - .ENABLE_ICEGATE_PORTB(1'b0), + .ENABLE_ICEGATE(1'b0), .TEST_MODE(1'b0) ) uut ( .REFERENCECLK (REFERENCECLK ), - // .PACKAGEPIN (REFERENCECLK ), - // .PLLOUTCORE (PLLOUTCORE ), - // .PLLOUTGLOBAL (PLLOUTGLOBAL ), - .PLLOUTCOREA (PLLOUTCORE [0]), - .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), - .PLLOUTCOREB (PLLOUTCORE [1]), - .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), + .PLLOUTCORE (PLLOUTCORE ), + .PLLOUTGLOBAL (PLLOUTGLOBAL ), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), |