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* | Add BeagleWire linkClifford Wolf2017-11-191-0/+1
| * Merge branch 'master' into up5kDavid Shah2017-11-188-13/+44
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* | Merge commit '05440e4'Clifford Wolf2017-11-187-12/+43
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| * | Fix up build system to work with emscriptenRobert Ou2017-11-157-12/+43
* | | Update udev rule in docs/index.htmlClifford Wolf2017-11-181-1/+1
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| * Add all cf_bits and pullup strength notesDavid Shah2017-11-182-0/+27
| * Corrections and changes to UltraPlus docDavid Shah2017-11-181-12/+16
| * Merge branch 'master' into up5kDavid Shah2017-11-180-0/+0
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* | Merge pull request #107 from daveshah1/ultraplus_experimentsClifford Wolf2017-11-149-45/+1590
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| | * Add missing 5k BRAM bitsDavid Shah2017-11-174-7/+1277
| | * Make 5k db as a default targetDavid Shah2017-11-171-1/+2
| | * Remove non-existing routing resources (5k)David Shah2017-11-171-2/+3
| | * Add support for UltraPlus SPRAMDavid Shah2017-11-174-238/+496
| | * Add UltraPlus LED driver support and demoDavid Shah2017-11-176-11/+171
| | * UltraPlus Internal Oscillator supportDavid Shah2017-11-172-1/+34
| | * UltraPlus DSPs workingDavid Shah2017-11-175-1/+95
| | * Add new tile types and MAC16s to chipdbDavid Shah2017-11-172-4/+138
| | * Tidy up some of the icebox changesDavid Shah2017-11-171-44/+53
| | * 5k RGB driver reverse engineeredDavid Shah2017-11-174-0/+223
| | * Fix 5k corner routing, and reverse engineer SPRAMDavid Shah2017-11-175-20/+523
| | * Figure out DSP config bits for all locsDavid Shah2017-11-174-3/+184
| | * Start UltraPlus DSP documentationDavid Shah2017-11-173-2/+160
| | * Trace DSP routingDavid Shah2017-11-175-350/+6534
| | * Create icefuzz scripts for DSP and 5kDavid Shah2017-11-1713-986/+16479
| | * Preparations for DSP and IpCon fuzzingDavid Shah2017-11-089-10/+75
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| * Fix 5k gbin configurationDavid Shah2017-11-061-2/+2
| * Add more 5k RAM bits to dbDavid Shah2017-11-053-4/+1329
| * Fix 5k padin_glb_netwk bitsDavid Shah2017-11-051-8/+8
| * 5k-related fixes to icepackDavid Shah2017-11-051-22/+64
| * Add 5k colbuf fuzzing scriptsDavid Shah2017-11-024-0/+172
| * Fix global network 1 padin bitDavid Shah2017-11-011-2/+2
| * Work on 5k global buffer padsDavid Shah2017-11-011-8/+10
| * Fix BRAM initialisation on 5k partsDavid Shah2017-11-011-4/+5
| * Merge branch 'master' into ultraplus_experimentsDavid Shah2017-11-010-0/+0
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* | Merge branch 'daveshah1-u5k'Clifford Wolf2017-10-3125-125/+1286
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| | * Add missing up5k global buffer padsDavid Shah2017-10-311-1/+4
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| * Working up5k PLL supportDavid Shah2017-10-311-63/+61
| * Fix loading 5k asc filesDavid Shah2017-10-311-1/+1
| * PLL configuration fuzzing scriptDavid Shah2017-10-303-0/+316
| * Add new 5k IO config bits to databaseDavid Shah2017-10-291-3/+21
| * Share glb_netwk data between 5k and 8k partsDavid Shah2017-10-293-82/+101
| * Fix global network data for up5kDavid Shah2017-10-251-9/+9
| * Fix colbuf db for up5kDavid Shah2017-10-251-5/+7
| * Add ColBufCtrl bits to database for 5k partsDavid Shah2017-10-252-100/+76
| * Add CarryInSet bit to DBDavid Shah2017-10-241-0/+3
| * Add some verilog tests for analysing up5k featuresDavid Shah2017-10-238-0/+216
| * Fix IeRen database for up5kDavid Shah2017-10-234-97/+91
| * Swap IEREN for pin 26 to get example working, other inputs still need fixingDavid Shah2017-10-212-2/+73
| * Basic example, outputs work but inputs don'tDavid Shah2017-10-214-0/+53
| * Fix RAM tile location in icebox.pyDavid Shah2017-10-211-1/+1
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