iCE40/icestorm - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Remove seperate 5k RAM DB and share with 8k instead	David Shah	2018-01-16	1	-2838/+0
\| \| \| \| \|	This should ensure that the 5k RAM routing entries are now complete, fixing #115
*	Add missing 5k BRAM bits	David Shah	2017-11-17	1	-7/+338
\|
*	Trace DSP routing	David Shah	2017-11-17	1	-324/+6374
\|
*	Add more 5k RAM bits to db	David Shah	2017-11-05	1	-4/+86
\|
*	Share glb_netwk data between 5k and 8k parts	David Shah	2017-10-29	1	-72/+100
\|
*	Add ColBufCtrl bits to database for 5k parts	David Shah	2017-10-25	1	-100/+72
\|
*	Swap IEREN for pin 26 to get example working, other inputs still need fixing	David Shah	2017-10-21	1	-0/+71
\|
*	Modify icebox.py so it generates a 5k chipdb	David Shah	2017-10-20	1	-30/+378
\|
*	Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from database	Clifford Wolf	2017-07-31	1	-4/+0
\|
*	Work in progress DB. Having trouble getting group_segments to work without ↵	Scott Shawcroft	2017-07-07	1	-0/+2341
\| \| \| \|	error.
*	icefuzz improvements, refuzz timings	Clifford Wolf	2016-01-16	1	-0/+4
\|
*	Fuzzed RamCascade bits	Clifford Wolf	2016-01-09	1	-0/+8
\|
*	Added lutff_i/lout net to model	Clifford Wolf	2015-12-04	1	-7/+7
\|
*	Added 8k timing data	Clifford Wolf	2015-10-06	1	-0/+1
\|
*	more database updates	Clifford Wolf	2015-10-02	1	-0/+1
\|
*	database updates	Clifford Wolf	2015-09-27	1	-0/+3
\|
*	Imported full dev sources	Clifford Wolf	2015-07-18	1	-138/+2902
\|
*	Import of icestorm-snapshot-150526.zip	Clifford Wolf	2015-07-18	1	-0/+9
\|
*	Import of icestorm-snapshot-150413.zip	Clifford Wolf	2015-07-18	1	-73/+2496
\|
*	Import of icestorm-snapshot-150322.zip	Clifford Wolf	2015-07-18	1	-0/+2985