aboutsummaryrefslogtreecommitdiffstats
path: root/icebox
Commit message (Expand)AuthorAgeFilesLines
...
| * Completed first pass at icebox support for lm4k.Andrew Wygle2018-05-121-11/+14
| * [WIP] Added colbuf and gbufin data for LM seriesAndrew Wygle2018-05-121-8/+25
| * [WIP] Add partial icebox support for lm4k.Andrew Wygle2018-05-121-11/+242
* | Extact reproducable chipdb-5k.txtClifford Wolf2018-05-131-2/+2
|/
* Add BG121 package variant and update docsDavid Shah2018-04-021-0/+190
* Add UltraPlus I³C IO to chipdbDavid Shah2018-02-091-1/+10
* Add RGB driver outputs to chipdbDavid Shah2018-02-091-0/+4
* Add 5k UWG30 ieren data to dbDavid Shah2018-01-161-1/+5
* Remove seperate 5k RAM DB and share with 8k insteadDavid Shah2018-01-162-2849/+9
* Add pinout for 5k UWG30 packageDavid Shah2018-01-161-0/+23
* HFOSC trimming infoDavid Shah2018-01-161-1/+12
* New UltraPlus corner tracing algorithmDavid Shah2018-01-161-87/+86
* Misc routing tweaksDavid Shah2018-01-161-3/+7
* Figure out missing SPI config bits, and add to chipdbDavid Shah2018-01-161-0/+8
* Chipdb fix for hard IPDavid Shah2017-11-261-4/+4
* Add UltraPlus IP to chipdbDavid Shah2017-11-242-3/+212
* Begin I2C/SPI IP reverse engineeringDavid Shah2017-11-231-0/+8
* Fix whitespace and a couple of typosDavid Shah2017-11-201-3/+3
* Add all cf_bits and pullup strength notesDavid Shah2017-11-181-0/+12
* Add missing 5k BRAM bitsDavid Shah2017-11-171-7/+338
* Make 5k db as a default targetDavid Shah2017-11-171-1/+2
* Remove non-existing routing resources (5k)David Shah2017-11-171-2/+3
* Add support for UltraPlus SPRAMDavid Shah2017-11-172-1/+254
* Add UltraPlus LED driver support and demoDavid Shah2017-11-172-11/+39
* UltraPlus Internal Oscillator supportDavid Shah2017-11-172-1/+34
* UltraPlus DSPs workingDavid Shah2017-11-172-1/+8
* Add new tile types and MAC16s to chipdbDavid Shah2017-11-172-4/+138
* Tidy up some of the icebox changesDavid Shah2017-11-171-44/+53
* Fix 5k corner routing, and reverse engineer SPRAMDavid Shah2017-11-171-20/+93
* Start UltraPlus DSP documentationDavid Shah2017-11-172-2/+3
* Trace DSP routingDavid Shah2017-11-174-349/+6531
* Fix 5k gbin configurationDavid Shah2017-11-061-2/+2
* Add more 5k RAM bits to dbDavid Shah2017-11-051-4/+86
* Fix 5k padin_glb_netwk bitsDavid Shah2017-11-051-8/+8
* Fix global network 1 padin bitDavid Shah2017-11-011-2/+2
* Work on 5k global buffer padsDavid Shah2017-11-011-8/+10
* Add missing up5k global buffer padsDavid Shah2017-10-311-1/+4
* Working up5k PLL supportDavid Shah2017-10-311-63/+61
* Fix loading 5k asc filesDavid Shah2017-10-311-1/+1
* Add new 5k IO config bits to databaseDavid Shah2017-10-291-3/+21
* Share glb_netwk data between 5k and 8k partsDavid Shah2017-10-292-78/+101
* Fix global network data for up5kDavid Shah2017-10-251-9/+9
* Fix colbuf db for up5kDavid Shah2017-10-251-5/+7
* Add ColBufCtrl bits to database for 5k partsDavid Shah2017-10-251-100/+72
* Add CarryInSet bit to DBDavid Shah2017-10-241-0/+3
* Fix IeRen database for up5kDavid Shah2017-10-231-97/+40
* Swap IEREN for pin 26 to get example working, other inputs still need fixingDavid Shah2017-10-212-2/+73
* Fix RAM tile location in icebox.pyDavid Shah2017-10-211-1/+1
* Fix icebox to generate a working chipdbDavid Shah2017-10-211-4/+4
* Bring chip data in icebox in line with icepack - and icecubeDavid Shah2017-10-211-50/+50
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 01:19:04 +0000