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module top (
input clk,
output LED0,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7
);
localparam BITS = 3;
localparam LOG2DELAY = 20;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end
assign {LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} = 1 << outcnt;
endmodule
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