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authorgatecat <gatecat@ds0.me>2021-02-15 16:19:17 +0000
committerGitHub <noreply@github.com>2021-02-15 16:19:17 +0000
commitf16089b33b980703db5e11e80368b2248919652b (patch)
treeb3702e08795c33d1711d6fdcdd930a9530d0baf8
parent31648368460b9e216479ce7c38e6fed883c380c4 (diff)
parent7673d60124707346de001367afcbab6be466f405 (diff)
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Merge pull request #4 from YosysHQ/gatecat/generic-belpin
generic: Add test of bel pin mapping
-rw-r--r--generic/flow/.gitignore4
-rw-r--r--generic/flow/bel-pin/design.v7
-rw-r--r--generic/flow/bel-pin/post_route.py2
-rw-r--r--generic/flow/bel-pin/pre_pack.py21
-rwxr-xr-xgeneric/flow/bel-pin/run.sh4
-rwxr-xr-xgeneric/flow/run.sh2
6 files changed, 40 insertions, 0 deletions
diff --git a/generic/flow/.gitignore b/generic/flow/.gitignore
new file mode 100644
index 0000000..f179590
--- /dev/null
+++ b/generic/flow/.gitignore
@@ -0,0 +1,4 @@
+*.pyc
+*.json
+*.fasm
+*.log
diff --git a/generic/flow/bel-pin/design.v b/generic/flow/bel-pin/design.v
new file mode 100644
index 0000000..bcec0be
--- /dev/null
+++ b/generic/flow/bel-pin/design.v
@@ -0,0 +1,7 @@
+(* blackbox *)
+module TEST_BEL(input wire A, output wire Q);
+endmodule
+
+module top(output wire q);
+TEST_BEL cell_i(.A(q), .Q(q));
+endmodule
diff --git a/generic/flow/bel-pin/post_route.py b/generic/flow/bel-pin/post_route.py
new file mode 100644
index 0000000..9243c1b
--- /dev/null
+++ b/generic/flow/bel-pin/post_route.py
@@ -0,0 +1,2 @@
+assert "BEL_A0" in ctx.nets["q"].wires
+assert "BEL_A1" in ctx.nets["q"].wires
diff --git a/generic/flow/bel-pin/pre_pack.py b/generic/flow/bel-pin/pre_pack.py
new file mode 100644
index 0000000..2ee06d6
--- /dev/null
+++ b/generic/flow/bel-pin/pre_pack.py
@@ -0,0 +1,21 @@
+ctx.addWire(name="BEL_A0", type="WIRE", x=0, y=0)
+ctx.addWire(name="BEL_A1", type="WIRE", x=0, y=0)
+ctx.addWire(name="BEL_Q", type="WIRE", x=0, y=0)
+ctx.addWire(name="SLICE_F", type="WIRE", x=0, y=0)
+
+ctx.addPip(name="Q->A0", type="PIP", srcWire="BEL_Q", dstWire="BEL_A0", delay=ctx.getDelayFromNS(0.05), loc=Loc(0, 0, 0))
+ctx.addPip(name="Q->A1", type="PIP", srcWire="BEL_Q", dstWire="BEL_A1", delay=ctx.getDelayFromNS(0.05), loc=Loc(0, 0, 0))
+
+ctx.addBel(name="BEL", type="TEST_BEL", loc=Loc(0, 0, 0), gb=False, hidden=False)
+
+ctx.addBelInput(bel="BEL", name="A0", wire="BEL_A0")
+ctx.addBelInput(bel="BEL", name="A1", wire="BEL_A1")
+ctx.addBelOutput(bel="BEL", name="Q", wire="BEL_Q")
+
+ctx.addBel(name="DUMMY_SLICE", type="GENERIC_SLICE", loc=Loc(0, 0, 1), gb=False, hidden=False)
+ctx.addBelOutput(bel="DUMMY_SLICE", name="F", wire="SLICE_F")
+
+
+ctx.clearCellBelPinMap(cell="cell_i", cell_pin="A")
+ctx.addCellBelPinMapping(cell="cell_i", cell_pin="A", bel_pin="A0")
+ctx.addCellBelPinMapping(cell="cell_i", cell_pin="A", bel_pin="A1")
diff --git a/generic/flow/bel-pin/run.sh b/generic/flow/bel-pin/run.sh
new file mode 100755
index 0000000..b599297
--- /dev/null
+++ b/generic/flow/bel-pin/run.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -ex
+yosys -q -p "prep; write_json design.json" design.v
+$NPNR --json design.json --pre-pack pre_pack.py --post-route post_route.py --no-iobs
diff --git a/generic/flow/run.sh b/generic/flow/run.sh
new file mode 100755
index 0000000..1d60c4c
--- /dev/null
+++ b/generic/flow/run.sh
@@ -0,0 +1,2 @@
+#!/usr/bin/env bash
+cd bel-pin && bash run.sh