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| author | gatecat <gatecat@ds0.me> | 2021-06-11 08:38:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-11 08:38:24 +0100 |
| commit | 0a27601c817abbbaf230708ffc0daee5ef6fec61 (patch) | |
| tree | 0ffca21f055ae8b271561344425d1ee75cabd2b5 /fpga_interchange/site_router_tests/common/synth.tcl | |
| parent | 1cc7ee785957c14f83b89d6bf18f14d072e6312e (diff) | |
| parent | 1cd2901d854b969a8cb1afc66e3f3388766776a0 (diff) | |
| download | nextpnr-tests-0a27601c817abbbaf230708ffc0daee5ef6fec61.tar.gz nextpnr-tests-0a27601c817abbbaf230708ffc0daee5ef6fec61.tar.bz2 nextpnr-tests-0a27601c817abbbaf230708ffc0daee5ef6fec61.zip | |
Merge pull request #10 from antmicro/site_router_test_framework
fpga_interchange: Add initial site router test framework
Diffstat (limited to 'fpga_interchange/site_router_tests/common/synth.tcl')
| -rw-r--r-- | fpga_interchange/site_router_tests/common/synth.tcl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga_interchange/site_router_tests/common/synth.tcl b/fpga_interchange/site_router_tests/common/synth.tcl new file mode 100644 index 0000000..cba4503 --- /dev/null +++ b/fpga_interchange/site_router_tests/common/synth.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -flatten -abc9 -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) |