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| author | Tomasz Michalak <tmichalak@antmicro.com> | 2021-06-09 23:01:27 +0200 |
|---|---|---|
| committer | Tomasz Michalak <tmichalak@antmicro.com> | 2021-06-10 12:06:04 +0200 |
| commit | 1cd2901d854b969a8cb1afc66e3f3388766776a0 (patch) | |
| tree | 08d7000a9368b13812f2c5a89cb696e0eaebdc2f /fpga_interchange/site_router_tests/lut/test.yaml | |
| parent | caf7261be7b34b365ab6d8449455891c2ed28faa (diff) | |
| download | nextpnr-tests-1cd2901d854b969a8cb1afc66e3f3388766776a0.tar.gz nextpnr-tests-1cd2901d854b969a8cb1afc66e3f3388766776a0.tar.bz2 nextpnr-tests-1cd2901d854b969a8cb1afc66e3f3388766776a0.zip | |
fpga_interchange: Add initial site router test framework
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Diffstat (limited to 'fpga_interchange/site_router_tests/lut/test.yaml')
| -rw-r--r-- | fpga_interchange/site_router_tests/lut/test.yaml | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/fpga_interchange/site_router_tests/lut/test.yaml b/fpga_interchange/site_router_tests/lut/test.yaml new file mode 100644 index 0000000..e299d81 --- /dev/null +++ b/fpga_interchange/site_router_tests/lut/test.yaml @@ -0,0 +1,28 @@ +test_case: + - place: + # Place cell `lut_2` at BEL `SLICE_X1Y8.SLICEL/A6LUT` + lut_1: SLICE_X1Y8.SLICEL/A6LUT + - test: + # Make sure this placement is accept + SLICE_X1Y8.SLICEL/A6LUT: true + - unplace: + SLICE_X1Y8.SLICEL/A6LUT + # - place: + # lut_1: SLICE_X1Y8.SLICEL/B6LUT + # - test: + # # Make sure this placement is accept + # SLICE_X1Y8.SLICEL/A6LUT: true + # SLICE_X1Y8.SLICEL/B6LUT: true + # - place: + # lut_1: SLICE_X1Y8.SLICEL/A6LUT + # lut_2: SLICE_X1Y8.SLICEL/A5LUT + # - test: + # # The site is now invalid because too many signals into the A6/A5LUT + # SLICE_X1Y8.SLICEL/A6LUT: false + # SLICE_X1Y8.SLICEL/A5LUT: false + # - unplace: + # - lut_2 + # - test: + # # By removing lut_2, the site is valid again + # SLICE_X1Y8.SLICEL/A6LUT: true + # SLICE_X1Y8.SLICEL/A5LUT: true |