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| author | gatecat <gatecat@ds0.me> | 2021-02-17 10:22:12 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-02-17 10:22:12 +0000 |
| commit | 2aa02a28d4078c616d96400973d3b5e4cf1e454c (patch) | |
| tree | 209494e91cac21410ac277f26e3c6f68f4599e17 /generic/flow | |
| parent | 6d010ef07edb383f9caba9498cdec8b13fff03a6 (diff) | |
| download | nextpnr-tests-2aa02a28d4078c616d96400973d3b5e4cf1e454c.tar.gz nextpnr-tests-2aa02a28d4078c616d96400973d3b5e4cf1e454c.tar.bz2 nextpnr-tests-2aa02a28d4078c616d96400973d3b5e4cf1e454c.zip | |
Remove dummy slice from bel-pin generic test
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'generic/flow')
| -rw-r--r-- | generic/flow/bel-pin/pre_pack.py | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/generic/flow/bel-pin/pre_pack.py b/generic/flow/bel-pin/pre_pack.py index 2ee06d6..31ddbe9 100644 --- a/generic/flow/bel-pin/pre_pack.py +++ b/generic/flow/bel-pin/pre_pack.py @@ -1,7 +1,6 @@ ctx.addWire(name="BEL_A0", type="WIRE", x=0, y=0) ctx.addWire(name="BEL_A1", type="WIRE", x=0, y=0) ctx.addWire(name="BEL_Q", type="WIRE", x=0, y=0) -ctx.addWire(name="SLICE_F", type="WIRE", x=0, y=0) ctx.addPip(name="Q->A0", type="PIP", srcWire="BEL_Q", dstWire="BEL_A0", delay=ctx.getDelayFromNS(0.05), loc=Loc(0, 0, 0)) ctx.addPip(name="Q->A1", type="PIP", srcWire="BEL_Q", dstWire="BEL_A1", delay=ctx.getDelayFromNS(0.05), loc=Loc(0, 0, 0)) @@ -12,10 +11,6 @@ ctx.addBelInput(bel="BEL", name="A0", wire="BEL_A0") ctx.addBelInput(bel="BEL", name="A1", wire="BEL_A1") ctx.addBelOutput(bel="BEL", name="Q", wire="BEL_Q") -ctx.addBel(name="DUMMY_SLICE", type="GENERIC_SLICE", loc=Loc(0, 0, 1), gb=False, hidden=False) -ctx.addBelOutput(bel="DUMMY_SLICE", name="F", wire="SLICE_F") - - ctx.clearCellBelPinMap(cell="cell_i", cell_pin="A") ctx.addCellBelPinMapping(cell="cell_i", cell_pin="A", bel_pin="A0") ctx.addCellBelPinMapping(cell="cell_i", cell_pin="A", bel_pin="A1") |