Add testcases from GH

103 files changed, 576917 insertions, 0 deletions

diff --git a/ice40/.gitignore b/ice40/.gitignore
new file mode 100644
index 0000000..397b4a7
--- /dev/null
+++ b/ice40/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/ice40/regressions/Makefile b/ice40/regressions/Makefile
new file mode 100644
index 0000000..0ecb3a4
--- /dev/null
+++ b/ice40/regressions/Makefile
@@ -0,0 +1,16 @@
+NPNR = ../../nextpnr-ice40
+override NPNR := $(abspath $(NPNR))
+JSON := $(wildcard */*.json)
+SH := $(wildcard */*.sh)
+SH_BASENAME := $(patsubst %.sh,%,$(SH))
+JSON := $(filter-out $(addsuffix .json,$(SH_BASENAME)),$(JSON))
+JSON_OUTPUT := $(patsubst %.json,%.log,$(JSON))
+SH_OUTPUT := $(patsubst %.sh,%.log,$(SH))
+
+all: $(JSON_OUTPUT) $(SH_OUTPUT)
+
+$(JSON_OUTPUT): %.log: %.json $(wildcard %.pcf) $(wildcard %.npnr) $(NPNR)
+	$(NPNR) --json $(word 1,$^) $(if $(wildcard $*.pcf),--pcf $*.pcf,) $(if $(wildcard $*.npnr),$(shell cat $*.npnr),) > $@ 2>&1
+
+$(SH_OUTPUT): %.log: %.sh $(NPNR)
+	cd $(dir $@) && NPNR=$(NPNR) bash $(notdir $(word 1,$^)) > /dev/null 2>&1
diff --git a/ice40/regressions/issue0069/top.json b/ice40/regressions/issue0069/top.json
new file mode 100644
index 0000000..96601f7
--- /dev/null
+++ b/ice40/regressions/issue0069/top.json
@@ -0,0 +1,5354 @@
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+    "top": {
+      "attributes": {
+        "top": 1,
+        "src": "top.v:2"
+      },
+      "ports": {
+        "clk16": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 3 ]
+        }
+      },
+      "cells": {
+        "SB_GB": {
+          "hide_name": 0,
+          "type": "SB_GB",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "top.v:33"
+          },
+          "port_directions": {
+            "GLOBAL_BUFFER_OUTPUT": "output",
+            "USER_SIGNAL_TO_GLOBAL_BUFFER": "input"
+          },
+          "connections": {
+            "GLOBAL_BUFFER_OUTPUT": [ 3 ],
+            "USER_SIGNAL_TO_GLOBAL_BUFFER": [ 4 ]
+          }
+        },
+        "SB_PLL40_CORE": {
+          "hide_name": 0,
+          "type": "SB_PLL40_CORE",
+          "parameters": {
+            "DIVF": 63,
+            "DIVQ": 5,
+            "DIVR": 0,
+            "FILTER_RANGE": 1
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "top.v:22"
+          },
+          "port_directions": {
+            "PLLOUTGLOBAL": "output",
+            "REFERENCECLK": "input",
+            "RESETB": "input"
+          },
+          "connections": {
+            "PLLOUTGLOBAL": [ 4 ],
+            "REFERENCECLK": [ 2 ],
+            "RESETB": [ "1" ]
+          }
+        }
+      },
+      "netnames": {
+        "clk16": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "clk16_1": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:8"
+          }
+        },
+        "clk32": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:9"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        },
+        "sys_clk": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:7"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0069/top.npnr b/ice40/regressions/issue0069/top.npnr
new file mode 100644
index 0000000..f9212ab
--- /dev/null
+++ b/ice40/regressions/issue0069/top.npnr
@@ -0,0 +1 @@
+--lp8k --package cm81 --freq 16.0 --force
diff --git a/ice40/regressions/issue0069/top.pcf b/ice40/regressions/issue0069/top.pcf
new file mode 100644
index 0000000..e22b48b
--- /dev/null
+++ b/ice40/regressions/issue0069/top.pcf
@@ -0,0 +1,2 @@
+set_io clk16 B4

+set_io out B2

diff --git a/ice40/regressions/issue0069/top.v b/ice40/regressions/issue0069/top.v
new file mode 100644
index 0000000..5acb308
--- /dev/null
+++ b/ice40/regressions/issue0069/top.v
@@ -0,0 +1,38 @@
+/* Machine-generated using Migen */

+module top(

+	input clk16,

+	output out

+);

+

+wire sys_clk;

+wire clk16_1;

+wire clk32;

+

+

+// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator

+// to run the combinatorial process once at the beginning.

+// synthesis translate_off

+reg dummy_s;

+initial dummy_s <= 1'd0;

+// synthesis translate_on

+

+assign clk16_1 = clk16;

+assign out = sys_clk;

+

+SB_PLL40_CORE #(

+	.DIVF(6'd63),

+	.DIVQ(3'd5),

+	.DIVR(1'd0),

+	.FILTER_RANGE(3'd1)

+) SB_PLL40_CORE (

+	.REFERENCECLK(clk16_1),

+	.RESETB(1'd1),

+	.PLLOUTGLOBAL(clk32)

+);

+

+SB_GB SB_GB(

+	.USER_SIGNAL_TO_GLOBAL_BUFFER(clk32),

+	.GLOBAL_BUFFER_OUTPUT(sys_clk)

+);

+

+endmodule

diff --git a/ice40/regressions/issue0069/top.ys b/ice40/regressions/issue0069/top.ys
new file mode 100644
index 0000000..4752248
--- /dev/null
+++ b/ice40/regressions/issue0069/top.ys
@@ -0,0 +1,3 @@
+read_verilog top.v

+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0

+synth_ice40 -top top -json top.json
\ No newline at end of file
diff --git a/ice40/regressions/issue0070/sb_rgba_drv.json b/ice40/regressions/issue0070/sb_rgba_drv.json
new file mode 100644
index 0000000..88ea06f
--- /dev/null
+++ b/ice40/regressions/issue0070/sb_rgba_drv.json
@@ -0,0 +1,5370 @@
+{
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+          "hide_name": 0,
+          "bits": [ 38 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+          "bits": [ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ],
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+        },
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+          "bits": [ 32, 33, 34, 35 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:945"
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+        },
+        "POWEROFF": {
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+          "bits": [ 41 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+        "SLEEP": {
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+          "bits": [ 40 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+        },
+        "STANDBY": {
+          "hide_name": 0,
+          "bits": [ 39 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+        },
+        "WREN": {
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+          "bits": [ 36 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
+          }
+        }
+      }
+    },
+    "SB_WARMBOOT": {
+      "attributes": {
+        "blackbox": 1,
+        "keep": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:882"
+      },
+      "ports": {
+        "BOOT": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "S1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "S0": {
+          "direction": "input",
+          "bits": [ 4 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "BOOT": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:883"
+          }
+        },
+        "S0": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:885"
+          }
+        },
+        "S1": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:884"
+          }
+        }
+      }
+    },
+    "top": {
+      "attributes": {
+        "top": 1,
+        "src": "sb_rgba_drv.v:1"
+      },
+      "ports": {
+        "r_in": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "g_in": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "b_in": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "r_led": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "g_led": {
+          "direction": "output",
+          "bits": [ 6 ]
+        },
+        "b_led": {
+          "direction": "output",
+          "bits": [ 7 ]
+        }
+      },
+      "cells": {
+        "RGBA_DRIVER": {
+          "hide_name": 0,
+          "type": "SB_RGBA_DRV",
+          "parameters": {
+            "CURRENT_MODE": "0b0",
+            "RGB0_CURRENT": "0b000011",
+            "RGB1_CURRENT": "0b001111",
+            "RGB2_CURRENT": "0b111111"
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "sb_rgba_drv.v:12"
+          },
+          "port_directions": {
+            "CURREN": "input",
+            "RGB0": "output",
+            "RGB0PWM": "input",
+            "RGB1": "output",
+            "RGB1PWM": "input",
+            "RGB2": "output",
+            "RGB2PWM": "input",
+            "RGBLEDEN": "input"
+          },
+          "connections": {
+            "CURREN": [ "1" ],
+            "RGB0": [ 5 ],
+            "RGB0PWM": [ 2 ],
+            "RGB1": [ 6 ],
+            "RGB1PWM": [ 2 ],
+            "RGB2": [ 7 ],
+            "RGB2PWM": [ 2 ],
+            "RGBLEDEN": [ "1" ]
+          }
+        }
+      },
+      "netnames": {
+        "b_in": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "sb_rgba_drv.v:4"
+          }
+        },
+        "b_led": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "sb_rgba_drv.v:7"
+          }
+        },
+        "g_in": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "sb_rgba_drv.v:3"
+          }
+        },
+        "g_led": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "sb_rgba_drv.v:6"
+          }
+        },
+        "r_in": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "sb_rgba_drv.v:2"
+          }
+        },
+        "r_led": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "sb_rgba_drv.v:5"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0070/sb_rgba_drv.npnr b/ice40/regressions/issue0070/sb_rgba_drv.npnr
new file mode 100644
index 0000000..1f6350e
--- /dev/null
+++ b/ice40/regressions/issue0070/sb_rgba_drv.npnr
@@ -0,0 +1 @@
+--up5k
diff --git a/ice40/regressions/issue0070/sb_rgba_drv.v b/ice40/regressions/issue0070/sb_rgba_drv.v
new file mode 100644
index 0000000..e5a0c36
--- /dev/null
+++ b/ice40/regressions/issue0070/sb_rgba_drv.v
@@ -0,0 +1,32 @@
+module top(
+    input r_in,
+    input g_in,
+    input b_in,
+    output r_led,
+    output g_led,
+    output b_led);
+  
+  wire curren;
+  wire rgbleden;
+  
+  SB_RGBA_DRV RGBA_DRIVER (
+    .CURREN(curren),
+    .RGBLEDEN(rgbleden),
+    .RGB0PWM(r_in),
+    .RGB1PWM(r_in),
+    .RGB2PWM(r_in),
+    .RGB0(r_led),
+    .RGB1(g_led),
+    .RGB2(b_led)
+  );
+
+defparam RGBA_DRIVER.CURRENT_MODE = "0b0";
+defparam RGBA_DRIVER.RGB0_CURRENT = "0b000011";
+defparam RGBA_DRIVER.RGB1_CURRENT = "0b001111";
+defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";
+
+assign curren = 1'b1;
+assign rgbleden = 1'b1;
+
+
+endmodule
\ No newline at end of file
diff --git a/ice40/regressions/issue0071/top-nopll.json b/ice40/regressions/issue0071/top-nopll.json
new file mode 100644
index 0000000..5a506f3
--- /dev/null
+++ b/ice40/regressions/issue0071/top-nopll.json
@@ -0,0 +1,6747 @@
+{

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+        "I0": {

+          "direction": "input",

+          "bits": [ 2 ]

+        },

+        "I1": {

+          "direction": "input",

+          "bits": [ 3 ]

+        },

+        "I2": {

+          "direction": "input",

+          "bits": [ 4 ]

+        },

+        "I3": {

+          "direction": "input",

+          "bits": [ 5 ]

+        },

+        "CIN": {

+          "direction": "input",

+          "bits": [ 6 ]

+        },

+        "CLK": {

+          "direction": "input",

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+        },

+        "CEN": {

+          "direction": "input",

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+        },

+        "SR": {

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+        },

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+        },

+        "O": {

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+        },

+        "COUT": {

+          "direction": "output",

+          "bits": [ 12 ]

+        }

+      },

+      "cells": {

+      },

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+          "attributes": {

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+          }

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+          "bits": [ 6 ],

+          "attributes": {

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+            "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:649"

+          }

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+          "attributes": {

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+          "attributes": {

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+          }

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+          "bits": [ 11 ],

+          "attributes": {

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+            "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:649"

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+        "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:129"

+      },

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+        },

+        "I0": {

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+        },

+        "I1": {

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+        "CI": {

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+        }

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+          }

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+        "E": {

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+        "D": {

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+      }

+    },

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+      },

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+        },

+        "R": {

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+        },

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+        }

+      },

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+        "Q": {

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+        },

+        "R": {

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+        }

+      }

+    },

+    "SB_DFFES": {

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+      },

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+        },

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+        },

+        "E": {

+          "direction": "input",

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+        },

+        "S": {

+          "direction": "input",

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+        },

+        "D": {

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+          "bits": [ 6 ]

+        }

+      },

+      "cells": {

+      },

+      "netnames": {

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+          "bits": [ 3 ],

+          "attributes": {

+            "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:206"

+          }

+        },

+        "D": {

+          "hide_name": 0,

+          "bits": [ 6 ],

+          "attributes": {

+            "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:206"

+          }

+        },

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+          }

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+          }

+        },

+        "S": {

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+            "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:206"

+          }

+        }

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+    },

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+        "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:178"

+      },

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+        },

+        "C": {

+          "direction": "input",

+          "bits": [ 3 ]

+        },

+        "E": {

+          "direction": "input",

+          "bits": [ 4 ]

+        },

+        "R": {

+          "direction": "input",

+          "bits": [ 5 ]

+        },

+        "D": {

+          "direction": "input",

+          "bits": [ 6 ]

+        }

+      },

+      "cells": {

+      },

+      "netnames": {

+        "C": {

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+          "bits": [ 3 ],

+          "attributes": {

+            "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:178"

+          }

+        },

+        "D": {

+          "hide_name": 0,

+          "bits": [ 6 ],

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+          }

+        },

+        "E": {

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+          "bits": [ 4 ],

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+          }

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+}

diff --git a/ice40/regressions/issue0071/top-nopll.npnr b/ice40/regressions/issue0071/top-nopll.npnr
new file mode 100644
index 0000000..7da092a
--- /dev/null
+++ b/ice40/regressions/issue0071/top-nopll.npnr
@@ -0,0 +1 @@
+--lp8k --package cm81 --freq 16.0
diff --git a/ice40/regressions/issue0071/top-nopll.pcf b/ice40/regressions/issue0071/top-nopll.pcf
new file mode 100644
index 0000000..f90bf2b
--- /dev/null
+++ b/ice40/regressions/issue0071/top-nopll.pcf
@@ -0,0 +1,5 @@
+set_io clk16 B2

+set_io usb_d_p B4

+set_io usb_d_n A4

+set_io usb_pullup A3

+set_io user_led B3

diff --git a/ice40/regressions/issue0071/top-nopll.v b/ice40/regressions/issue0071/top-nopll.v
new file mode 100644
index 0000000..1e8c870
--- /dev/null
+++ b/ice40/regressions/issue0071/top-nopll.v
@@ -0,0 +1,35 @@
+/* Machine-generated using Migen */

+module top(

+	input clk16,

+	input usb_d_p,

+	input usb_d_n,

+	output usb_pullup,

+	output user_led

+);

+

+wire sys_clk;

+reg sys_rst = 1'd0;

+wire clk16_1;

+reg [23:0] count = 24'd0;

+

+

+// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator

+// to run the combinatorial process once at the beginning.

+// synthesis translate_off

+reg dummy_s;

+initial dummy_s <= 1'd0;

+// synthesis translate_on

+

+assign sys_clk = clk16_1;

+assign clk16_1 = clk16;

+assign usb_pullup = 1'd0;

+assign user_led = count[22];

+

+always @(posedge sys_clk) begin

+	count <= (count + 1'd1);

+	if (sys_rst) begin

+		count <= 24'd0;

+	end

+end

+

+endmodule

diff --git a/ice40/regressions/issue0071/top-nopll.ys b/ice40/regressions/issue0071/top-nopll.ys
new file mode 100644
index 0000000..4752248
--- /dev/null
+++ b/ice40/regressions/issue0071/top-nopll.ys
@@ -0,0 +1,3 @@
+read_verilog top.v

+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0

+synth_ice40 -top top -json top.json
\ No newline at end of file
diff --git a/ice40/regressions/issue0071/top-pll.json b/ice40/regressions/issue0071/top-pll.json
new file mode 100644
index 0000000..4067018
--- /dev/null
+++ b/ice40/regressions/issue0071/top-pll.json
@@ -0,0 +1,6794 @@
+{

+  "creator": "Yosys 0.7+651 (git sha1 96d79878, x86_64-w64-mingw32-g++ 7.3.0 -Os)",

+  "modules": {

+    "ICESTORM_LC": {

+      "attributes": {

+        "blackbox": 1,

+        "src": "C:\\msys64\\mingw64\\bin\\../share/yosys/ice40/cells_sim.v:648"

+      },

+      "ports": {

+        "I0": {

+          "direction": "input",

+          "bits": [ 2 ]

+        },

+        "I1": {

+          "direction": "input",

+          "bits": [ 3 ]

+        },

+        "I2": {

+          "direction": "input",

+          "bits": [ 4 ]

+        },

+        "I3": {

+          "direction": "input",

+          "bits": [ 5 ]

+        },

+        "CIN": {

+          "direction": "input",

+          "bits": [ 6 ]

+        },

+        "CLK": {

+          "direction": "input",

+          "bits": [ 7 ]

+        },

+        "CEN": {

+          "direction": "input",

+          "bits": [ 8 ]

+        },

+        "SR": {

+          "direction": "input",

+          "bits": [ 9 ]

+        },

+        "LO": {

+          "direction": "output",

+          "bits": [ 10 ]

+        },

+        "O": {

+          "direction": "output",

+          "bits": [ 11 ]

+        },

+        "COUT": {

+          "direction": "output",

+          "bits": [ 12 ]

+        }

+      },

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+}

diff --git a/ice40/regressions/issue0071/top-pll.npnr b/ice40/regressions/issue0071/top-pll.npnr
new file mode 100644
index 0000000..7da092a
--- /dev/null
+++ b/ice40/regressions/issue0071/top-pll.npnr
@@ -0,0 +1 @@
+--lp8k --package cm81 --freq 16.0
diff --git a/ice40/regressions/issue0071/top-pll.pcf b/ice40/regressions/issue0071/top-pll.pcf
new file mode 100644
index 0000000..f90bf2b
--- /dev/null
+++ b/ice40/regressions/issue0071/top-pll.pcf
@@ -0,0 +1,5 @@
+set_io clk16 B2

+set_io usb_d_p B4

+set_io usb_d_n A4

+set_io usb_pullup A3

+set_io user_led B3

diff --git a/ice40/regressions/issue0071/top-pll.v b/ice40/regressions/issue0071/top-pll.v
new file mode 100644
index 0000000..49df6c6
--- /dev/null
+++ b/ice40/regressions/issue0071/top-pll.v
@@ -0,0 +1,51 @@
+/* Machine-generated using Migen */

+module top(

+	input clk16,

+	input usb_d_p,

+	input usb_d_n,

+	output usb_pullup,

+	output user_led

+);

+

+wire sys_clk;

+reg sys_rst = 1'd0;

+wire clk16_1;

+wire clk16b;

+reg [23:0] count = 24'd0;

+

+

+// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator

+// to run the combinatorial process once at the beginning.

+// synthesis translate_off

+reg dummy_s;

+initial dummy_s <= 1'd0;

+// synthesis translate_on

+

+assign clk16_1 = clk16;

+assign usb_pullup = 1'd0;

+assign user_led = count[22];

+

+always @(posedge sys_clk) begin

+	count <= (count + 1'd1);

+	if (sys_rst) begin

+		count <= 24'd0;

+	end

+end

+

+SB_PLL40_CORE #(

+	.DIVF(6'd63),

+	.DIVQ(3'd6),

+	.DIVR(1'd0),

+	.FILTER_RANGE(3'd1)

+) SB_PLL40_CORE (

+	.REFERENCECLK(clk16_1),

+	.RESETB(1'd1),

+	.PLLOUTCORE(clk16b)

+);

+

+SB_GB SB_GB(

+	.USER_SIGNAL_TO_GLOBAL_BUFFER(clk16b),

+	.GLOBAL_BUFFER_OUTPUT(sys_clk)

+);

+

+endmodule

diff --git a/ice40/regressions/issue0071/top-pll.ys b/ice40/regressions/issue0071/top-pll.ys
new file mode 100644
index 0000000..4752248
--- /dev/null
+++ b/ice40/regressions/issue0071/top-pll.ys
@@ -0,0 +1,3 @@
+read_verilog top.v

+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0

+synth_ice40 -top top -json top.json
\ No newline at end of file
diff --git a/ice40/regressions/issue0072/top.json b/ice40/regressions/issue0072/top.json
new file mode 100644
index 0000000..8d0ab81
--- /dev/null
+++ b/ice40/regressions/issue0072/top.json
@@ -0,0 +1,28292 @@
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+            "src": "top.v:147"
+          }
+        },
+        "spiflashavrapplet_syncfifobuffered1_wrport_dat_w": {
+          "hide_name": 0,
+          "bits": [ 503, 504, 505, 506, 507, 508, 509, 511 ],
+          "attributes": {
+            "src": "top.v:150"
+          }
+        },
+        "spiflashavrapplet_syncfifobuffered1_wrport_we": {
+          "hide_name": 0,
+          "bits": [ 224 ],
+          "attributes": {
+            "src": "top.v:149"
+          }
+        },
+        "spiflashavrapplet_timer": {
+          "hide_name": 0,
+          "bits": [ 111, 112, 113, 114, 107, 108, 109, 110 ],
+          "attributes": {
+            "src": "top.v:164"
+          }
+        },
+        "spiflashavrapplet_tstriple0_i": {
+          "hide_name": 0,
+          "bits": [ 858 ],
+          "attributes": {
+            "src": "top.v:84",
+            "unused_bits": "0"
+          }
+        },
+        "spiflashavrapplet_tstriple0_o": {
+          "hide_name": 0,
+          "bits": [ 674 ],
+          "attributes": {
+            "src": "top.v:82"
+          }
+        },
+        "spiflashavrapplet_tstriple1_i": {
+          "hide_name": 0,
+          "bits": [ 860 ],
+          "attributes": {
+            "src": "top.v:87",
+            "unused_bits": "0"
+          }
+        },
+        "spiflashavrapplet_tstriple1_o": {
+          "hide_name": 0,
+          "bits": [ 99 ],
+          "attributes": {
+            "src": "top.v:85"
+          }
+        },
+        "spiflashavrapplet_tstriple1_oe": {
+          "hide_name": 0,
+          "bits": [ 592 ],
+          "attributes": {
+            "src": "top.v:86"
+          }
+        },
+        "spiflashavrapplet_tstriple2_i": {
+          "hide_name": 0,
+          "bits": [ 850 ],
+          "attributes": {
+            "src": "top.v:90"
+          }
+        },
+        "spiflashavrapplet_tstriple3_i": {
+          "hide_name": 0,
+          "bits": [ 861 ],
+          "attributes": {
+            "src": "top.v:93",
+            "unused_bits": "0"
+          }
+        },
+        "spiflashavrapplet_tstriple3_o": {
+          "hide_name": 0,
+          "bits": [ 846 ],
+          "attributes": {
+            "src": "top.v:91"
+          }
+        },
+        "spiflashavrapplet_tstriple3_oe": {
+          "hide_name": 0,
+          "bits": [ 592 ],
+          "attributes": {
+            "src": "top.v:92"
+          }
+        },
+        "storage_1[0]": {
+          "hide_name": 0,
+          "bits": [ 517, 523, 529, 535, 541, 547, 553, 559 ],
+          "attributes": {
+          }
+        },
+        "storage_1[1]": {
+          "hide_name": 0,
+          "bits": [ 516, 524, 530, 536, 542, 548, 554, 560 ],
+          "attributes": {
+          }
+        },
+        "sys_clk": {
+          "hide_name": 0,
+          "bits": [ 844 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "sys_rst": {
+          "hide_name": 0,
+          "bits": [ 50 ],
+          "attributes": {
+            "src": "top.v:19"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0072/top.npnr b/ice40/regressions/issue0072/top.npnr
new file mode 100644
index 0000000..0f913f2
--- /dev/null
+++ b/ice40/regressions/issue0072/top.npnr
@@ -0,0 +1 @@
+--up5k --package sg48 --freq 29.999999999999996
diff --git a/ice40/regressions/issue0072/top.pcf b/ice40/regressions/issue0072/top.pcf
new file mode 100644
index 0000000..885b86a
--- /dev/null
+++ b/ice40/regressions/issue0072/top.pcf
@@ -0,0 +1,37 @@
+set_io clk_if 20
+set_io i2c_scl 39
+set_io i2c_sda 40
+set_io fx2_sloe 6
+set_io fx2_slrd 47
+set_io fx2_slwr 46
+set_io fx2_pktend 2
+set_io fx2_fifoadr[0] 4
+set_io fx2_fifoadr[1] 3
+set_io fx2_flag[0] 11
+set_io fx2_flag[1] 10
+set_io fx2_flag[2] 9
+set_io fx2_flag[3] 48
+set_io fx2_fd[0] 19
+set_io fx2_fd[1] 18
+set_io fx2_fd[2] 17
+set_io fx2_fd[3] 16
+set_io fx2_fd[4] 15
+set_io fx2_fd[5] 14
+set_io fx2_fd[6] 13
+set_io fx2_fd[7] 12
+set_io io[0] 45
+set_io io[1] 43
+set_io io[2] 42
+set_io io[3] 38
+set_io io[4] 37
+set_io io[5] 36
+set_io io[6] 35
+set_io io[7] 34
+set_io io_1[0] 32
+set_io io_1[1] 31
+set_io io_1[2] 28
+set_io io_1[3] 27
+set_io io_1[4] 26
+set_io io_1[5] 25
+set_io io_1[6] 23
+set_io io_1[7] 21
diff --git a/ice40/regressions/issue0072/top.v b/ice40/regressions/issue0072/top.v
new file mode 100644
index 0000000..5eb8005
--- /dev/null
+++ b/ice40/regressions/issue0072/top.v
@@ -0,0 +1,1646 @@
+/* Machine-generated using Migen */
+module top(
+	inout clk_if,
+	inout i2c_scl,
+	inout i2c_sda,
+	inout fx2_sloe,
+	inout fx2_slrd,
+	inout fx2_slwr,
+	inout fx2_pktend,
+	inout [1:0] fx2_fifoadr,
+	inout [3:0] fx2_flag,
+	inout [7:0] fx2_fd,
+	inout [7:0] io,
+	input [7:0] io_1
+);
+
+wire por_clk;
+wire sys_clk;
+wire sys_rst;
+wire applet_clk_buf;
+reg [10:0] applet_reset_delay = 11'd2047;
+wire applet_tstriple0_o;
+wire applet_tstriple0_oe;
+wire applet_tstriple0_i;
+wire applet_tstriple1_o;
+wire applet_tstriple1_oe;
+wire applet_tstriple1_i;
+wire [6:0] applet_i2c_slave_address;
+reg applet_i2c_slave_start;
+wire applet_i2c_slave_stop;
+wire applet_i2c_slave_write;
+reg [7:0] applet_i2c_slave_data_i = 8'd0;
+reg applet_i2c_slave_ack_o;
+wire applet_i2c_slave_read;
+wire [7:0] applet_i2c_slave_data_o;
+wire applet_i2c_slave_scl_i;
+reg applet_i2c_slave_scl_o = 1'd1;
+wire applet_i2c_slave_sda_i;
+reg applet_i2c_slave_sda_o = 1'd1;
+wire applet_i2c_slave_bus_sample;
+wire applet_i2c_slave_bus_setup;
+wire applet_i2c_slave_bus_start;
+wire applet_i2c_slave_bus_stop;
+reg applet_i2c_slave_scl_r = 1'd1;
+reg applet_i2c_slave_sda_r = 1'd1;
+reg [2:0] applet_i2c_slave_bitno = 3'd0;
+reg [7:0] applet_i2c_slave_shreg_i = 8'd0;
+reg [7:0] applet_i2c_slave_shreg_o = 8'd0;
+reg applet_i2c_slave_signal_is_el0 = 1'd1;
+wire applet_i2c_slave_fsm_is_el0;
+reg applet_i2c_slave_signal_is_el1 = 1'd0;
+wire applet_i2c_slave_fsm_is_el1;
+wire applet_i2c_slave_fsm_is_el2;
+reg [7:0] applet_registers_address = 8'd0;
+wire applet_fifoadr_t_oe;
+wire [1:0] applet_fifoadr_t_o;
+wire [1:0] applet_fifoadr_t_i;
+reg applet_flag_t_oe = 1'd0;
+reg [3:0] applet_flag_t_o = 4'd0;
+wire [3:0] applet_flag_t_i;
+wire applet_fd_t_oe;
+wire [7:0] applet_fd_t_o;
+wire [7:0] applet_fd_t_i;
+wire applet_sloe_t_oe;
+wire applet_sloe_t_o;
+wire applet_sloe_t_i;
+wire applet_slrd_t_oe;
+wire applet_slrd_t_o;
+wire applet_slrd_t_i;
+wire applet_slwr_t_oe;
+wire applet_slwr_t_o;
+wire applet_slwr_t_i;
+wire applet_pktend_t_oe;
+wire applet_pktend_t_o;
+wire applet_pktend_t_i;
+reg applet_writable = 1'd0;
+reg applet_we;
+reg [7:0] applet_din;
+reg applet_re;
+reg applet_readable = 1'd0;
+reg [7:0] applet_dout = 8'd0;
+wire spiflashavrapplet_tstriple0_o;
+wire spiflashavrapplet_tstriple0_oe;
+wire spiflashavrapplet_tstriple0_i;
+wire spiflashavrapplet_tstriple1_o;
+wire spiflashavrapplet_tstriple1_oe;
+wire spiflashavrapplet_tstriple1_i;
+reg spiflashavrapplet_tstriple2_o = 1'd0;
+reg spiflashavrapplet_tstriple2_oe = 1'd0;
+wire spiflashavrapplet_tstriple2_i;
+wire spiflashavrapplet_tstriple3_o;
+wire spiflashavrapplet_tstriple3_oe;
+wire spiflashavrapplet_tstriple3_i;
+reg spiflashavrapplet_syncfifobuffered0_re;
+reg spiflashavrapplet_syncfifobuffered0_readable = 1'd0;
+reg spiflashavrapplet_syncfifobuffered0_syncfifo0_we;
+wire spiflashavrapplet_syncfifobuffered0_syncfifo0_writable;
+wire spiflashavrapplet_syncfifobuffered0_syncfifo0_re;
+wire spiflashavrapplet_syncfifobuffered0_syncfifo0_readable;
+reg [7:0] spiflashavrapplet_syncfifobuffered0_syncfifo0_din;
+wire [7:0] spiflashavrapplet_syncfifobuffered0_syncfifo0_dout;
+reg [9:0] spiflashavrapplet_syncfifobuffered0_level0 = 10'd0;
+reg spiflashavrapplet_syncfifobuffered0_replace = 1'd0;
+reg [8:0] spiflashavrapplet_syncfifobuffered0_produce = 9'd0;
+reg [8:0] spiflashavrapplet_syncfifobuffered0_consume = 9'd0;
+reg [8:0] spiflashavrapplet_syncfifobuffered0_wrport_adr;
+wire [7:0] spiflashavrapplet_syncfifobuffered0_wrport_dat_r;
+wire spiflashavrapplet_syncfifobuffered0_wrport_we;
+wire [7:0] spiflashavrapplet_syncfifobuffered0_wrport_dat_w;
+wire spiflashavrapplet_syncfifobuffered0_do_read;
+wire [8:0] spiflashavrapplet_syncfifobuffered0_rdport_adr;
+wire [7:0] spiflashavrapplet_syncfifobuffered0_rdport_dat_r;
+wire spiflashavrapplet_syncfifobuffered0_rdport_re;
+wire [9:0] spiflashavrapplet_syncfifobuffered0_level1;
+reg spiflashavrapplet_fifowithoverflow_we;
+reg spiflashavrapplet_fifowithoverflow_writable;
+reg [7:0] spiflashavrapplet_fifowithoverflow_din;
+reg spiflashavrapplet_fifowithoverflow_syncfifo_we;
+wire spiflashavrapplet_fifowithoverflow_syncfifo_writable;
+reg spiflashavrapplet_fifowithoverflow_syncfifo_re;
+wire spiflashavrapplet_fifowithoverflow_syncfifo_readable;
+reg [7:0] spiflashavrapplet_fifowithoverflow_syncfifo_din;
+wire [7:0] spiflashavrapplet_fifowithoverflow_syncfifo_dout;
+reg [1:0] spiflashavrapplet_fifowithoverflow_level = 2'd0;
+reg spiflashavrapplet_fifowithoverflow_replace = 1'd0;
+reg spiflashavrapplet_fifowithoverflow_produce = 1'd0;
+reg spiflashavrapplet_fifowithoverflow_consume = 1'd0;
+reg spiflashavrapplet_fifowithoverflow_wrport_adr;
+wire [7:0] spiflashavrapplet_fifowithoverflow_wrport_dat_r;
+wire spiflashavrapplet_fifowithoverflow_wrport_we;
+wire [7:0] spiflashavrapplet_fifowithoverflow_wrport_dat_w;
+wire spiflashavrapplet_fifowithoverflow_do_read;
+wire spiflashavrapplet_fifowithoverflow_rdport_adr;
+wire [7:0] spiflashavrapplet_fifowithoverflow_rdport_dat_r;
+reg spiflashavrapplet_syncfifobuffered1_re;
+reg spiflashavrapplet_syncfifobuffered1_readable = 1'd0;
+reg spiflashavrapplet_syncfifobuffered1_syncfifo1_we;
+wire spiflashavrapplet_syncfifobuffered1_syncfifo1_writable;
+wire spiflashavrapplet_syncfifobuffered1_syncfifo1_re;
+wire spiflashavrapplet_syncfifobuffered1_syncfifo1_readable;
+reg [7:0] spiflashavrapplet_syncfifobuffered1_syncfifo1_din;
+wire [7:0] spiflashavrapplet_syncfifobuffered1_syncfifo1_dout;
+reg [9:0] spiflashavrapplet_syncfifobuffered1_level0 = 10'd0;
+reg spiflashavrapplet_syncfifobuffered1_replace = 1'd0;
+reg [8:0] spiflashavrapplet_syncfifobuffered1_produce = 9'd0;
+reg [8:0] spiflashavrapplet_syncfifobuffered1_consume = 9'd0;
+reg [8:0] spiflashavrapplet_syncfifobuffered1_wrport_adr;
+wire [7:0] spiflashavrapplet_syncfifobuffered1_wrport_dat_r;
+wire spiflashavrapplet_syncfifobuffered1_wrport_we;
+wire [7:0] spiflashavrapplet_syncfifobuffered1_wrport_dat_w;
+wire spiflashavrapplet_syncfifobuffered1_do_read;
+wire [8:0] spiflashavrapplet_syncfifobuffered1_rdport_adr;
+wire [7:0] spiflashavrapplet_syncfifobuffered1_rdport_dat_r;
+wire spiflashavrapplet_syncfifobuffered1_rdport_re;
+wire [9:0] spiflashavrapplet_syncfifobuffered1_level1;
+wire spiflashavrapplet_oe;
+reg spiflashavrapplet_sck = 1'd0;
+reg spiflashavrapplet_ss = 1'd1;
+wire spiflashavrapplet_mosi;
+wire spiflashavrapplet_miso;
+reg spiflashavrapplet_sck_r = 1'd0;
+wire spiflashavrapplet_setup;
+wire spiflashavrapplet_latch;
+reg [7:0] spiflashavrapplet_timer = 8'd0;
+reg [15:0] spiflashavrapplet_count = 16'd0;
+reg [2:0] spiflashavrapplet_bitno = 3'd7;
+reg [7:0] spiflashavrapplet_oreg = 8'd0;
+reg [7:0] spiflashavrapplet_ireg = 8'd0;
+wire spiflashavrapplet_reset;
+reg spiflashavrapplet_reg0 = 1'd0;
+reg spiflashavrapplet_reg1 = 1'd0;
+reg [2:0] i2cslave_state = 3'd0;
+reg [2:0] i2cslave_next_state;
+reg [2:0] applet_i2c_slave_bitno_i2cslave_next_value;
+reg applet_i2c_slave_bitno_i2cslave_next_value_ce;
+reg [7:0] applet_i2c_slave_shreg_i_i2cslave_t_next_value;
+reg applet_i2c_slave_shreg_i_i2cslave_t_next_value_ce;
+reg applet_i2c_slave_sda_o_i2cslave_f_next_value0;
+reg applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0;
+reg [7:0] applet_i2c_slave_shreg_o_i2cslave_f_next_value1;
+reg applet_i2c_slave_shreg_o_i2cslave_f_next_value_ce1;
+reg [7:0] applet_i2c_slave_data_i_i2cslave_f_next_value2;
+reg applet_i2c_slave_data_i_i2cslave_f_next_value_ce2;
+reg latch_addr = 1'd0;
+wire [3:0] fx2arbiter_flag;
+reg [1:0] fx2arbiter_addr = 2'd0;
+reg fx2arbiter_fdoe = 1'd0;
+reg fx2arbiter_sloe = 1'd0;
+reg fx2arbiter_slrd;
+reg fx2arbiter_slwr;
+reg fx2arbiter_pend;
+wire [3:0] fx2arbiter_rdy;
+reg [1:0] fx2arbiter_naddr;
+reg [2:0] fx2arbiter_state = 3'd0;
+reg [2:0] fx2arbiter_next_state;
+reg fx2arbiter_sloe_fx2arbiter_next_value0;
+reg fx2arbiter_sloe_fx2arbiter_next_value_ce0;
+reg fx2arbiter_fdoe_fx2arbiter_next_value1;
+reg fx2arbiter_fdoe_fx2arbiter_next_value_ce1;
+reg [1:0] fx2arbiter_addr_fx2arbiter_next_value2;
+reg fx2arbiter_addr_fx2arbiter_next_value_ce2;
+reg [2:0] resetinserter_state = 3'd0;
+reg [2:0] resetinserter_next_state;
+reg [15:0] spiflashavrapplet_count_resetinserter_t_next_value0;
+reg spiflashavrapplet_count_resetinserter_t_next_value_ce0;
+reg spiflashavrapplet_ss_resetinserter_f_next_value;
+reg spiflashavrapplet_ss_resetinserter_f_next_value_ce;
+reg [7:0] spiflashavrapplet_oreg_resetinserter_t_next_value1;
+reg spiflashavrapplet_oreg_resetinserter_t_next_value_ce1;
+reg [7:0] spiflashavrapplet_timer_resetinserter_t_next_value2;
+reg spiflashavrapplet_timer_resetinserter_t_next_value_ce2;
+reg spiflashavrapplet_sck_resetinserter_t_next_value3;
+reg spiflashavrapplet_sck_resetinserter_t_next_value_ce3;
+reg [2:0] spiflashavrapplet_bitno_resetinserter_t_next_value4;
+reg spiflashavrapplet_bitno_resetinserter_t_next_value_ce4;
+reg rhs_array_muxed0;
+wire [7:0] lhs_array_muxed;
+reg [7:0] rhs_array_muxed1;
+reg cases_lhs_array_muxed;
+reg cases_basiclowerer_array_muxed0;
+reg cases_basiclowerer_array_muxed1;
+reg cases_f_array_muxed;
+reg cases_array_muxed;
+reg cases_rhs_array_muxed;
+reg array_muxed = 1'd0;
+reg multiregimpl0_regs0 = 1'd1;
+reg multiregimpl0_regs1 = 1'd1;
+reg multiregimpl1_regs0 = 1'd1;
+reg multiregimpl1_regs1 = 1'd1;
+reg multiregimpl2_regs0 = 1'd0;
+reg multiregimpl2_regs1 = 1'd0;
+
+
+// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
+// to run the combinatorial process once at the beginning.
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+
+assign applet_i2c_slave_address = 4'd8;
+assign spiflashavrapplet_reset = spiflashavrapplet_reg0;
+assign spiflashavrapplet_oe = spiflashavrapplet_reg1;
+assign spiflashavrapplet_tstriple0_oe = 1'd1;
+assign spiflashavrapplet_tstriple0_o = (~spiflashavrapplet_reg1);
+assign sys_clk = por_clk;
+assign sys_rst = (applet_reset_delay != 1'd0);
+assign applet_i2c_slave_stop = applet_i2c_slave_signal_is_el0;
+assign applet_i2c_slave_write = applet_i2c_slave_signal_is_el1;
+assign applet_i2c_slave_read = applet_i2c_slave_fsm_is_el2;
+assign applet_tstriple0_o = 1'd0;
+assign applet_tstriple0_oe = (~applet_i2c_slave_scl_o);
+assign applet_tstriple1_o = 1'd0;
+assign applet_tstriple1_oe = (~applet_i2c_slave_sda_o);
+assign applet_i2c_slave_bus_sample = ((~applet_i2c_slave_scl_r) & applet_i2c_slave_scl_i);
+assign applet_i2c_slave_bus_setup = (applet_i2c_slave_scl_r & (~applet_i2c_slave_scl_i));
+assign applet_i2c_slave_bus_start = ((applet_i2c_slave_scl_i & applet_i2c_slave_sda_r) & (~applet_i2c_slave_sda_i));
+assign applet_i2c_slave_bus_stop = ((applet_i2c_slave_scl_i & (~applet_i2c_slave_sda_r)) & applet_i2c_slave_sda_i);
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+	applet_i2c_slave_start <= 1'd0;
+	i2cslave_next_state <= 3'd0;
+	applet_i2c_slave_bitno_i2cslave_next_value <= 3'd0;
+	applet_i2c_slave_bitno_i2cslave_next_value_ce <= 1'd0;
+	applet_i2c_slave_shreg_i_i2cslave_t_next_value <= 8'd0;
+	applet_i2c_slave_shreg_i_i2cslave_t_next_value_ce <= 1'd0;
+	applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= 1'd0;
+	applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd0;
+	applet_i2c_slave_shreg_o_i2cslave_f_next_value1 <= 8'd0;
+	applet_i2c_slave_shreg_o_i2cslave_f_next_value_ce1 <= 1'd0;
+	applet_i2c_slave_data_i_i2cslave_f_next_value2 <= 8'd0;
+	applet_i2c_slave_data_i_i2cslave_f_next_value_ce2 <= 1'd0;
+	i2cslave_next_state <= i2cslave_state;
+	case (i2cslave_state)
+		1'd1: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_setup) begin
+					applet_i2c_slave_bitno_i2cslave_next_value <= 1'd0;
+					applet_i2c_slave_bitno_i2cslave_next_value_ce <= 1'd1;
+					i2cslave_next_state <= 2'd2;
+				end
+			end
+		end
+		2'd2: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_start) begin
+					i2cslave_next_state <= 1'd1;
+				end else begin
+					if (applet_i2c_slave_bus_sample) begin
+						applet_i2c_slave_shreg_i_i2cslave_t_next_value <= ((applet_i2c_slave_shreg_i <<< 1'd1) | applet_i2c_slave_sda_i);
+						applet_i2c_slave_shreg_i_i2cslave_t_next_value_ce <= 1'd1;
+					end else begin
+						if (applet_i2c_slave_bus_setup) begin
+							applet_i2c_slave_bitno_i2cslave_next_value <= (applet_i2c_slave_bitno + 1'd1);
+							applet_i2c_slave_bitno_i2cslave_next_value_ce <= 1'd1;
+							if ((applet_i2c_slave_bitno == 3'd7)) begin
+								if ((applet_i2c_slave_shreg_i[7:1] == applet_i2c_slave_address)) begin
+									applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= 1'd0;
+									applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd1;
+									i2cslave_next_state <= 2'd3;
+								end else begin
+									i2cslave_next_state <= 1'd0;
+								end
+							end
+						end
+					end
+				end
+			end
+		end
+		2'd3: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_start) begin
+					i2cslave_next_state <= 1'd1;
+				end else begin
+					if (applet_i2c_slave_bus_setup) begin
+						if ((~applet_i2c_slave_shreg_i[0])) begin
+							applet_i2c_slave_start <= 1'd1;
+							applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= 1'd1;
+							applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd1;
+							i2cslave_next_state <= 3'd4;
+						end
+					end else begin
+						if (applet_i2c_slave_bus_sample) begin
+							if (applet_i2c_slave_shreg_i[0]) begin
+								applet_i2c_slave_start <= 1'd1;
+								i2cslave_next_state <= 3'd6;
+								applet_i2c_slave_shreg_o_i2cslave_f_next_value1 <= applet_i2c_slave_data_o;
+								applet_i2c_slave_shreg_o_i2cslave_f_next_value_ce1 <= 1'd1;
+							end
+						end
+					end
+				end
+			end
+		end
+		3'd4: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_start) begin
+					i2cslave_next_state <= 1'd1;
+				end else begin
+					if (applet_i2c_slave_bus_sample) begin
+						applet_i2c_slave_shreg_i_i2cslave_t_next_value <= ((applet_i2c_slave_shreg_i <<< 1'd1) | applet_i2c_slave_sda_i);
+						applet_i2c_slave_shreg_i_i2cslave_t_next_value_ce <= 1'd1;
+					end else begin
+						if (applet_i2c_slave_bus_setup) begin
+							applet_i2c_slave_bitno_i2cslave_next_value <= (applet_i2c_slave_bitno + 1'd1);
+							applet_i2c_slave_bitno_i2cslave_next_value_ce <= 1'd1;
+							if ((applet_i2c_slave_bitno == 3'd7)) begin
+								applet_i2c_slave_data_i_i2cslave_f_next_value2 <= applet_i2c_slave_shreg_i;
+								applet_i2c_slave_data_i_i2cslave_f_next_value_ce2 <= 1'd1;
+								i2cslave_next_state <= 3'd5;
+							end
+						end
+					end
+				end
+			end
+		end
+		3'd5: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_start) begin
+					i2cslave_next_state <= 1'd1;
+				end else begin
+					if (((~applet_i2c_slave_scl_i) & applet_i2c_slave_ack_o)) begin
+						applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= 1'd0;
+						applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd1;
+					end else begin
+						if (applet_i2c_slave_bus_setup) begin
+							applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= 1'd1;
+							applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd1;
+							i2cslave_next_state <= 3'd4;
+						end
+					end
+				end
+			end
+		end
+		3'd6: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_start) begin
+					i2cslave_next_state <= 1'd1;
+				end else begin
+					if (applet_i2c_slave_bus_setup) begin
+						applet_i2c_slave_bitno_i2cslave_next_value <= (applet_i2c_slave_bitno + 1'd1);
+						applet_i2c_slave_bitno_i2cslave_next_value_ce <= 1'd1;
+						applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= applet_i2c_slave_shreg_o[7];
+						applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd1;
+						applet_i2c_slave_shreg_o_i2cslave_f_next_value1 <= (applet_i2c_slave_shreg_o <<< 1'd1);
+						applet_i2c_slave_shreg_o_i2cslave_f_next_value_ce1 <= 1'd1;
+					end else begin
+						if (applet_i2c_slave_bus_sample) begin
+							if ((applet_i2c_slave_bitno == 1'd0)) begin
+								applet_i2c_slave_sda_o_i2cslave_f_next_value0 <= 1'd1;
+								applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0 <= 1'd1;
+								i2cslave_next_state <= 3'd7;
+							end
+						end
+					end
+				end
+			end
+		end
+		3'd7: begin
+			if (applet_i2c_slave_bus_stop) begin
+				i2cslave_next_state <= 1'd0;
+			end else begin
+				if (applet_i2c_slave_bus_start) begin
+					i2cslave_next_state <= 1'd1;
+				end else begin
+					if (applet_i2c_slave_bus_sample) begin
+						if ((~applet_i2c_slave_sda_i)) begin
+							i2cslave_next_state <= 3'd6;
+						end else begin
+							i2cslave_next_state <= 1'd0;
+						end
+					end
+				end
+			end
+		end
+		default: begin
+			if (applet_i2c_slave_bus_start) begin
+				i2cslave_next_state <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d <= dummy_s;
+// synthesis translate_on
+end
+assign applet_i2c_slave_fsm_is_el0 = ((~(i2cslave_state == 1'd0)) & (i2cslave_next_state == 1'd0));
+assign applet_i2c_slave_fsm_is_el1 = ((~(i2cslave_state == 3'd5)) & (i2cslave_next_state == 3'd5));
+assign applet_i2c_slave_fsm_is_el2 = ((~(i2cslave_state == 3'd6)) & (i2cslave_next_state == 3'd6));
+assign applet_i2c_slave_data_o = rhs_array_muxed0;
+
+// synthesis translate_off
+reg dummy_d_1;
+// synthesis translate_on
+always @(*) begin
+	applet_i2c_slave_ack_o <= 1'd0;
+	if (applet_i2c_slave_write) begin
+		if ((latch_addr & (applet_i2c_slave_data_i < 2'd2))) begin
+			applet_i2c_slave_ack_o <= 1'd1;
+		end else begin
+			if ((~latch_addr)) begin
+				applet_i2c_slave_ack_o <= 1'd1;
+			end
+		end
+	end
+// synthesis translate_off
+	dummy_d_1 <= dummy_s;
+// synthesis translate_on
+end
+assign applet_fifoadr_t_oe = 1'd1;
+assign applet_fifoadr_t_o = fx2arbiter_addr;
+assign fx2arbiter_flag = applet_flag_t_i;
+assign fx2arbiter_rdy = ({applet_readable, spiflashavrapplet_syncfifobuffered1_readable, applet_writable, spiflashavrapplet_syncfifobuffered0_syncfifo0_writable} & fx2arbiter_flag);
+assign lhs_array_muxed = applet_fd_t_i;
+
+// synthesis translate_off
+reg dummy_d_2;
+// synthesis translate_on
+always @(*) begin
+	applet_din <= 8'd0;
+	spiflashavrapplet_fifowithoverflow_din <= 8'd0;
+	case (fx2arbiter_addr[0])
+		1'd0: begin
+			spiflashavrapplet_fifowithoverflow_din <= lhs_array_muxed;
+		end
+		default: begin
+			applet_din <= lhs_array_muxed;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_2 <= dummy_s;
+// synthesis translate_on
+end
+assign applet_fd_t_o = rhs_array_muxed1;
+assign applet_fd_t_oe = fx2arbiter_fdoe;
+assign applet_sloe_t_oe = 1'd1;
+assign applet_sloe_t_o = (~fx2arbiter_sloe);
+assign applet_slrd_t_oe = 1'd1;
+assign applet_slrd_t_o = (~fx2arbiter_slrd);
+assign applet_slwr_t_oe = 1'd1;
+assign applet_slwr_t_o = (~fx2arbiter_slwr);
+assign applet_pktend_t_oe = 1'd1;
+assign applet_pktend_t_o = (~fx2arbiter_pend);
+
+// synthesis translate_off
+reg dummy_d_3;
+// synthesis translate_on
+always @(*) begin
+	fx2arbiter_naddr <= 2'd0;
+	case ({fx2arbiter_addr, fx2arbiter_rdy})
+		1'd0: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		1'd1: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		2'd2: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		2'd3: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		3'd4: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		3'd5: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		3'd6: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		3'd7: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		4'd8: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		4'd9: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		4'd10: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		4'd11: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		4'd12: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		4'd13: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		4'd14: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		4'd15: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		5'd16: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		5'd17: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		5'd18: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd19: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd20: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		5'd21: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		5'd22: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd23: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd24: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		5'd25: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		5'd26: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd27: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd28: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		5'd29: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		5'd30: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		5'd31: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		6'd32: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd33: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd34: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		6'd35: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd36: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd37: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd38: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd39: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd40: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd41: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd42: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd43: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd44: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd45: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd46: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd47: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd48: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd49: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd50: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		6'd51: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd52: begin
+			fx2arbiter_naddr <= 2'd2;
+		end
+		6'd53: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd54: begin
+			fx2arbiter_naddr <= 1'd1;
+		end
+		6'd55: begin
+			fx2arbiter_naddr <= 1'd0;
+		end
+		6'd56: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd57: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd58: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd59: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd60: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd61: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd62: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+		6'd63: begin
+			fx2arbiter_naddr <= 2'd3;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_3 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_4;
+// synthesis translate_on
+always @(*) begin
+	spiflashavrapplet_syncfifobuffered0_syncfifo0_we <= 1'd0;
+	spiflashavrapplet_syncfifobuffered0_syncfifo0_din <= 8'd0;
+	spiflashavrapplet_fifowithoverflow_writable <= 1'd0;
+	spiflashavrapplet_fifowithoverflow_syncfifo_we <= 1'd0;
+	spiflashavrapplet_fifowithoverflow_syncfifo_re <= 1'd0;
+	spiflashavrapplet_fifowithoverflow_syncfifo_din <= 8'd0;
+	if (spiflashavrapplet_fifowithoverflow_syncfifo_readable) begin
+		spiflashavrapplet_syncfifobuffered0_syncfifo0_din <= spiflashavrapplet_fifowithoverflow_syncfifo_dout;
+		spiflashavrapplet_syncfifobuffered0_syncfifo0_we <= 1'd1;
+		spiflashavrapplet_fifowithoverflow_syncfifo_re <= spiflashavrapplet_syncfifobuffered0_syncfifo0_writable;
+	end
+	if ((spiflashavrapplet_syncfifobuffered0_syncfifo0_writable & (~spiflashavrapplet_fifowithoverflow_syncfifo_readable))) begin
+		spiflashavrapplet_syncfifobuffered0_syncfifo0_din <= spiflashavrapplet_fifowithoverflow_din;
+		spiflashavrapplet_syncfifobuffered0_syncfifo0_we <= spiflashavrapplet_fifowithoverflow_we;
+		spiflashavrapplet_fifowithoverflow_writable <= spiflashavrapplet_syncfifobuffered0_syncfifo0_writable;
+	end else begin
+		spiflashavrapplet_fifowithoverflow_syncfifo_din <= spiflashavrapplet_fifowithoverflow_din;
+		spiflashavrapplet_fifowithoverflow_syncfifo_we <= spiflashavrapplet_fifowithoverflow_we;
+		spiflashavrapplet_fifowithoverflow_writable <= spiflashavrapplet_fifowithoverflow_syncfifo_writable;
+	end
+// synthesis translate_off
+	dummy_d_4 <= dummy_s;
+// synthesis translate_on
+end
+assign spiflashavrapplet_syncfifobuffered0_syncfifo0_re = (spiflashavrapplet_syncfifobuffered0_syncfifo0_readable & ((~spiflashavrapplet_syncfifobuffered0_readable) | spiflashavrapplet_syncfifobuffered0_re));
+assign spiflashavrapplet_syncfifobuffered0_level1 = (spiflashavrapplet_syncfifobuffered0_level0 + spiflashavrapplet_syncfifobuffered0_readable);
+
+// synthesis translate_off
+reg dummy_d_5;
+// synthesis translate_on
+always @(*) begin
+	spiflashavrapplet_syncfifobuffered0_wrport_adr <= 9'd0;
+	if (spiflashavrapplet_syncfifobuffered0_replace) begin
+		spiflashavrapplet_syncfifobuffered0_wrport_adr <= (spiflashavrapplet_syncfifobuffered0_produce - 1'd1);
+	end else begin
+		spiflashavrapplet_syncfifobuffered0_wrport_adr <= spiflashavrapplet_syncfifobuffered0_produce;
+	end
+// synthesis translate_off
+	dummy_d_5 <= dummy_s;
+// synthesis translate_on
+end
+assign spiflashavrapplet_syncfifobuffered0_wrport_dat_w = spiflashavrapplet_syncfifobuffered0_syncfifo0_din;
+assign spiflashavrapplet_syncfifobuffered0_wrport_we = (spiflashavrapplet_syncfifobuffered0_syncfifo0_we & (spiflashavrapplet_syncfifobuffered0_syncfifo0_writable | spiflashavrapplet_syncfifobuffered0_replace));
+assign spiflashavrapplet_syncfifobuffered0_do_read = (spiflashavrapplet_syncfifobuffered0_syncfifo0_readable & spiflashavrapplet_syncfifobuffered0_syncfifo0_re);
+assign spiflashavrapplet_syncfifobuffered0_rdport_adr = spiflashavrapplet_syncfifobuffered0_consume;
+assign spiflashavrapplet_syncfifobuffered0_syncfifo0_dout = spiflashavrapplet_syncfifobuffered0_rdport_dat_r;
+assign spiflashavrapplet_syncfifobuffered0_rdport_re = spiflashavrapplet_syncfifobuffered0_do_read;
+assign spiflashavrapplet_syncfifobuffered0_syncfifo0_writable = (spiflashavrapplet_syncfifobuffered0_level0 != 10'd512);
+assign spiflashavrapplet_syncfifobuffered0_syncfifo0_readable = (spiflashavrapplet_syncfifobuffered0_level0 != 1'd0);
+
+// synthesis translate_off
+reg dummy_d_6;
+// synthesis translate_on
+always @(*) begin
+	spiflashavrapplet_fifowithoverflow_wrport_adr <= 1'd0;
+	if (spiflashavrapplet_fifowithoverflow_replace) begin
+		spiflashavrapplet_fifowithoverflow_wrport_adr <= (spiflashavrapplet_fifowithoverflow_produce - 1'd1);
+	end else begin
+		spiflashavrapplet_fifowithoverflow_wrport_adr <= spiflashavrapplet_fifowithoverflow_produce;
+	end
+// synthesis translate_off
+	dummy_d_6 <= dummy_s;
+// synthesis translate_on
+end
+assign spiflashavrapplet_fifowithoverflow_wrport_dat_w = spiflashavrapplet_fifowithoverflow_syncfifo_din;
+assign spiflashavrapplet_fifowithoverflow_wrport_we = (spiflashavrapplet_fifowithoverflow_syncfifo_we & (spiflashavrapplet_fifowithoverflow_syncfifo_writable | spiflashavrapplet_fifowithoverflow_replace));
+assign spiflashavrapplet_fifowithoverflow_do_read = (spiflashavrapplet_fifowithoverflow_syncfifo_readable & spiflashavrapplet_fifowithoverflow_syncfifo_re);
+assign spiflashavrapplet_fifowithoverflow_rdport_adr = spiflashavrapplet_fifowithoverflow_consume;
+assign spiflashavrapplet_fifowithoverflow_syncfifo_dout = spiflashavrapplet_fifowithoverflow_rdport_dat_r;
+assign spiflashavrapplet_fifowithoverflow_syncfifo_writable = (spiflashavrapplet_fifowithoverflow_level != 2'd2);
+assign spiflashavrapplet_fifowithoverflow_syncfifo_readable = (spiflashavrapplet_fifowithoverflow_level != 1'd0);
+assign spiflashavrapplet_syncfifobuffered1_syncfifo1_re = (spiflashavrapplet_syncfifobuffered1_syncfifo1_readable & ((~spiflashavrapplet_syncfifobuffered1_readable) | spiflashavrapplet_syncfifobuffered1_re));
+assign spiflashavrapplet_syncfifobuffered1_level1 = (spiflashavrapplet_syncfifobuffered1_level0 + spiflashavrapplet_syncfifobuffered1_readable);
+
+// synthesis translate_off
+reg dummy_d_7;
+// synthesis translate_on
+always @(*) begin
+	spiflashavrapplet_syncfifobuffered1_wrport_adr <= 9'd0;
+	if (spiflashavrapplet_syncfifobuffered1_replace) begin
+		spiflashavrapplet_syncfifobuffered1_wrport_adr <= (spiflashavrapplet_syncfifobuffered1_produce - 1'd1);
+	end else begin
+		spiflashavrapplet_syncfifobuffered1_wrport_adr <= spiflashavrapplet_syncfifobuffered1_produce;
+	end
+// synthesis translate_off
+	dummy_d_7 <= dummy_s;
+// synthesis translate_on
+end
+assign spiflashavrapplet_syncfifobuffered1_wrport_dat_w = spiflashavrapplet_syncfifobuffered1_syncfifo1_din;
+assign spiflashavrapplet_syncfifobuffered1_wrport_we = (spiflashavrapplet_syncfifobuffered1_syncfifo1_we & (spiflashavrapplet_syncfifobuffered1_syncfifo1_writable | spiflashavrapplet_syncfifobuffered1_replace));
+assign spiflashavrapplet_syncfifobuffered1_do_read = (spiflashavrapplet_syncfifobuffered1_syncfifo1_readable & spiflashavrapplet_syncfifobuffered1_syncfifo1_re);
+assign spiflashavrapplet_syncfifobuffered1_rdport_adr = spiflashavrapplet_syncfifobuffered1_consume;
+assign spiflashavrapplet_syncfifobuffered1_syncfifo1_dout = spiflashavrapplet_syncfifobuffered1_rdport_dat_r;
+assign spiflashavrapplet_syncfifobuffered1_rdport_re = spiflashavrapplet_syncfifobuffered1_do_read;
+assign spiflashavrapplet_syncfifobuffered1_syncfifo1_writable = (spiflashavrapplet_syncfifobuffered1_level0 != 10'd512);
+assign spiflashavrapplet_syncfifobuffered1_syncfifo1_readable = (spiflashavrapplet_syncfifobuffered1_level0 != 1'd0);
+
+// synthesis translate_off
+reg dummy_d_8;
+// synthesis translate_on
+always @(*) begin
+	applet_we <= 1'd0;
+	applet_re <= 1'd0;
+	spiflashavrapplet_fifowithoverflow_we <= 1'd0;
+	spiflashavrapplet_syncfifobuffered1_re <= 1'd0;
+	fx2arbiter_slrd <= 1'd0;
+	fx2arbiter_slwr <= 1'd0;
+	fx2arbiter_pend <= 1'd0;
+	fx2arbiter_next_state <= 3'd0;
+	fx2arbiter_sloe_fx2arbiter_next_value0 <= 1'd0;
+	fx2arbiter_sloe_fx2arbiter_next_value_ce0 <= 1'd0;
+	fx2arbiter_fdoe_fx2arbiter_next_value1 <= 1'd0;
+	fx2arbiter_fdoe_fx2arbiter_next_value_ce1 <= 1'd0;
+	fx2arbiter_addr_fx2arbiter_next_value2 <= 2'd0;
+	fx2arbiter_addr_fx2arbiter_next_value_ce2 <= 1'd0;
+	cases_lhs_array_muxed <= 1'd0;
+	cases_array_muxed <= 1'd0;
+	fx2arbiter_next_state <= fx2arbiter_state;
+	case (fx2arbiter_state)
+		1'd1: begin
+			if (fx2arbiter_addr[1]) begin
+				fx2arbiter_fdoe_fx2arbiter_next_value1 <= 1'd1;
+				fx2arbiter_fdoe_fx2arbiter_next_value_ce1 <= 1'd1;
+			end else begin
+				fx2arbiter_sloe_fx2arbiter_next_value0 <= 1'd1;
+				fx2arbiter_sloe_fx2arbiter_next_value_ce0 <= 1'd1;
+			end
+			fx2arbiter_next_state <= 2'd2;
+		end
+		2'd2: begin
+			if (fx2arbiter_addr[1]) begin
+				fx2arbiter_next_state <= 2'd3;
+			end else begin
+				fx2arbiter_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			fx2arbiter_next_state <= 3'd4;
+		end
+		3'd4: begin
+			if ((fx2arbiter_rdy & (1'd1 <<< fx2arbiter_addr))) begin
+				fx2arbiter_slwr <= 1'd1;
+				cases_lhs_array_muxed <= 1'd1;
+				case (fx2arbiter_addr[0])
+					1'd0: begin
+						spiflashavrapplet_syncfifobuffered1_re <= cases_lhs_array_muxed;
+					end
+					default: begin
+						applet_re <= cases_lhs_array_muxed;
+					end
+				endcase
+			end else begin
+				if (((((fx2arbiter_flag & (1'd1 <<< fx2arbiter_addr)) == 1'd0) & (~cases_basiclowerer_array_muxed0)) & cases_basiclowerer_array_muxed1)) begin
+					fx2arbiter_pend <= 1'd1;
+					fx2arbiter_next_state <= 1'd0;
+				end else begin
+					if ((((fx2arbiter_flag & (1'd1 <<< fx2arbiter_addr)) != 1'd0) & (~cases_f_array_muxed))) begin
+						fx2arbiter_pend <= 1'd1;
+						fx2arbiter_next_state <= 1'd0;
+					end else begin
+						fx2arbiter_next_state <= 1'd0;
+					end
+				end
+			end
+		end
+		3'd5: begin
+			fx2arbiter_slrd <= 1'd1;
+			fx2arbiter_next_state <= 3'd6;
+		end
+		3'd6: begin
+			cases_array_muxed <= ((fx2arbiter_flag & (1'd1 <<< fx2arbiter_addr)) != 1'd0);
+			case (fx2arbiter_addr[0])
+				1'd0: begin
+					spiflashavrapplet_fifowithoverflow_we <= cases_array_muxed;
+				end
+				default: begin
+					applet_we <= cases_array_muxed;
+				end
+			endcase
+			if ((fx2arbiter_rdy & (1'd1 <<< fx2arbiter_addr))) begin
+				fx2arbiter_slrd <= cases_rhs_array_muxed;
+			end else begin
+				fx2arbiter_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			fx2arbiter_sloe_fx2arbiter_next_value0 <= 1'd0;
+			fx2arbiter_sloe_fx2arbiter_next_value_ce0 <= 1'd1;
+			fx2arbiter_fdoe_fx2arbiter_next_value1 <= 1'd0;
+			fx2arbiter_fdoe_fx2arbiter_next_value_ce1 <= 1'd1;
+			fx2arbiter_addr_fx2arbiter_next_value2 <= fx2arbiter_naddr;
+			fx2arbiter_addr_fx2arbiter_next_value_ce2 <= 1'd1;
+			if (fx2arbiter_rdy) begin
+				fx2arbiter_next_state <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_8 <= dummy_s;
+// synthesis translate_on
+end
+assign spiflashavrapplet_mosi = spiflashavrapplet_oreg[7];
+assign spiflashavrapplet_tstriple1_oe = spiflashavrapplet_oe;
+assign spiflashavrapplet_tstriple1_o = spiflashavrapplet_sck;
+assign spiflashavrapplet_tstriple3_oe = spiflashavrapplet_oe;
+assign spiflashavrapplet_tstriple3_o = spiflashavrapplet_mosi;
+assign spiflashavrapplet_setup = (spiflashavrapplet_sck_r & (~spiflashavrapplet_sck));
+assign spiflashavrapplet_latch = ((~spiflashavrapplet_sck_r) & spiflashavrapplet_sck);
+
+// synthesis translate_off
+reg dummy_d_9;
+// synthesis translate_on
+always @(*) begin
+	spiflashavrapplet_syncfifobuffered0_re <= 1'd0;
+	spiflashavrapplet_syncfifobuffered1_syncfifo1_we <= 1'd0;
+	spiflashavrapplet_syncfifobuffered1_syncfifo1_din <= 8'd0;
+	resetinserter_next_state <= 3'd0;
+	spiflashavrapplet_count_resetinserter_t_next_value0 <= 16'd0;
+	spiflashavrapplet_count_resetinserter_t_next_value_ce0 <= 1'd0;
+	spiflashavrapplet_ss_resetinserter_f_next_value <= 1'd0;
+	spiflashavrapplet_ss_resetinserter_f_next_value_ce <= 1'd0;
+	spiflashavrapplet_oreg_resetinserter_t_next_value1 <= 8'd0;
+	spiflashavrapplet_oreg_resetinserter_t_next_value_ce1 <= 1'd0;
+	spiflashavrapplet_timer_resetinserter_t_next_value2 <= 8'd0;
+	spiflashavrapplet_timer_resetinserter_t_next_value_ce2 <= 1'd0;
+	spiflashavrapplet_sck_resetinserter_t_next_value3 <= 1'd0;
+	spiflashavrapplet_sck_resetinserter_t_next_value_ce3 <= 1'd0;
+	spiflashavrapplet_bitno_resetinserter_t_next_value4 <= 3'd0;
+	spiflashavrapplet_bitno_resetinserter_t_next_value_ce4 <= 1'd0;
+	resetinserter_next_state <= resetinserter_state;
+	case (resetinserter_state)
+		1'd1: begin
+			if (spiflashavrapplet_syncfifobuffered0_readable) begin
+				spiflashavrapplet_syncfifobuffered0_re <= 1'd1;
+				spiflashavrapplet_count_resetinserter_t_next_value0 <= (spiflashavrapplet_count | spiflashavrapplet_syncfifobuffered0_syncfifo0_dout);
+				spiflashavrapplet_count_resetinserter_t_next_value_ce0 <= 1'd1;
+				resetinserter_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if ((spiflashavrapplet_count == 1'd0)) begin
+				resetinserter_next_state <= 1'd0;
+			end else begin
+				spiflashavrapplet_ss_resetinserter_f_next_value <= 1'd0;
+				spiflashavrapplet_ss_resetinserter_f_next_value_ce <= 1'd1;
+				resetinserter_next_state <= 2'd3;
+			end
+		end
+		2'd3: begin
+			if (spiflashavrapplet_syncfifobuffered0_readable) begin
+				spiflashavrapplet_syncfifobuffered0_re <= 1'd1;
+				spiflashavrapplet_count_resetinserter_t_next_value0 <= (spiflashavrapplet_count - 1'd1);
+				spiflashavrapplet_count_resetinserter_t_next_value_ce0 <= 1'd1;
+				spiflashavrapplet_oreg_resetinserter_t_next_value1 <= spiflashavrapplet_syncfifobuffered0_syncfifo0_dout;
+				spiflashavrapplet_oreg_resetinserter_t_next_value_ce1 <= 1'd1;
+				spiflashavrapplet_timer_resetinserter_t_next_value2 <= 8'd149;
+				spiflashavrapplet_timer_resetinserter_t_next_value_ce2 <= 1'd1;
+				resetinserter_next_state <= 3'd4;
+			end
+		end
+		3'd4: begin
+			if ((spiflashavrapplet_timer == 1'd0)) begin
+				spiflashavrapplet_timer_resetinserter_t_next_value2 <= 8'd149;
+				spiflashavrapplet_timer_resetinserter_t_next_value_ce2 <= 1'd1;
+				spiflashavrapplet_sck_resetinserter_t_next_value3 <= (~spiflashavrapplet_sck);
+				spiflashavrapplet_sck_resetinserter_t_next_value_ce3 <= 1'd1;
+				if ((spiflashavrapplet_sck == 1'd1)) begin
+					spiflashavrapplet_bitno_resetinserter_t_next_value4 <= (spiflashavrapplet_bitno - 1'd1);
+					spiflashavrapplet_bitno_resetinserter_t_next_value_ce4 <= 1'd1;
+					if ((spiflashavrapplet_bitno == 1'd0)) begin
+						resetinserter_next_state <= 3'd5;
+					end
+				end
+			end else begin
+				spiflashavrapplet_timer_resetinserter_t_next_value2 <= (spiflashavrapplet_timer - 1'd1);
+				spiflashavrapplet_timer_resetinserter_t_next_value_ce2 <= 1'd1;
+			end
+		end
+		3'd5: begin
+			spiflashavrapplet_syncfifobuffered1_syncfifo1_din <= spiflashavrapplet_ireg;
+			if (spiflashavrapplet_syncfifobuffered1_syncfifo1_writable) begin
+				spiflashavrapplet_syncfifobuffered1_syncfifo1_we <= 1'd1;
+				if ((spiflashavrapplet_count == 1'd0)) begin
+					resetinserter_next_state <= 3'd6;
+				end else begin
+					resetinserter_next_state <= 2'd3;
+				end
+			end
+		end
+		3'd6: begin
+			if ((spiflashavrapplet_timer == 1'd0)) begin
+				spiflashavrapplet_ss_resetinserter_f_next_value <= 1'd1;
+				spiflashavrapplet_ss_resetinserter_f_next_value_ce <= 1'd1;
+				resetinserter_next_state <= 1'd0;
+			end else begin
+				spiflashavrapplet_timer_resetinserter_t_next_value2 <= (spiflashavrapplet_timer - 1'd1);
+				spiflashavrapplet_timer_resetinserter_t_next_value_ce2 <= 1'd1;
+			end
+		end
+		default: begin
+			if (spiflashavrapplet_syncfifobuffered0_readable) begin
+				spiflashavrapplet_syncfifobuffered0_re <= 1'd1;
+				spiflashavrapplet_count_resetinserter_t_next_value0 <= (spiflashavrapplet_syncfifobuffered0_syncfifo0_dout <<< 4'd8);
+				spiflashavrapplet_count_resetinserter_t_next_value_ce0 <= 1'd1;
+				resetinserter_next_state <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_9 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_10;
+// synthesis translate_on
+always @(*) begin
+	rhs_array_muxed0 <= 1'd0;
+	case (applet_registers_address)
+		1'd0: begin
+			rhs_array_muxed0 <= spiflashavrapplet_reg0;
+		end
+		default: begin
+			rhs_array_muxed0 <= spiflashavrapplet_reg1;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_10 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_11;
+// synthesis translate_on
+always @(*) begin
+	rhs_array_muxed1 <= 8'd0;
+	case (fx2arbiter_addr[0])
+		1'd0: begin
+			rhs_array_muxed1 <= spiflashavrapplet_syncfifobuffered1_syncfifo1_dout;
+		end
+		default: begin
+			rhs_array_muxed1 <= applet_dout;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_11 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_12;
+// synthesis translate_on
+always @(*) begin
+	cases_basiclowerer_array_muxed0 <= 1'd0;
+	case (fx2arbiter_addr[0])
+		1'd0: begin
+			cases_basiclowerer_array_muxed0 <= spiflashavrapplet_syncfifobuffered1_readable;
+		end
+		default: begin
+			cases_basiclowerer_array_muxed0 <= applet_readable;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_12 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_13;
+// synthesis translate_on
+always @(*) begin
+	cases_basiclowerer_array_muxed1 <= 1'd0;
+	case (fx2arbiter_addr[0])
+		1'd0: begin
+			cases_basiclowerer_array_muxed1 <= 1'd0;
+		end
+		default: begin
+			cases_basiclowerer_array_muxed1 <= 1'd0;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_13 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_14;
+// synthesis translate_on
+always @(*) begin
+	cases_f_array_muxed <= 1'd0;
+	case (fx2arbiter_addr[0])
+		1'd0: begin
+			cases_f_array_muxed <= 1'd0;
+		end
+		default: begin
+			cases_f_array_muxed <= 1'd0;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_14 <= dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_15;
+// synthesis translate_on
+always @(*) begin
+	cases_rhs_array_muxed <= 1'd0;
+	case (fx2arbiter_addr[0])
+		1'd0: begin
+			cases_rhs_array_muxed <= spiflashavrapplet_syncfifobuffered0_syncfifo0_writable;
+		end
+		default: begin
+			cases_rhs_array_muxed <= applet_writable;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_15 <= dummy_s;
+// synthesis translate_on
+end
+assign applet_i2c_slave_scl_i = multiregimpl0_regs1;
+assign applet_i2c_slave_sda_i = multiregimpl1_regs1;
+assign spiflashavrapplet_miso = multiregimpl2_regs1;
+
+always @(posedge por_clk) begin
+	if ((applet_reset_delay != 1'd0)) begin
+		applet_reset_delay <= (applet_reset_delay - 1'd1);
+	end
+end
+
+always @(posedge sys_clk) begin
+	applet_i2c_slave_scl_r <= applet_i2c_slave_scl_i;
+	applet_i2c_slave_sda_r <= applet_i2c_slave_sda_i;
+	applet_i2c_slave_signal_is_el0 <= applet_i2c_slave_fsm_is_el0;
+	applet_i2c_slave_signal_is_el1 <= applet_i2c_slave_fsm_is_el1;
+	i2cslave_state <= i2cslave_next_state;
+	if (applet_i2c_slave_bitno_i2cslave_next_value_ce) begin
+		applet_i2c_slave_bitno <= applet_i2c_slave_bitno_i2cslave_next_value;
+	end
+	if (applet_i2c_slave_shreg_i_i2cslave_t_next_value_ce) begin
+		applet_i2c_slave_shreg_i <= applet_i2c_slave_shreg_i_i2cslave_t_next_value;
+	end
+	if (applet_i2c_slave_sda_o_i2cslave_f_next_value_ce0) begin
+		applet_i2c_slave_sda_o <= applet_i2c_slave_sda_o_i2cslave_f_next_value0;
+	end
+	if (applet_i2c_slave_shreg_o_i2cslave_f_next_value_ce1) begin
+		applet_i2c_slave_shreg_o <= applet_i2c_slave_shreg_o_i2cslave_f_next_value1;
+	end
+	if (applet_i2c_slave_data_i_i2cslave_f_next_value_ce2) begin
+		applet_i2c_slave_data_i <= applet_i2c_slave_data_i_i2cslave_f_next_value2;
+	end
+	if (applet_i2c_slave_start) begin
+		latch_addr <= 1'd1;
+	end
+	if (applet_i2c_slave_write) begin
+		if (latch_addr) begin
+			if ((applet_i2c_slave_data_i < 2'd2)) begin
+				latch_addr <= 1'd0;
+				applet_registers_address <= applet_i2c_slave_data_i;
+			end
+		end else begin
+			array_muxed = applet_i2c_slave_data_i;
+			case (applet_registers_address)
+				1'd0: begin
+					spiflashavrapplet_reg0 <= array_muxed;
+				end
+				default: begin
+					spiflashavrapplet_reg1 <= array_muxed;
+				end
+			endcase
+		end
+	end
+	if (spiflashavrapplet_syncfifobuffered0_syncfifo0_re) begin
+		spiflashavrapplet_syncfifobuffered0_readable <= 1'd1;
+	end else begin
+		if (spiflashavrapplet_syncfifobuffered0_re) begin
+			spiflashavrapplet_syncfifobuffered0_readable <= 1'd0;
+		end
+	end
+	if (((spiflashavrapplet_syncfifobuffered0_syncfifo0_we & spiflashavrapplet_syncfifobuffered0_syncfifo0_writable) & (~spiflashavrapplet_syncfifobuffered0_replace))) begin
+		spiflashavrapplet_syncfifobuffered0_produce <= (spiflashavrapplet_syncfifobuffered0_produce + 1'd1);
+	end
+	if (spiflashavrapplet_syncfifobuffered0_do_read) begin
+		spiflashavrapplet_syncfifobuffered0_consume <= (spiflashavrapplet_syncfifobuffered0_consume + 1'd1);
+	end
+	if (((spiflashavrapplet_syncfifobuffered0_syncfifo0_we & spiflashavrapplet_syncfifobuffered0_syncfifo0_writable) & (~spiflashavrapplet_syncfifobuffered0_replace))) begin
+		if ((~spiflashavrapplet_syncfifobuffered0_do_read)) begin
+			spiflashavrapplet_syncfifobuffered0_level0 <= (spiflashavrapplet_syncfifobuffered0_level0 + 1'd1);
+		end
+	end else begin
+		if (spiflashavrapplet_syncfifobuffered0_do_read) begin
+			spiflashavrapplet_syncfifobuffered0_level0 <= (spiflashavrapplet_syncfifobuffered0_level0 - 1'd1);
+		end
+	end
+	if (((spiflashavrapplet_fifowithoverflow_syncfifo_we & spiflashavrapplet_fifowithoverflow_syncfifo_writable) & (~spiflashavrapplet_fifowithoverflow_replace))) begin
+		spiflashavrapplet_fifowithoverflow_produce <= (spiflashavrapplet_fifowithoverflow_produce + 1'd1);
+	end
+	if (spiflashavrapplet_fifowithoverflow_do_read) begin
+		spiflashavrapplet_fifowithoverflow_consume <= (spiflashavrapplet_fifowithoverflow_consume + 1'd1);
+	end
+	if (((spiflashavrapplet_fifowithoverflow_syncfifo_we & spiflashavrapplet_fifowithoverflow_syncfifo_writable) & (~spiflashavrapplet_fifowithoverflow_replace))) begin
+		if ((~spiflashavrapplet_fifowithoverflow_do_read)) begin
+			spiflashavrapplet_fifowithoverflow_level <= (spiflashavrapplet_fifowithoverflow_level + 1'd1);
+		end
+	end else begin
+		if (spiflashavrapplet_fifowithoverflow_do_read) begin
+			spiflashavrapplet_fifowithoverflow_level <= (spiflashavrapplet_fifowithoverflow_level - 1'd1);
+		end
+	end
+	if (spiflashavrapplet_syncfifobuffered1_syncfifo1_re) begin
+		spiflashavrapplet_syncfifobuffered1_readable <= 1'd1;
+	end else begin
+		if (spiflashavrapplet_syncfifobuffered1_re) begin
+			spiflashavrapplet_syncfifobuffered1_readable <= 1'd0;
+		end
+	end
+	if (((spiflashavrapplet_syncfifobuffered1_syncfifo1_we & spiflashavrapplet_syncfifobuffered1_syncfifo1_writable) & (~spiflashavrapplet_syncfifobuffered1_replace))) begin
+		spiflashavrapplet_syncfifobuffered1_produce <= (spiflashavrapplet_syncfifobuffered1_produce + 1'd1);
+	end
+	if (spiflashavrapplet_syncfifobuffered1_do_read) begin
+		spiflashavrapplet_syncfifobuffered1_consume <= (spiflashavrapplet_syncfifobuffered1_consume + 1'd1);
+	end
+	if (((spiflashavrapplet_syncfifobuffered1_syncfifo1_we & spiflashavrapplet_syncfifobuffered1_syncfifo1_writable) & (~spiflashavrapplet_syncfifobuffered1_replace))) begin
+		if ((~spiflashavrapplet_syncfifobuffered1_do_read)) begin
+			spiflashavrapplet_syncfifobuffered1_level0 <= (spiflashavrapplet_syncfifobuffered1_level0 + 1'd1);
+		end
+	end else begin
+		if (spiflashavrapplet_syncfifobuffered1_do_read) begin
+			spiflashavrapplet_syncfifobuffered1_level0 <= (spiflashavrapplet_syncfifobuffered1_level0 - 1'd1);
+		end
+	end
+	fx2arbiter_state <= fx2arbiter_next_state;
+	if (fx2arbiter_sloe_fx2arbiter_next_value_ce0) begin
+		fx2arbiter_sloe <= fx2arbiter_sloe_fx2arbiter_next_value0;
+	end
+	if (fx2arbiter_fdoe_fx2arbiter_next_value_ce1) begin
+		fx2arbiter_fdoe <= fx2arbiter_fdoe_fx2arbiter_next_value1;
+	end
+	if (fx2arbiter_addr_fx2arbiter_next_value_ce2) begin
+		fx2arbiter_addr <= fx2arbiter_addr_fx2arbiter_next_value2;
+	end
+	if (spiflashavrapplet_setup) begin
+		spiflashavrapplet_oreg[7:1] <= spiflashavrapplet_oreg;
+	end else begin
+		if (spiflashavrapplet_latch) begin
+			spiflashavrapplet_ireg <= {spiflashavrapplet_ireg, spiflashavrapplet_miso};
+		end
+	end
+	spiflashavrapplet_sck_r <= spiflashavrapplet_sck;
+	resetinserter_state <= resetinserter_next_state;
+	if (spiflashavrapplet_count_resetinserter_t_next_value_ce0) begin
+		spiflashavrapplet_count <= spiflashavrapplet_count_resetinserter_t_next_value0;
+	end
+	if (spiflashavrapplet_ss_resetinserter_f_next_value_ce) begin
+		spiflashavrapplet_ss <= spiflashavrapplet_ss_resetinserter_f_next_value;
+	end
+	if (spiflashavrapplet_oreg_resetinserter_t_next_value_ce1) begin
+		spiflashavrapplet_oreg <= spiflashavrapplet_oreg_resetinserter_t_next_value1;
+	end
+	if (spiflashavrapplet_timer_resetinserter_t_next_value_ce2) begin
+		spiflashavrapplet_timer <= spiflashavrapplet_timer_resetinserter_t_next_value2;
+	end
+	if (spiflashavrapplet_sck_resetinserter_t_next_value_ce3) begin
+		spiflashavrapplet_sck <= spiflashavrapplet_sck_resetinserter_t_next_value3;
+	end
+	if (spiflashavrapplet_bitno_resetinserter_t_next_value_ce4) begin
+		spiflashavrapplet_bitno <= spiflashavrapplet_bitno_resetinserter_t_next_value4;
+	end
+	if (spiflashavrapplet_reset) begin
+		spiflashavrapplet_sck <= 1'd0;
+		spiflashavrapplet_ss <= 1'd1;
+		spiflashavrapplet_sck_r <= 1'd0;
+		spiflashavrapplet_timer <= 8'd0;
+		spiflashavrapplet_count <= 16'd0;
+		spiflashavrapplet_bitno <= 3'd7;
+		spiflashavrapplet_oreg <= 8'd0;
+		spiflashavrapplet_ireg <= 8'd0;
+		resetinserter_state <= 3'd0;
+	end
+	if (sys_rst) begin
+		applet_i2c_slave_data_i <= 8'd0;
+		applet_i2c_slave_sda_o <= 1'd1;
+		applet_i2c_slave_scl_r <= 1'd1;
+		applet_i2c_slave_sda_r <= 1'd1;
+		applet_i2c_slave_bitno <= 3'd0;
+		applet_i2c_slave_shreg_i <= 8'd0;
+		applet_i2c_slave_shreg_o <= 8'd0;
+		applet_i2c_slave_signal_is_el0 <= 1'd1;
+		applet_i2c_slave_signal_is_el1 <= 1'd0;
+		applet_registers_address <= 8'd0;
+		spiflashavrapplet_syncfifobuffered0_readable <= 1'd0;
+		spiflashavrapplet_syncfifobuffered0_level0 <= 10'd0;
+		spiflashavrapplet_syncfifobuffered0_produce <= 9'd0;
+		spiflashavrapplet_syncfifobuffered0_consume <= 9'd0;
+		spiflashavrapplet_fifowithoverflow_level <= 2'd0;
+		spiflashavrapplet_fifowithoverflow_produce <= 1'd0;
+		spiflashavrapplet_fifowithoverflow_consume <= 1'd0;
+		spiflashavrapplet_syncfifobuffered1_readable <= 1'd0;
+		spiflashavrapplet_syncfifobuffered1_level0 <= 10'd0;
+		spiflashavrapplet_syncfifobuffered1_produce <= 9'd0;
+		spiflashavrapplet_syncfifobuffered1_consume <= 9'd0;
+		spiflashavrapplet_sck <= 1'd0;
+		spiflashavrapplet_ss <= 1'd1;
+		spiflashavrapplet_sck_r <= 1'd0;
+		spiflashavrapplet_timer <= 8'd0;
+		spiflashavrapplet_count <= 16'd0;
+		spiflashavrapplet_bitno <= 3'd7;
+		spiflashavrapplet_oreg <= 8'd0;
+		spiflashavrapplet_ireg <= 8'd0;
+		spiflashavrapplet_reg0 <= 1'd0;
+		spiflashavrapplet_reg1 <= 1'd0;
+		i2cslave_state <= 3'd0;
+		latch_addr <= 1'd0;
+		fx2arbiter_addr <= 2'd0;
+		fx2arbiter_fdoe <= 1'd0;
+		fx2arbiter_sloe <= 1'd0;
+		fx2arbiter_state <= 3'd0;
+		resetinserter_state <= 3'd0;
+	end
+	multiregimpl0_regs0 <= applet_tstriple0_i;
+	multiregimpl0_regs1 <= multiregimpl0_regs0;
+	multiregimpl1_regs0 <= applet_tstriple1_i;
+	multiregimpl1_regs1 <= multiregimpl1_regs0;
+	multiregimpl2_regs0 <= spiflashavrapplet_tstriple2_i;
+	multiregimpl2_regs1 <= multiregimpl2_regs0;
+end
+
+SB_IO #(
+	.PIN_TYPE(6'd1)
+) SB_IO (
+	.PACKAGE_PIN(clk_if),
+	.D_IN_0(applet_clk_buf)
+);
+
+SB_GB SB_GB(
+	.USER_SIGNAL_TO_GLOBAL_BUFFER(applet_clk_buf),
+	.GLOBAL_BUFFER_OUTPUT(por_clk)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_1 (
+	.D_OUT_0(applet_fifoadr_t_o[0]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fifoadr_t_oe),
+	.PACKAGE_PIN(fx2_fifoadr[0]),
+	.D_IN_0(applet_fifoadr_t_i[0])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_2 (
+	.D_OUT_0(applet_fifoadr_t_o[1]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fifoadr_t_oe),
+	.PACKAGE_PIN(fx2_fifoadr[1]),
+	.D_IN_0(applet_fifoadr_t_i[1])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_3 (
+	.D_OUT_0(applet_flag_t_o[0]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_flag_t_oe),
+	.PACKAGE_PIN(fx2_flag[0]),
+	.D_IN_0(applet_flag_t_i[0])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_4 (
+	.D_OUT_0(applet_flag_t_o[1]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_flag_t_oe),
+	.PACKAGE_PIN(fx2_flag[1]),
+	.D_IN_0(applet_flag_t_i[1])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_5 (
+	.D_OUT_0(applet_flag_t_o[2]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_flag_t_oe),
+	.PACKAGE_PIN(fx2_flag[2]),
+	.D_IN_0(applet_flag_t_i[2])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_6 (
+	.D_OUT_0(applet_flag_t_o[3]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_flag_t_oe),
+	.PACKAGE_PIN(fx2_flag[3]),
+	.D_IN_0(applet_flag_t_i[3])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_7 (
+	.D_OUT_0(applet_fd_t_o[0]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[0]),
+	.D_IN_0(applet_fd_t_i[0])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_8 (
+	.D_OUT_0(applet_fd_t_o[1]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[1]),
+	.D_IN_0(applet_fd_t_i[1])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_9 (
+	.D_OUT_0(applet_fd_t_o[2]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[2]),
+	.D_IN_0(applet_fd_t_i[2])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_10 (
+	.D_OUT_0(applet_fd_t_o[3]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[3]),
+	.D_IN_0(applet_fd_t_i[3])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_11 (
+	.D_OUT_0(applet_fd_t_o[4]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[4]),
+	.D_IN_0(applet_fd_t_i[4])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_12 (
+	.D_OUT_0(applet_fd_t_o[5]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[5]),
+	.D_IN_0(applet_fd_t_i[5])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_13 (
+	.D_OUT_0(applet_fd_t_o[6]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[6]),
+	.D_IN_0(applet_fd_t_i[6])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_14 (
+	.D_OUT_0(applet_fd_t_o[7]),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_fd_t_oe),
+	.PACKAGE_PIN(fx2_fd[7]),
+	.D_IN_0(applet_fd_t_i[7])
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_15 (
+	.D_OUT_0(applet_sloe_t_o),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_sloe_t_oe),
+	.PACKAGE_PIN(fx2_sloe),
+	.D_IN_0(applet_sloe_t_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_16 (
+	.D_OUT_0(applet_slrd_t_o),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_slrd_t_oe),
+	.PACKAGE_PIN(fx2_slrd),
+	.D_IN_0(applet_slrd_t_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_17 (
+	.D_OUT_0(applet_slwr_t_o),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_slwr_t_oe),
+	.PACKAGE_PIN(fx2_slwr),
+	.D_IN_0(applet_slwr_t_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd52)
+) SB_IO_18 (
+	.D_OUT_0(applet_pktend_t_o),
+	.INPUT_CLK(sys_clk),
+	.OUTPUT_CLK(sys_clk),
+	.OUTPUT_ENABLE(applet_pktend_t_oe),
+	.PACKAGE_PIN(fx2_pktend),
+	.D_IN_0(applet_pktend_t_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd41)
+) SB_IO_19 (
+	.D_OUT_0(spiflashavrapplet_tstriple0_o),
+	.OUTPUT_ENABLE(spiflashavrapplet_tstriple0_oe),
+	.PACKAGE_PIN(io[0]),
+	.D_IN_0(spiflashavrapplet_tstriple0_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd41)
+) SB_IO_20 (
+	.D_OUT_0(spiflashavrapplet_tstriple1_o),
+	.OUTPUT_ENABLE(spiflashavrapplet_tstriple1_oe),
+	.PACKAGE_PIN(io[1]),
+	.D_IN_0(spiflashavrapplet_tstriple1_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd41)
+) SB_IO_21 (
+	.D_OUT_0(spiflashavrapplet_tstriple2_o),
+	.OUTPUT_ENABLE(spiflashavrapplet_tstriple2_oe),
+	.PACKAGE_PIN(io[2]),
+	.D_IN_0(spiflashavrapplet_tstriple2_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd41)
+) SB_IO_22 (
+	.D_OUT_0(spiflashavrapplet_tstriple3_o),
+	.OUTPUT_ENABLE(spiflashavrapplet_tstriple3_oe),
+	.PACKAGE_PIN(io[3]),
+	.D_IN_0(spiflashavrapplet_tstriple3_i)
+);
+
+reg [7:0] storage[0:511];
+reg [7:0] memdat;
+reg [7:0] memdat_1;
+always @(posedge sys_clk) begin
+	if (spiflashavrapplet_syncfifobuffered0_wrport_we)
+		storage[spiflashavrapplet_syncfifobuffered0_wrport_adr] <= spiflashavrapplet_syncfifobuffered0_wrport_dat_w;
+	memdat <= storage[spiflashavrapplet_syncfifobuffered0_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+	if (spiflashavrapplet_syncfifobuffered0_rdport_re)
+		memdat_1 <= storage[spiflashavrapplet_syncfifobuffered0_rdport_adr];
+end
+
+assign spiflashavrapplet_syncfifobuffered0_wrport_dat_r = memdat;
+assign spiflashavrapplet_syncfifobuffered0_rdport_dat_r = memdat_1;
+
+reg [7:0] storage_1[0:1];
+reg [7:0] memdat_2;
+always @(posedge sys_clk) begin
+	if (spiflashavrapplet_fifowithoverflow_wrport_we)
+		storage_1[spiflashavrapplet_fifowithoverflow_wrport_adr] <= spiflashavrapplet_fifowithoverflow_wrport_dat_w;
+	memdat_2 <= storage_1[spiflashavrapplet_fifowithoverflow_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign spiflashavrapplet_fifowithoverflow_wrport_dat_r = memdat_2;
+assign spiflashavrapplet_fifowithoverflow_rdport_dat_r = storage_1[spiflashavrapplet_fifowithoverflow_rdport_adr];
+
+reg [7:0] storage_2[0:511];
+reg [7:0] memdat_3;
+reg [7:0] memdat_4;
+always @(posedge sys_clk) begin
+	if (spiflashavrapplet_syncfifobuffered1_wrport_we)
+		storage_2[spiflashavrapplet_syncfifobuffered1_wrport_adr] <= spiflashavrapplet_syncfifobuffered1_wrport_dat_w;
+	memdat_3 <= storage_2[spiflashavrapplet_syncfifobuffered1_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+	if (spiflashavrapplet_syncfifobuffered1_rdport_re)
+		memdat_4 <= storage_2[spiflashavrapplet_syncfifobuffered1_rdport_adr];
+end
+
+assign spiflashavrapplet_syncfifobuffered1_wrport_dat_r = memdat_3;
+assign spiflashavrapplet_syncfifobuffered1_rdport_dat_r = memdat_4;
+
+SB_IO #(
+	.PIN_TYPE(6'd41)
+) SB_IO_23 (
+	.D_OUT_0(applet_tstriple0_o),
+	.OUTPUT_ENABLE(applet_tstriple0_oe),
+	.PACKAGE_PIN(i2c_scl),
+	.D_IN_0(applet_tstriple0_i)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'd41)
+) SB_IO_24 (
+	.D_OUT_0(applet_tstriple1_o),
+	.OUTPUT_ENABLE(applet_tstriple1_oe),
+	.PACKAGE_PIN(i2c_sda),
+	.D_IN_0(applet_tstriple1_i)
+);
+
+endmodule
diff --git a/ice40/regressions/issue0072/top.ys b/ice40/regressions/issue0072/top.ys
new file mode 100644
index 0000000..b22a82d
--- /dev/null
+++ b/ice40/regressions/issue0072/top.ys
@@ -0,0 +1,3 @@
+read_verilog top.v
+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
+synth_ice40 -top top -json top.json
\ No newline at end of file
diff --git a/ice40/regressions/issue0084/mlaccel.json b/ice40/regressions/issue0084/mlaccel.json
new file mode 100644
index 0000000..eb205d7
--- /dev/null
+++ b/ice40/regressions/issue0084/mlaccel.json
@@ -0,0 +1,120323 @@
+{
+  "creator": "Yosys 0.7+661 (git sha1 592a82c, clang 3.8.0-2ubuntu4 -fPIC -Os)",
+  "modules": {
+    "ICESTORM_LC": {
+      "attributes": {
+        "blackbox": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:648"
+      },
+      "ports": {
+        "I0": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "I1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I2": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "I3": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "CIN": {
+          "direction": "input",
+          "bits": [ 6 ]
+        },
+        "CLK": {
+          "direction": "input",
+          "bits": [ 7 ]
+        },
+        "CEN": {
+          "direction": "input",
+          "bits": [ 8 ]
+        },
+        "SR": {
+          "direction": "input",
+          "bits": [ 9 ]
+        },
+        "LO": {
+          "direction": "output",
+          "bits": [ 10 ]
+        },
+        "O": {
+          "direction": "output",
+          "bits": [ 11 ]
+        },
+        "COUT": {
+          "direction": "output",
+          "bits": [ 12 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "CEN": {
+          "hide_name": 0,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "CIN": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "CLK": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "COUT": {
+          "hide_name": 0,
+          "bits": [ 12 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:650"
+          }
+        },
+        "I0": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "I1": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "I2": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "I3": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "LO": {
+          "hide_name": 0,
+          "bits": [ 10 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:650"
+          }
+        },
+        "O": {
+          "hide_name": 0,
+          "bits": [ 11 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:650"
+          }
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+            "INIT_4": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "INIT_6": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "INIT_C": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_D": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_E": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_F": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "READ_MODE": 1,
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+          },
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+          },
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+            "RCLK": "input",
+            "RCLKE": "input",
+            "RDATA": "output",
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+            "WADDR": "input",
+            "WCLK": "input",
+            "WCLKE": "input",
+            "WDATA": "input",
+            "WE": "input"
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+            "WE": [ "1" ]
+          }
+        },
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+            "READ_MODE": 1,
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+          },
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+            "WCLK": "input",
+            "WCLKE": "input",
+            "WDATA": "input",
+            "WE": "input"
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+            "READ_MODE": 1,
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+          },
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+            "WE": [ "1" ]
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+            "WE": [ "1" ]
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+            "READ_MODE": 1,
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+          },
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+            "WE": "input"
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+            "WE": [ "1" ]
+          }
+        },
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+          "parameters": {
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+            "INIT_2": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "INIT_4": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "READ_MODE": 1,
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+          },
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+          },
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+            "RCLK": "input",
+            "RCLKE": "input",
+            "RDATA": "output",
+            "RE": "input",
+            "WADDR": "input",
+            "WCLK": "input",
+            "WCLKE": "input",
+            "WDATA": "input",
+            "WE": "input"
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+            "WE": [ "1" ]
+          }
+        },
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+            "WADDR": "input",
+            "WCLK": "input",
+            "WCLKE": "input",
+            "WDATA": "input",
+            "WE": "input"
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+            "WCLKE": "input",
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+            "WE": "input"
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+            "WE": [ "1" ]
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+          },
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+            "WE": "input"
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+            "WE": [ "1" ]
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+            "READ_MODE": 1,
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+          },
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+            "WE": "input"
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+            "WE": [ "1" ]
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+            "READ_MODE": 1,
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+          },
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+            "WADDR": "input",
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+            "WCLKE": "input",
+            "WDATA": "input",
+            "WE": "input"
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+            "WE": [ "1" ]
+          }
+        },
+        "comp.coeff_mem.5.0.0": {
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+          "parameters": {
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+            "INIT_1": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_2": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_3": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_4": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_5": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "INIT_7": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "WCLKE": "input",
+            "WDATA": "input",
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+            "READ_MODE": 1,
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+            "WCLK": "input",
+            "WCLKE": "input",
+            "WDATA": "input",
+            "WE": "input"
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+            "WE": [ "1" ]
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+            "INIT_C": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "INIT_E": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "READ_MODE": 1,
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+            "WE": "input"
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+            "WE": [ "1" ]
+          }
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+            "INIT_1": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_2": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_3": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_4": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_5": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_6": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_7": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_8": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
+            "INIT_9": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
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+            "WE": "input"
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+            "WE": [ "1" ]
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+            "BOTADDSUB_UPPERINPUT": 0,
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+            "BOT_8x8_MULT_REG": 1,
+            "B_REG": 1,
+            "B_SIGNED": 1,
+            "C_REG": 0,
+            "D_REG": 0,
+            "MODE_8x8": 1,
+            "NEG_TRIGGER": 0,
+            "PIPELINE_16x16_MULT_REG1": 1,
+            "PIPELINE_16x16_MULT_REG2": 0,
+            "TOPADDSUB_CARRYSELECT": 0,
+            "TOPADDSUB_LOWERINPUT": 0,
+            "TOPADDSUB_UPPERINPUT": 0,
+            "TOPOUTPUT_SELECT": 2,
+            "TOP_8x8_MULT_REG": 1
+          },
+          "attributes": {
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+          },
+          "port_directions": {
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+            "ACCUMCI": "input",
+            "ACCUMCO": "output",
+            "ADDSUBBOT": "input",
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+            "AHOLD": "input",
+            "B": "input",
+            "BHOLD": "input",
+            "C": "input",
+            "CE": "input",
+            "CHOLD": "input",
+            "CI": "input",
+            "CLK": "input",
+            "CO": "output",
+            "D": "input",
+            "DHOLD": "input",
+            "IRSTBOT": "input",
+            "IRSTTOP": "input",
+            "O": "output",
+            "OHOLDBOT": "input",
+            "OHOLDTOP": "input",
+            "OLOADBOT": "input",
+            "OLOADTOP": "input",
+            "ORSTBOT": "input",
+            "ORSTTOP": "input",
+            "SIGNEXTIN": "input",
+            "SIGNEXTOUT": "output"
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+            "BHOLD": [ "0" ],
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+            "OHOLDTOP": [ "0" ],
+            "OLOADBOT": [ "0" ],
+            "OLOADTOP": [ "0" ],
+            "ORSTBOT": [ "0" ],
+            "ORSTTOP": [ "0" ],
+            "SIGNEXTIN": [ "0" ],
+            "SIGNEXTOUT": [ ]
+          }
+        },
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+          "type": "SB_MAC16",
+          "parameters": {
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+            "A_SIGNED": 1,
+            "BOTADDSUB_CARRYSELECT": 0,
+            "BOTADDSUB_LOWERINPUT": 0,
+            "BOTADDSUB_UPPERINPUT": 0,
+            "BOTOUTPUT_SELECT": 2,
+            "BOT_8x8_MULT_REG": 1,
+            "B_REG": 1,
+            "B_SIGNED": 1,
+            "C_REG": 0,
+            "D_REG": 0,
+            "MODE_8x8": 1,
+            "NEG_TRIGGER": 0,
+            "PIPELINE_16x16_MULT_REG1": 1,
+            "PIPELINE_16x16_MULT_REG2": 0,
+            "TOPADDSUB_CARRYSELECT": 0,
+            "TOPADDSUB_LOWERINPUT": 0,
+            "TOPADDSUB_UPPERINPUT": 0,
+            "TOPOUTPUT_SELECT": 2,
+            "TOP_8x8_MULT_REG": 1
+          },
+          "attributes": {
+            "src": "../rtl/top.v:360|../rtl/compute.v:313|../rtl/compute.v:612"
+          },
+          "port_directions": {
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+            "ACCUMCI": "input",
+            "ACCUMCO": "output",
+            "ADDSUBBOT": "input",
+            "ADDSUBTOP": "input",
+            "AHOLD": "input",
+            "B": "input",
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diff --git a/ice40/regressions/issue0084/mlaccel.npnr b/ice40/regressions/issue0084/mlaccel.npnr
new file mode 100644
index 0000000..6038935
--- /dev/null
+++ b/ice40/regressions/issue0084/mlaccel.npnr
@@ -0,0 +1 @@
+--freq 25 --up5k
diff --git a/ice40/regressions/issue0084/mlaccel.pcf b/ice40/regressions/issue0084/mlaccel.pcf
new file mode 100644
index 0000000..414467b
--- /dev/null
+++ b/ice40/regressions/issue0084/mlaccel.pcf
@@ -0,0 +1,15 @@
+set_io clock      35
+
+set_io qpi_clk     4
+set_io qpi_csb     2
+set_io qpi_io0    47
+set_io qpi_io1    45
+set_io qpi_io2     3
+set_io qpi_io3    48
+set_io qpi_rdy    46
+set_io qpi_err    44
+
+set_io dbg1       43
+set_io dbg2       38
+set_io dbg3       34
+set_io dbg4       31
diff --git a/ice40/regressions/issue0084/mlaccel.sh b/ice40/regressions/issue0084/mlaccel.sh
new file mode 100644
index 0000000..3327547
--- /dev/null
+++ b/ice40/regressions/issue0084/mlaccel.sh
@@ -0,0 +1,3 @@
+:> mlaccel.log
+${NPNR} --json mlaccel.json --pcf mlaccel.pcf `cat mlaccel.npnr` > mlaccel.log 2>&1 || true
+grep "^ERROR: PACKAGE_PIN of SB_IO 'qpi_in_buf\\[1\\]' connected to more than a single top level IO.$" mlaccel.log
diff --git a/ice40/regressions/issue0098/j4a.json b/ice40/regressions/issue0098/j4a.json
new file mode 100644
index 0000000..7eb1da4
--- /dev/null
+++ b/ice40/regressions/issue0098/j4a.json
@@ -0,0 +1,126303 @@
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+            "WRITE_MODE": 3
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+            "WE": [ 2720 ]
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+            "INIT_6": "1111110011111100111111001111111011111100111111001111110011111100111111001111110011111100111111001111111011111100111111011111110011111111111111011111110011111100111111111111110011111101111111001111111011111101111111001111111111111100111111011111110011111111",
+            "INIT_7": "1111111011111100111111101111111011111100111111101111110011111110111111001111111011111100111111001111110011111100111111101111111011111110111111101111111011111110111111001111110011111110111111001111111011111100111111101111111011111110111111101111110011111110",
+            "INIT_8": "1111110011111100111111001111111011111100111111001111110011111100111111101111111011111110111111101111110011111110111111001111111011111100111111001111111011111100111111101111111011111100111111101111110011111100111111101111111011111100111111001111111011111100",
+            "INIT_9": "1111111011111101111111001111110011111100111111001111110011111101111111011111111111111101111111001111110111111101111111111111110011111111111111001111111011111101111111011111110011111100111111001111111011111100111111001111110011111101111111111111110011111100",
+            "INIT_A": "1111110111111110111111101111110011111101111111001111110011111100111111001111110011111100111111011111110011111110111111001111110111111101111111001111110011111100111111101111110111111110111111111111111011111100111111101111110011111101111111001111110011111100",
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+            "WE": [ 2720 ]
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+            "WE": [ 2720 ]
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+        },
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+            "WE": [ 2720 ]
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+            "INIT_6": "1111111011111100111111001111110011111100111111101111110011111110111111001111111011111110111111001111110011111110111111001111111111111101111111101111110011111111111111001111111011111100111111101111110011111111111111001111111111111110111111011111110011111111",
+            "INIT_7": "1111110011111110111111001111111011111100111111101111110011111110111111001111111011111110111111001111110011111110111111001111111011111100111111101111111011111100111111001111111011111100111111001111110011111110111111001111111011111110111111101111110011111110",
+            "INIT_8": "1111110011111110111111001111111011111110111111001111110011111110111111001111110011111100111111101111110011111100111111001111111011111100111111101111110011111100111111001111110011111100111111001111110011111110111111001111111011111100111111101111110011111110",
+            "INIT_9": "1111110011111111111111001111111111111100111111111111110011111111111111001111111111111110111111001111111011111101111111001111111011111100111111111111110011111111111111001111111111111101111111101111110011111110111111001111111111111100111111101111111011111100",
+            "INIT_A": "1111111011111101111111011111111011111100111111111111110111111110111111001111111111111100111111101111110011111111111111101111110011111110111111011111110111111110111111001111111011111100111111111111110011111101111111001111111011111100111111111111110011111111",
+            "INIT_B": "1111110011111111111111001111110111111100111111101111110011111111111111001111111111111100111111111111110011111101111111001111111111111100111111111111110011111111111111001111111011111110111111011111110011111111111111001111110111111101111111101111110011111111",
+            "INIT_C": "1111111011111111111111111111111011111110111111111111111011111111111111101111111011111110111111101111111011111110111111101111111111111100111111011111110011111101111111001111110011111100111111011111110011111101111111011111110011111100111111011111110011111101",
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+            "INIT_E": "1111111011111111111111111111111011111110111111111111111011111111111111101111111111111110111111111111111011111111111111101111111011111110111111101111111011111111111111101111111111111110111111111111111011111111111111101111111111111110111111111111111011111111",
+            "INIT_F": "1111111011111111111111101111111111111110111111111111111011111111111111101111111111111110111111111111111011111111111111101111111111111110111111111111111011111111111111101111111011111110111111111111111011111111111111101111111111111110111111101111111011111110",
+            "READ_MODE": 3,
+            "WRITE_MODE": 3
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+            "WE": [ 2720 ]
+          }
+        },
+        "_leds.io[0]._io": {
+          "hide_name": 0,
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+            "PIN_TYPE": 37
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+          "attributes": {
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+        "uart0_data": {
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+        },
+        "uart0_wr": {
+          "hide_name": 0,
+          "bits": [ 66 ],
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+        },
+        "uart_RXD": {
+          "hide_name": 0,
+          "bits": [ 2775 ],
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+          }
+        },
+        "unlocked": {
+          "hide_name": 0,
+          "bits": [ 2710 ],
+          "attributes": {
+            "src": "j4a.v:207"
+          }
+        },
+        "w8": {
+          "hide_name": 0,
+          "bits": [ 2774 ],
+          "attributes": {
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+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0098/j4a.npnr b/ice40/regressions/issue0098/j4a.npnr
new file mode 100644
index 0000000..4c4a45a
--- /dev/null
+++ b/ice40/regressions/issue0098/j4a.npnr
@@ -0,0 +1 @@
+--hx8k --package ct256
diff --git a/ice40/regressions/issue0098/j4a.pcf b/ice40/regressions/issue0098/j4a.pcf
new file mode 100644
index 0000000..578b3b9
--- /dev/null
+++ b/ice40/regressions/issue0098/j4a.pcf
@@ -0,0 +1,63 @@
+
+
+set_io D[0] C3
+set_io D[1] B3
+set_io D[2] C4
+set_io D[3] C5
+set_io D[4] A1
+set_io D[5] A2
+set_io D[6] B4
+set_io D[7] B5
+set_io D[8] A5
+set_io D[9] A6
+set_io D[10] C6
+set_io D[11] B6
+set_io D[12] B7
+set_io D[13] C7
+set_io D[14] A7
+set_io D[15] B8
+
+
+set_io TXD B12
+set_io RXD B10
+set_io pclk J3
+set_io reset A16
+set_io PIOS_00 R11
+set_io PIOS_01 P11
+set_io PIOS_02 P12
+set_io PIOS_03 R12
+
+set_io MISO N12 # in maxrefdes#24 J1 Pin 3
+set_io SCL P10 # out maxrefdes#24 J1 Pin 4
+set_io MOSI N10 # out maxrefdes#24 J1 Pin 2
+# note 3.3V and Gnd connected to maxrefdes#24 J1 pins 6 and 5 respectively also
+
+set_io PA[0] R16 # in ERR maxrefdes#24 J1 Pin 7
+set_io PA[1] T16 # out nCS1 maxrefdes#24 J1 Pin 1
+set_io PA[2] T15 # out nCS2 maxrefdes#24 J1 Pin 8
+set_io PA[3] T14 # out purge mosfet (on is purge-disabled)
+set_io PA[4] T13 # out valve enable control (via optoisolator) 
+set_io PA[5] P13 # in valve ok (via optoisolator, low is ok, hi is fault)
+set_io PA[6] M11
+set_io PA[7] T11
+
+set_io PA[8]  R10
+set_io PA[9]  T10
+set_io PA[10] P9
+set_io PA[11] P8
+set_io PA[12] R9
+set_io PA[13] T9
+set_io PA[14] T8
+set_io PA[15] T7 # out nCS for CAN bus module
+
+set_io MISO2  T1 # in CAN bus module 
+set_io SCL2  R2 # out CAN bus module 
+set_io MOSI2  R3 # out CAN bus module 
+
+set_io sCS E16
+set_io sSCL H16 # Must be this pin - H16 can get a clock to the GB.
+set_io sMOSI K14
+set_io spower[0] C16
+set_io spower[1] F16
+set_io spower[2] J15
+
diff --git a/ice40/regressions/issue0106/top.json b/ice40/regressions/issue0106/top.json
new file mode 100644
index 0000000..670a580
--- /dev/null
+++ b/ice40/regressions/issue0106/top.json
@@ -0,0 +1,6876 @@
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+}
diff --git a/ice40/regressions/issue0106/top.npnr b/ice40/regressions/issue0106/top.npnr
new file mode 100644
index 0000000..836602c
--- /dev/null
+++ b/ice40/regressions/issue0106/top.npnr
@@ -0,0 +1 @@
+--lp384
diff --git a/ice40/regressions/issue0106/top.pcf b/ice40/regressions/issue0106/top.pcf
new file mode 100644
index 0000000..9830f1e
--- /dev/null
+++ b/ice40/regressions/issue0106/top.pcf
@@ -0,0 +1,2 @@
+set_io led 18
+set_io clock 19
diff --git a/ice40/regressions/issue0106/top.v b/ice40/regressions/issue0106/top.v
new file mode 100644
index 0000000..117d8fe
--- /dev/null
+++ b/ice40/regressions/issue0106/top.v
@@ -0,0 +1,15 @@
+`timescale 1ns / 1ps
+
+module top(input clock,
+	   output led);
+
+   reg [23:0] 	 count = 0;
+
+   always @ (posedge clock)
+     begin
+	count <= count + 1'b1;
+     end
+
+   assign led = count[23];
+
+endmodule
diff --git a/ice40/regressions/issue0106/top.ys b/ice40/regressions/issue0106/top.ys
new file mode 100644
index 0000000..0fb45b0
--- /dev/null
+++ b/ice40/regressions/issue0106/top.ys
@@ -0,0 +1,2 @@
+read_verilog top.v
+synth_ice40 -top top -json top.json
diff --git a/ice40/regressions/issue0117/top.json b/ice40/regressions/issue0117/top.json
new file mode 100644
index 0000000..aa1b38f
--- /dev/null
+++ b/ice40/regressions/issue0117/top.json
@@ -0,0 +1,5282 @@
+{
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diff --git a/ice40/regressions/issue0117/top.v b/ice40/regressions/issue0117/top.v
new file mode 100644
index 0000000..9150834
--- /dev/null
+++ b/ice40/regressions/issue0117/top.v
@@ -0,0 +1,5 @@
+module bug (
+    inout wire gpio
+);
+
+endmodule
diff --git a/ice40/regressions/issue0117/top.ys b/ice40/regressions/issue0117/top.ys
new file mode 100644
index 0000000..0efb9f9
--- /dev/null
+++ b/ice40/regressions/issue0117/top.ys
@@ -0,0 +1,2 @@
+read_verilog top.v
+synth_ice40 -json top.json
diff --git a/ice40/regressions/issue0120/mem.init b/ice40/regressions/issue0120/mem.init
new file mode 100644
index 0000000..7b9fd27
--- /dev/null
+++ b/ice40/regressions/issue0120/mem.init
@@ -0,0 +1,11 @@
+55
+53
+42
+54
+65
+73
+74
+53
+6f
+43
+0
diff --git a/ice40/regressions/issue0120/top.json b/ice40/regressions/issue0120/top.json
new file mode 100644
index 0000000..9c678a5
--- /dev/null
+++ b/ice40/regressions/issue0120/top.json
@@ -0,0 +1,82893 @@
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+        "usbdevice_usbfstx_data_shifter_shifter": {
+          "hide_name": 0,
+          "bits": [ 884, 552, 553, 554, 555, 556, 549, 550, 551 ],
+          "attributes": {
+            "src": "top.v:313"
+          }
+        },
+        "usbdevice_usbfstx_load_crc16": {
+          "hide_name": 0,
+          "bits": [ 558 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:302"
+          }
+        },
+        "usbdevice_usbfstx_mux_stuff_bit_strobe": {
+          "hide_name": 0,
+          "bits": [ 588 ],
+          "attributes": {
+            "src": "top.v:328"
+          }
+        },
+        "usbdevice_usbfstx_mux_stuff_data": {
+          "hide_name": 0,
+          "bits": [ 827 ],
+          "attributes": {
+            "src": "top.v:326"
+          }
+        },
+        "usbdevice_usbfstx_mux_stuff_oe": {
+          "hide_name": 0,
+          "bits": [ 2817 ],
+          "attributes": {
+            "src": "top.v:325"
+          }
+        },
+        "usbdevice_usbfstx_mux_stuff_se0": {
+          "hide_name": 0,
+          "bits": [ 2818 ],
+          "attributes": {
+            "src": "top.v:327"
+          }
+        },
+        "usbdevice_usbfstx_nrzi_o_oe": {
+          "hide_name": 0,
+          "bits": [ 2821 ],
+          "attributes": {
+            "src": "top.v:339"
+          }
+        },
+        "usbdevice_usbfstx_nrzi_o_usbn": {
+          "hide_name": 0,
+          "bits": [ 2820 ],
+          "attributes": {
+            "src": "top.v:338"
+          }
+        },
+        "usbdevice_usbfstx_nrzi_o_usbp": {
+          "hide_name": 0,
+          "bits": [ 2819 ],
+          "attributes": {
+            "src": "top.v:337"
+          }
+        },
+        "usbdevice_usbfstx_nrzi_oe": {
+          "hide_name": 0,
+          "bits": [ 147 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:336"
+          }
+        },
+        "usbdevice_usbfstx_nrzi_usbn": {
+          "hide_name": 0,
+          "bits": [ 144 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:335"
+          }
+        },
+        "usbdevice_usbfstx_nrzi_usbp": {
+          "hide_name": 0,
+          "bits": [ 142 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:334"
+          }
+        },
+        "usbdevice_usbfstx_o_oe": {
+          "hide_name": 0,
+          "bits": [ 2824 ],
+          "attributes": {
+            "src": "top.v:344"
+          }
+        },
+        "usbdevice_usbfstx_o_usbn": {
+          "hide_name": 0,
+          "bits": [ 2823 ],
+          "attributes": {
+            "src": "top.v:343"
+          }
+        },
+        "usbdevice_usbfstx_o_usbp": {
+          "hide_name": 0,
+          "bits": [ 2822 ],
+          "attributes": {
+            "src": "top.v:342"
+          }
+        },
+        "usbdevice_usbfstx_pid_is_data": {
+          "hide_name": 0,
+          "bits": [ 562 ],
+          "attributes": {
+            "src": "top.v:324"
+          }
+        },
+        "usbdevice_usbfstx_pid_shifter_not_empty": {
+          "hide_name": 0,
+          "bits": [ 561 ],
+          "attributes": {
+            "src": "top.v:312"
+          }
+        },
+        "usbdevice_usbfstx_pid_shifter_o_data": {
+          "hide_name": 0,
+          "bits": [ 1391 ],
+          "attributes": {
+            "src": "top.v:310"
+          }
+        },
+        "usbdevice_usbfstx_pid_shifter_shifter": {
+          "hide_name": 0,
+          "bits": [ 1391, 538, 539, 540, 541, 542, 535, 536, 537 ],
+          "attributes": {
+            "src": "top.v:309"
+          }
+        },
+        "usbdevice_usbfstx_pkt_active": {
+          "hide_name": 0,
+          "bits": [ 141 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:296"
+          }
+        },
+        "usbdevice_usbfstx_sync_shifter_not_empty": {
+          "hide_name": 0,
+          "bits": [ 834 ],
+          "attributes": {
+            "src": "top.v:308"
+          }
+        },
+        "usbdevice_usbfstx_sync_shifter_o_data": {
+          "hide_name": 0,
+          "bits": [ 1387 ],
+          "attributes": {
+            "src": "top.v:306"
+          }
+        },
+        "usbdevice_usbfstx_sync_shifter_shifter": {
+          "hide_name": 0,
+          "bits": [ 1387, 524, 525, 526, 527, 528, 521, 522, 523 ],
+          "attributes": {
+            "src": "top.v:305"
+          }
+        },
+        "usbdevice_valid_ack_packet": {
+          "hide_name": 0,
+          "bits": [ 2317 ],
+          "attributes": {
+            "src": "top.v:352"
+          }
+        },
+        "usbdevice_valid_data_packet": {
+          "hide_name": 0,
+          "bits": [ 2317 ],
+          "attributes": {
+            "src": "top.v:350"
+          }
+        },
+        "usbdevice_valid_request_token": {
+          "hide_name": 0,
+          "bits": [ 590 ],
+          "attributes": {
+            "src": "top.v:348"
+          }
+        },
+        "usbdevice_valid_request_token_pre": {
+          "hide_name": 0,
+          "bits": [ 2317 ],
+          "attributes": {
+            "src": "top.v:347"
+          }
+        },
+        "usbtestsoc_crg_reset_delay": {
+          "hide_name": 0,
+          "bits": [ 2261, 2262, 2263, 2264, 2265, 2266, 2267, 2268, 2269, 2270, 2271, 2251 ],
+          "attributes": {
+            "src": "top.v:79"
+          }
+        },
+        "usbtestsoc_spiflash_bitbang_en_storage": {
+          "hide_name": 0,
+          "bits": [ 792 ],
+          "attributes": {
+            "src": "top.v:99"
+          }
+        },
+        "usbtestsoc_spiflash_bitbang_en_storage_full": {
+          "hide_name": 0,
+          "bits": [ 792 ],
+          "attributes": {
+            "src": "top.v:98"
+          }
+        },
+        "usbtestsoc_spiflash_bitbang_storage": {
+          "hide_name": 0,
+          "bits": [ 796, 790, 793, 1137 ],
+          "attributes": {
+            "src": "top.v:95"
+          }
+        },
+        "usbtestsoc_spiflash_bitbang_storage_full": {
+          "hide_name": 0,
+          "bits": [ 796, 790, 793, 1137 ],
+          "attributes": {
+            "src": "top.v:94"
+          }
+        },
+        "usbtestsoc_spiflash_bus_ack": {
+          "hide_name": 0,
+          "bits": [ 84 ],
+          "attributes": {
+            "src": "top.v:89"
+          }
+        },
+        "usbtestsoc_spiflash_bus_adr": {
+          "hide_name": 0,
+          "bits": [ 1846, 1848, 1850, 1852, 1854, 1856, 1858, 1860, 1862, 1864, 1866, 1868, 1870, 1872, 936, 939, 942, 945, 948, 951, 954, 957, "x", "x", "x", "x" ],
+          "attributes": {
+          }
+        },
+        "usbtestsoc_spiflash_bus_dat_r": {
+          "hide_name": 0,
+          "bits": [ 1600, 1605, 1609, 1613, 1617, 1621, 1625, 1630, 1634, 1638, 1642, 1646, 1650, 1654, 1658, 1662, 1666, 1670, 1674, 1678, 1682, 1686, 1690, 935, 938, 941, 944, 947, 950, 953, 956, 795 ],
+          "attributes": {
+            "src": "top.v:85"
+          }
+        },
+        "usbtestsoc_spiflash_bus_dat_w": {
+          "hide_name": 0,
+          "bits": [ 1631, 1635, 1639, 1643, 1647, 1651, 1655, 1659, 1663, 1667, 1671, 1675, 1679, 1683, 1687, 1691, 1694, 1697, 1700, 1703, 1706, 1709, 1712, 1715, 1801, 1808, 1814, 1820, 1826, 1832, 1838, 1843 ],
+          "attributes": {
+            "src": "top.v:84"
+          }
+        },
+        "usbtestsoc_spiflash_clk1": {
+          "hide_name": 0,
+          "bits": [ 791 ],
+          "attributes": {
+            "src": "top.v:102"
+          }
+        },
+        "usbtestsoc_spiflash_counter": {
+          "hide_name": 0,
+          "bits": [ 47, 49, 50, 51, 54, 52, 53, 55 ],
+          "attributes": {
+            "src": "top.v:106"
+          }
+        },
+        "usbtestsoc_spiflash_i": {
+          "hide_name": 0,
+          "bits": [ 370 ],
+          "attributes": {
+            "src": "top.v:104"
+          }
+        },
+        "usbtestsoc_spiflash_miso1": {
+          "hide_name": 0,
+          "bits": [ 2797 ],
+          "attributes": {
+            "src": "top.v:105"
+          }
+        },
+        "usbtestsoc_spiflash_sr": {
+          "hide_name": 0,
+          "bits": [ 1600, 1605, 1609, 1613, 1617, 1621, 1625, 1630, 1634, 1638, 1642, 1646, 1650, 1654, 1658, 1662, 1666, 1670, 1674, 1678, 1682, 1686, 1690, 935, 938, 941, 944, 947, 950, 953, 956, 795 ],
+          "attributes": {
+            "src": "top.v:103"
+          }
+        },
+        "usbtestsoc_usbtestsoc_adr": {
+          "hide_name": 0,
+          "bits": [ 208, 209, 211, 210, 276, 1160, "x", "x", "x", 205, 207, 202, 203, 206 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:28"
+          }
+        },
+        "usbtestsoc_usbtestsoc_bus_errors": {
+          "hide_name": 0,
+          "bits": [ 219, 251, 241, 242, 235, 236, 237, 238, 233, 234, 227, 228, 229, 230, 239, 240, 260, 261, 254, 255, 256, 257, 231, 232, 252, 253, 247, 248, 249, 250, 258, 259 ],
+          "attributes": {
+            "src": "top.v:27"
+          }
+        },
+        "usbtestsoc_usbtestsoc_bus_errors_status": {
+          "hide_name": 0,
+          "bits": [ 219, 251, 241, 242, 235, 236, 237, 238, 233, 234, 227, 228, 229, 230, 239, 240, 260, 261, 254, 255, 256, 257, 231, 232, 252, 253, 247, 248, 249, 250, 258, 259 ],
+          "attributes": {
+            "src": "top.v:24"
+          }
+        },
+        "usbtestsoc_usbtestsoc_bus_wishbone_ack": {
+          "hide_name": 0,
+          "bits": [ 83 ],
+          "attributes": {
+            "src": "top.v:38"
+          }
+        },
+        "usbtestsoc_usbtestsoc_bus_wishbone_adr": {
+          "hide_name": 0,
+          "bits": [ 1846, 1848, 1850, 1852, 1854, 1856, 1858, 1860, 1862, 1864, 1866, 1868, 1870, 1872, 936, 939, 942, 945, 948, 951, 954, 957, "x", "x", "x", "x" ],
+          "attributes": {
+          }
+        },
+        "usbtestsoc_usbtestsoc_bus_wishbone_dat_r": {
+          "hide_name": 0,
+          "bits": [ 1602, 1606, 1610, 1614, 1618, 1622, 1626, 1629, "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "attributes": {
+            "src": "top.v:34"
+          }
+        },
+        "usbtestsoc_usbtestsoc_bus_wishbone_dat_w": {
+          "hide_name": 0,
+          "bits": [ 1631, 1635, 1639, 1643, 1647, 1651, 1655, 1659, 1663, 1667, 1671, 1675, 1679, 1683, 1687, 1691, 1694, 1697, 1700, 1703, 1706, 1709, 1712, 1715, 1801, 1808, 1814, 1820, 1826, 1832, 1838, 1843 ],
+          "attributes": {
+            "src": "top.v:33"
+          }
+        },
+        "usbtestsoc_usbtestsoc_counter": {
+          "hide_name": 0,
+          "bits": [ 266, 263 ],
+          "attributes": {
+            "src": "top.v:43"
+          }
+        },
+        "usbtestsoc_usbtestsoc_dat_r": {
+          "hide_name": 0,
+          "bits": [ 2165, 2176, 2186, 2196, 2208, 2216, 2224, 2232 ],
+          "attributes": {
+            "src": "top.v:31"
+          }
+        },
+        "usbtestsoc_usbtestsoc_dat_w": {
+          "hide_name": 0,
+          "bits": [ 349, 40, 36, 17, 42, 38, 34, 2796 ],
+          "attributes": {
+            "src": "top.v:30"
+          }
+        },
+        "usbtestsoc_usbtestsoc_en_storage": {
+          "hide_name": 0,
+          "bits": [ 355 ],
+          "attributes": {
+            "src": "top.v:51"
+          }
+        },
+        "usbtestsoc_usbtestsoc_en_storage_full": {
+          "hide_name": 0,
+          "bits": [ 355 ],
+          "attributes": {
+            "src": "top.v:50"
+          }
+        },
+        "usbtestsoc_usbtestsoc_eventmanager_pending_r": {
+          "hide_name": 0,
+          "bits": [ 349 ],
+          "attributes": {
+            "src": "top.v:67"
+          }
+        },
+        "usbtestsoc_usbtestsoc_eventmanager_pending_w": {
+          "hide_name": 0,
+          "bits": [ 973 ],
+          "attributes": {
+            "src": "top.v:68"
+          }
+        },
+        "usbtestsoc_usbtestsoc_eventmanager_status_r": {
+          "hide_name": 0,
+          "bits": [ 349 ],
+          "attributes": {
+            "src": "top.v:64"
+          }
+        },
+        "usbtestsoc_usbtestsoc_eventmanager_status_w": {
+          "hide_name": 0,
+          "bits": [ 302 ],
+          "attributes": {
+            "src": "top.v:65"
+          }
+        },
+        "usbtestsoc_usbtestsoc_eventmanager_storage": {
+          "hide_name": 0,
+          "bits": [ 967 ],
+          "attributes": {
+            "src": "top.v:70"
+          }
+        },
+        "usbtestsoc_usbtestsoc_eventmanager_storage_full": {
+          "hide_name": 0,
+          "bits": [ 967 ],
+          "attributes": {
+            "src": "top.v:69"
+          }
+        },
+        "usbtestsoc_usbtestsoc_load_storage": {
+          "hide_name": 0,
+          "bits": [ 985, 1004, 1027, 1036, 1053, 1089, 1110, 1125, 984, 1006, 1023, 1046, 1064, 1081, 1104, 1127, 966, 1005, 1017, 1048, 1066, 1073, 1108, 1124, 980, 993, 1019, 1042, 1065, 1088, 1107, 1120 ],
+          "attributes": {
+            "src": "top.v:45"
+          }
+        },
+        "usbtestsoc_usbtestsoc_load_storage_full": {
+          "hide_name": 0,
+          "bits": [ 985, 1004, 1027, 1036, 1053, 1089, 1110, 1125, 984, 1006, 1023, 1046, 1064, 1081, 1104, 1127, 966, 1005, 1017, 1048, 1066, 1073, 1108, 1124, 980, 993, 1019, 1042, 1065, 1088, 1107, 1120 ],
+          "attributes": {
+            "src": "top.v:44"
+          }
+        },
+        "usbtestsoc_usbtestsoc_reload_storage": {
+          "hide_name": 0,
+          "bits": [ 974, 990, 1018, 1041, 1068, 1085, 1106, 1131, 981, 1001, 1020, 1038, 1063, 1080, 1103, 1128, 971, 1000, 1025, 1032, 1060, 1087, 1098, 1115, 979, 1003, 1026, 1035, 1062, 1079, 1105, 1121 ],
+          "attributes": {
+            "src": "top.v:48"
+          }
+        },
+        "usbtestsoc_usbtestsoc_reload_storage_full": {
+          "hide_name": 0,
+          "bits": [ 974, 990, 1018, 1041, 1068, 1085, 1106, 1131, 981, 1001, 1020, 1038, 1063, 1080, 1103, 1128, 971, 1000, 1025, 1032, 1060, 1087, 1098, 1115, 979, 1003, 1026, 1035, 1062, 1079, 1105, 1121 ],
+          "attributes": {
+            "src": "top.v:47"
+          }
+        },
+        "usbtestsoc_usbtestsoc_reset_reset_r": {
+          "hide_name": 0,
+          "bits": [ 349 ],
+          "attributes": {
+            "src": "top.v:19"
+          }
+        },
+        "usbtestsoc_usbtestsoc_storage": {
+          "hide_name": 0,
+          "bits": [ 1218, 1229, 1230, 2989, 2990, 2991, 2992, 1280, 1217, 2993, 2994, 1243, 2995, 1263, 2996, 1286, 1210, 1228, 2997, 1248, 2998, 2999, 1279, 1289, 1219, 3000, 1239, 1249, 3001, 1268, 1278, 1288 ],
+          "attributes": {
+            "src": "top.v:22"
+          }
+        },
+        "usbtestsoc_usbtestsoc_storage_full": {
+          "hide_name": 0,
+          "bits": [ 1218, 1229, 1230, 2989, 2990, 2991, 2992, 1280, 1217, 2993, 2994, 1243, 2995, 1263, 2996, 1286, 1210, 1228, 2997, 1248, 2998, 2999, 1279, 1289, 1219, 3000, 1239, 1249, 3001, 1268, 1278, 1288 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "usbtestsoc_usbtestsoc_update_value_r": {
+          "hide_name": 0,
+          "bits": [ 349 ],
+          "attributes": {
+            "src": "top.v:54"
+          }
+        },
+        "usbtestsoc_usbtestsoc_value": {
+          "hide_name": 0,
+          "bits": [ 335, 336, 337, 338, 331, 332, 333, 334, 343, 344, 345, 346, 339, 340, 341, 342, 317, 318, 319, 320, 313, 314, 315, 316, 325, 326, 327, 328, 321, 322, 323, 324 ],
+          "attributes": {
+            "src": "top.v:72"
+          }
+        },
+        "usbtestsoc_usbtestsoc_value_status": {
+          "hide_name": 0,
+          "bits": [ 982, 999, 1014, 1043, 1059, 1086, 1109, 1126, 983, 998, 1024, 1037, 1061, 1078, 1097, 1117, 963, 997, 1011, 1039, 1067, 1084, 1095, 1119, 969, 996, 1016, 1047, 1056, 1076, 1093, 1130 ],
+          "attributes": {
+            "src": "top.v:56"
+          }
+        },
+        "usbtestsoc_usbtestsoc_we": {
+          "hide_name": 0,
+          "bits": [ 198 ],
+          "attributes": {
+            "src": "top.v:29"
+          }
+        },
+        "usbtestsoc_usbtestsoc_zero_old_trigger": {
+          "hide_name": 0,
+          "bits": [ 303 ],
+          "attributes": {
+            "src": "top.v:62"
+          }
+        },
+        "usbtestsoc_usbtestsoc_zero_pending": {
+          "hide_name": 0,
+          "bits": [ 973 ],
+          "attributes": {
+            "src": "top.v:59"
+          }
+        },
+        "usbtestsoc_usbtestsoc_zero_status": {
+          "hide_name": 0,
+          "bits": [ 302 ],
+          "attributes": {
+            "src": "top.v:58"
+          }
+        },
+        "usbtestsoc_usbtestsoc_zero_trigger": {
+          "hide_name": 0,
+          "bits": [ 302 ],
+          "attributes": {
+            "src": "top.v:60"
+          }
+        },
+        "user_led0": {
+          "hide_name": 0,
+          "bits": [ 12 ],
+          "attributes": {
+            "src": "top.v:15"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0120/top.npnr b/ice40/regressions/issue0120/top.npnr
new file mode 100644
index 0000000..7da092a
--- /dev/null
+++ b/ice40/regressions/issue0120/top.npnr
@@ -0,0 +1 @@
+--lp8k --package cm81 --freq 16.0
diff --git a/ice40/regressions/issue0120/top.pcf b/ice40/regressions/issue0120/top.pcf
new file mode 100644
index 0000000..9a82db4
--- /dev/null
+++ b/ice40/regressions/issue0120/top.pcf
@@ -0,0 +1,13 @@
+set_io clk16 B2
+set_io spiflash_cs_n F7
+set_io spiflash_clk G7
+set_io spiflash_mosi G6
+set_io spiflash_miso H7
+set_io spiflash_wp H4
+set_io spiflash_hold J8
+set_io serial_rx A2
+set_io serial_tx A1
+set_io usb_d_p B4
+set_io usb_d_n A4
+set_io usb_pullup A3
+set_io user_led0 B3
diff --git a/ice40/regressions/issue0120/top.sh b/ice40/regressions/issue0120/top.sh
new file mode 100644
index 0000000..43da7d4
--- /dev/null
+++ b/ice40/regressions/issue0120/top.sh
@@ -0,0 +1,3 @@
+:> top.log
+${NPNR} --json top.json --pcf top.pcf `cat top.npnr` > top.log 2>&1 || true
+grep "^ERROR: PACKAGE_PIN of SB_IO 'SB_IO' connected to more than a single top level IO.$" top.log
diff --git a/ice40/regressions/issue0120/top.v b/ice40/regressions/issue0120/top.v
new file mode 100644
index 0000000..813e887
--- /dev/null
+++ b/ice40/regressions/issue0120/top.v
@@ -0,0 +1,3971 @@
+/* Machine-generated using LiteX gen */
+module top(
+	input clk16,
+	output reg spiflash_cs_n,
+	output reg spiflash_clk,
+	output reg spiflash_mosi,
+	input spiflash_miso,
+	output spiflash_wp,
+	output spiflash_hold,
+	input serial_rx,
+	output reg serial_tx,
+	inout usb_d_p,
+	inout usb_d_n,
+	output usb_pullup,
+	output user_led0
+);
+
+wire usbtestsoc_usbtestsoc_reset_reset_re;
+wire usbtestsoc_usbtestsoc_reset_reset_r;
+reg usbtestsoc_usbtestsoc_reset_reset_w = 1'd0;
+reg [31:0] usbtestsoc_usbtestsoc_storage_full = 32'd305419896;
+wire [31:0] usbtestsoc_usbtestsoc_storage;
+reg usbtestsoc_usbtestsoc_re = 1'd0;
+wire [31:0] usbtestsoc_usbtestsoc_bus_errors_status;
+wire usbtestsoc_usbtestsoc_reset;
+wire usbtestsoc_usbtestsoc_bus_error;
+reg [31:0] usbtestsoc_usbtestsoc_bus_errors = 32'd0;
+reg [13:0] usbtestsoc_usbtestsoc_adr = 14'd0;
+reg usbtestsoc_usbtestsoc_we = 1'd0;
+reg [7:0] usbtestsoc_usbtestsoc_dat_w = 8'd0;
+wire [7:0] usbtestsoc_usbtestsoc_dat_r;
+wire [29:0] usbtestsoc_usbtestsoc_bus_wishbone_adr;
+wire [31:0] usbtestsoc_usbtestsoc_bus_wishbone_dat_w;
+reg [31:0] usbtestsoc_usbtestsoc_bus_wishbone_dat_r = 32'd0;
+wire [3:0] usbtestsoc_usbtestsoc_bus_wishbone_sel;
+wire usbtestsoc_usbtestsoc_bus_wishbone_cyc;
+wire usbtestsoc_usbtestsoc_bus_wishbone_stb;
+reg usbtestsoc_usbtestsoc_bus_wishbone_ack = 1'd0;
+wire usbtestsoc_usbtestsoc_bus_wishbone_we;
+wire [2:0] usbtestsoc_usbtestsoc_bus_wishbone_cti;
+wire [1:0] usbtestsoc_usbtestsoc_bus_wishbone_bte;
+reg usbtestsoc_usbtestsoc_bus_wishbone_err = 1'd0;
+reg [1:0] usbtestsoc_usbtestsoc_counter = 2'd0;
+reg [31:0] usbtestsoc_usbtestsoc_load_storage_full = 32'd0;
+wire [31:0] usbtestsoc_usbtestsoc_load_storage;
+reg usbtestsoc_usbtestsoc_load_re = 1'd0;
+reg [31:0] usbtestsoc_usbtestsoc_reload_storage_full = 32'd0;
+wire [31:0] usbtestsoc_usbtestsoc_reload_storage;
+reg usbtestsoc_usbtestsoc_reload_re = 1'd0;
+reg usbtestsoc_usbtestsoc_en_storage_full = 1'd0;
+wire usbtestsoc_usbtestsoc_en_storage;
+reg usbtestsoc_usbtestsoc_en_re = 1'd0;
+wire usbtestsoc_usbtestsoc_update_value_re;
+wire usbtestsoc_usbtestsoc_update_value_r;
+reg usbtestsoc_usbtestsoc_update_value_w = 1'd0;
+reg [31:0] usbtestsoc_usbtestsoc_value_status = 32'd0;
+wire usbtestsoc_usbtestsoc_irq;
+wire usbtestsoc_usbtestsoc_zero_status;
+reg usbtestsoc_usbtestsoc_zero_pending = 1'd0;
+wire usbtestsoc_usbtestsoc_zero_trigger;
+reg usbtestsoc_usbtestsoc_zero_clear = 1'd0;
+reg usbtestsoc_usbtestsoc_zero_old_trigger = 1'd0;
+wire usbtestsoc_usbtestsoc_eventmanager_status_re;
+wire usbtestsoc_usbtestsoc_eventmanager_status_r;
+wire usbtestsoc_usbtestsoc_eventmanager_status_w;
+wire usbtestsoc_usbtestsoc_eventmanager_pending_re;
+wire usbtestsoc_usbtestsoc_eventmanager_pending_r;
+wire usbtestsoc_usbtestsoc_eventmanager_pending_w;
+reg usbtestsoc_usbtestsoc_eventmanager_storage_full = 1'd0;
+wire usbtestsoc_usbtestsoc_eventmanager_storage;
+reg usbtestsoc_usbtestsoc_eventmanager_re = 1'd0;
+reg [31:0] usbtestsoc_usbtestsoc_value = 32'd0;
+wire sys_clk;
+wire sys_rst;
+wire usb_48_clk;
+reg usbtestsoc_crg_reset = 1'd0;
+wire por_clk;
+wire por_rst;
+reg [11:0] usbtestsoc_crg_reset_delay = 12'd4095;
+wire [159:0] usbtestsoc_status;
+wire [63:0] usbtestsoc_platform_status;
+wire [63:0] usbtestsoc_target_status;
+wire [29:0] usbtestsoc_spiflash_bus_adr;
+wire [31:0] usbtestsoc_spiflash_bus_dat_w;
+wire [31:0] usbtestsoc_spiflash_bus_dat_r;
+wire [3:0] usbtestsoc_spiflash_bus_sel;
+wire usbtestsoc_spiflash_bus_cyc;
+wire usbtestsoc_spiflash_bus_stb;
+reg usbtestsoc_spiflash_bus_ack = 1'd0;
+wire usbtestsoc_spiflash_bus_we;
+wire [2:0] usbtestsoc_spiflash_bus_cti;
+wire [1:0] usbtestsoc_spiflash_bus_bte;
+reg usbtestsoc_spiflash_bus_err = 1'd0;
+reg [3:0] usbtestsoc_spiflash_bitbang_storage_full = 4'd0;
+wire [3:0] usbtestsoc_spiflash_bitbang_storage;
+reg usbtestsoc_spiflash_bitbang_re = 1'd0;
+reg usbtestsoc_spiflash_miso_status = 1'd0;
+reg usbtestsoc_spiflash_bitbang_en_storage_full = 1'd0;
+wire usbtestsoc_spiflash_bitbang_en_storage;
+reg usbtestsoc_spiflash_bitbang_en_re = 1'd0;
+reg usbtestsoc_spiflash_cs_n1 = 1'd1;
+reg usbtestsoc_spiflash_clk1 = 1'd0;
+reg [31:0] usbtestsoc_spiflash_sr = 32'd0;
+reg usbtestsoc_spiflash_i = 1'd0;
+reg usbtestsoc_spiflash_miso1 = 1'd0;
+reg [7:0] usbtestsoc_spiflash_counter = 8'd0;
+reg [31:0] uartwishbonebridge_storage = 32'd30923764;
+reg uartwishbonebridge_sink_valid = 1'd0;
+reg uartwishbonebridge_sink_ready = 1'd0;
+wire uartwishbonebridge_sink_last;
+reg [7:0] uartwishbonebridge_sink_payload_data = 8'd0;
+reg uartwishbonebridge_uart_clk_txen = 1'd0;
+reg [31:0] uartwishbonebridge_phase_accumulator_tx = 32'd0;
+reg [7:0] uartwishbonebridge_tx_reg = 8'd0;
+reg [3:0] uartwishbonebridge_tx_bitcount = 4'd0;
+reg uartwishbonebridge_tx_busy = 1'd0;
+reg uartwishbonebridge_source_valid = 1'd0;
+wire uartwishbonebridge_source_ready;
+reg [7:0] uartwishbonebridge_source_payload_data = 8'd0;
+reg uartwishbonebridge_uart_clk_rxen = 1'd0;
+reg [31:0] uartwishbonebridge_phase_accumulator_rx = 32'd0;
+wire uartwishbonebridge_rx;
+reg uartwishbonebridge_rx_r = 1'd0;
+reg [7:0] uartwishbonebridge_rx_reg = 8'd0;
+reg [3:0] uartwishbonebridge_rx_bitcount = 4'd0;
+reg uartwishbonebridge_rx_busy = 1'd0;
+wire [29:0] uartwishbonebridge_wishbone_adr;
+wire [31:0] uartwishbonebridge_wishbone_dat_w;
+wire [31:0] uartwishbonebridge_wishbone_dat_r;
+wire [3:0] uartwishbonebridge_wishbone_sel;
+reg uartwishbonebridge_wishbone_cyc = 1'd0;
+reg uartwishbonebridge_wishbone_stb = 1'd0;
+wire uartwishbonebridge_wishbone_ack;
+reg uartwishbonebridge_wishbone_we = 1'd0;
+reg [2:0] uartwishbonebridge_wishbone_cti = 3'd0;
+reg [1:0] uartwishbonebridge_wishbone_bte = 2'd0;
+wire uartwishbonebridge_wishbone_err;
+reg [2:0] uartwishbonebridge_byte_counter = 3'd0;
+reg uartwishbonebridge_byte_counter_reset = 1'd0;
+reg uartwishbonebridge_byte_counter_ce = 1'd0;
+reg [2:0] uartwishbonebridge_word_counter = 3'd0;
+reg uartwishbonebridge_word_counter_reset = 1'd0;
+reg uartwishbonebridge_word_counter_ce = 1'd0;
+reg [7:0] uartwishbonebridge_cmd = 8'd0;
+reg uartwishbonebridge_cmd_ce = 1'd0;
+reg [7:0] uartwishbonebridge_length = 8'd0;
+reg uartwishbonebridge_length_ce = 1'd0;
+reg [31:0] uartwishbonebridge_address = 32'd0;
+reg uartwishbonebridge_address_ce = 1'd0;
+reg [31:0] uartwishbonebridge_data = 32'd0;
+reg uartwishbonebridge_rx_data_ce = 1'd0;
+reg uartwishbonebridge_tx_data_ce = 1'd0;
+wire uartwishbonebridge_reset;
+wire uartwishbonebridge_wait;
+wire uartwishbonebridge_done;
+reg [20:0] uartwishbonebridge_count = 21'd1600000;
+reg uartwishbonebridge_is_ongoing = 1'd0;
+reg usbdevice0 = 1'd0;
+reg usbdevice1 = 1'd0;
+reg usbdevice2 = 1'd0;
+reg usbdevice3 = 1'd0;
+reg usbdevice4 = 1'd0;
+reg usbdevice5 = 1'd0;
+reg usbdevice6 = 1'd0;
+reg usbdevice7 = 1'd0;
+reg usbdevice8 = 1'd0;
+reg usbdevice9 = 1'd0;
+reg usbdevice10 = 1'd0;
+reg usbdevice11 = 1'd0;
+reg usbdevice12 = 1'd0;
+reg usbdevice13 = 1'd0;
+reg usbdevice14 = 1'd0;
+reg usbdevice15 = 1'd0;
+reg usbdevice_o_out_commit = 1'd0;
+reg usbdevice_o_out_rollback = 1'd0;
+reg usbdevice16 = 1'd0;
+reg usbdevice17 = 1'd0;
+reg usbdevice18 = 1'd0;
+reg usbdevice19 = 1'd0;
+reg usbdevice20 = 1'd0;
+reg usbdevice21 = 1'd0;
+reg usbdevice22 = 1'd0;
+reg usbdevice23 = 1'd0;
+reg usbdevice24 = 1'd0;
+reg usbdevice25 = 1'd0;
+reg usbdevice26 = 1'd0;
+reg usbdevice27 = 1'd0;
+reg usbdevice28 = 1'd0;
+reg usbdevice29 = 1'd0;
+reg usbdevice30 = 1'd0;
+reg usbdevice31 = 1'd0;
+reg usbdevice32 = 1'd0;
+reg usbdevice33 = 1'd0;
+reg usbdevice34 = 1'd0;
+reg usbdevice35 = 1'd0;
+reg usbdevice36 = 1'd0;
+reg usbdevice37 = 1'd0;
+reg usbdevice38 = 1'd0;
+reg usbdevice39 = 1'd0;
+reg usbdevice40 = 1'd0;
+reg usbdevice41 = 1'd0;
+reg usbdevice42 = 1'd0;
+reg usbdevice43 = 1'd0;
+reg usbdevice44 = 1'd0;
+reg usbdevice45 = 1'd0;
+reg usbdevice46 = 1'd0;
+reg usbdevice47 = 1'd0;
+reg usbdevice_o_in_commit = 1'd0;
+reg usbdevice_o_in_rollback = 1'd0;
+reg usbdevice_in_tx_pkt_start = 1'd0;
+reg [3:0] usbdevice_in_tx_pid = 4'd0;
+reg usbdevice_out_tx_pkt_start = 1'd0;
+reg [3:0] usbdevice_out_tx_pid = 4'd0;
+reg usbdevice_tx_pkt_start = 1'd0;
+wire usbdevice_tx_pkt_end;
+reg [3:0] usbdevice_tx_pid = 4'd0;
+reg usbdevice_tx_data_avail = 1'd0;
+wire usbdevice_tx_data_get;
+reg [7:0] usbdevice_tx_data = 8'd0;
+wire usbdevice_usb_tx_en;
+wire usbdevice_usb_p_tx;
+wire usbdevice_usb_n_tx;
+reg usbdevice_usb_p_rx = 1'd0;
+reg usbdevice_usb_n_rx = 1'd0;
+wire usbdevice_usb_p_rx_io;
+wire usbdevice_usb_n_rx_io;
+wire usbdevice_usbfsrx_usbp;
+wire usbdevice_usbfsrx_usbn;
+wire [1:0] usbdevice_usbfsrx_dpair;
+reg usbdevice_usbfsrx_line_state_dt = 1'd0;
+reg usbdevice_usbfsrx_line_state_dj0 = 1'd0;
+reg usbdevice_usbfsrx_line_state_dk0 = 1'd0;
+reg usbdevice_usbfsrx_line_state_se00 = 1'd0;
+reg usbdevice_usbfsrx_line_state_se10 = 1'd0;
+reg [1:0] usbdevice_usbfsrx_line_state_phase = 2'd0;
+reg usbdevice_usbfsrx_line_state_valid = 1'd0;
+reg usbdevice_usbfsrx_line_state_dj1 = 1'd0;
+reg usbdevice_usbfsrx_line_state_dk1 = 1'd0;
+reg usbdevice_usbfsrx_line_state_se01 = 1'd0;
+reg usbdevice_usbfsrx_line_state_se11 = 1'd0;
+reg usbdevice_usbfsrx_nrzi_o_valid0 = 1'd0;
+reg usbdevice_usbfsrx_nrzi_o_data0 = 1'd0;
+reg usbdevice_usbfsrx_nrzi_o_valid1 = 1'd0;
+reg usbdevice_usbfsrx_nrzi_o_data1 = 1'd0;
+reg usbdevice_usbfsrx_nrzi_o_se0 = 1'd0;
+reg usbdevice_usbfsrx_bitstuff_drop_bit = 1'd0;
+reg usbdevice_usbfsrx_bitstuff_o_valid = 1'd0;
+reg usbdevice_usbfsrx_bitstuff_o_data = 1'd0;
+reg usbdevice_usbfsrx_bitstuff_o_se0 = 1'd0;
+reg usbdevice_usbfsrx_bitstuff_o_bitstuff_error = 1'd0;
+reg usbdevice_usbfsrx_valid = 1'd0;
+reg usbdevice_usbfsrx_data = 1'd0;
+reg usbdevice_usbfsrx_se0 = 1'd0;
+reg usbdevice_usbfsrx_bitstuff_error = 1'd0;
+reg usbdevice_usbfsrx_pkt_start = 1'd0;
+reg usbdevice_usbfsrx_pkt_active0 = 1'd0;
+reg usbdevice_usbfsrx_pkt_end0 = 1'd0;
+reg usbdevice_usbfsrx_o_pkt_start0 = 1'd0;
+reg usbdevice_usbfsrx_o_pkt_active = 1'd0;
+reg usbdevice_usbfsrx_o_pkt_end0 = 1'd0;
+reg usbdevice_usbfsrx_pkt_active1 = 1'd0;
+reg usbdevice_usbfsrx_pkt_end1 = 1'd0;
+reg [8:0] usbdevice_usbfsrx_pid_shifter_shift_reg = 9'd0;
+wire usbdevice_usbfsrx_pid_shifter_o_full;
+wire [7:0] usbdevice_usbfsrx_pid_shifter_o_output;
+reg usbdevice_usbfsrx_pid_shifter_o_put = 1'd0;
+reg [16:0] usbdevice_usbfsrx_tok_shifter_shift_reg = 17'd0;
+wire usbdevice_usbfsrx_tok_shifter_o_full;
+wire [15:0] usbdevice_usbfsrx_tok_shifter_o_output;
+reg usbdevice_usbfsrx_tok_shifter_o_put = 1'd0;
+reg [4:0] usbdevice_usbfsrx_tok_crc5_crc = 5'd0;
+wire usbdevice_usbfsrx_tok_crc5_crc_good;
+wire usbdevice_usbfsrx_tok_crc5_crc_invert;
+reg usbdevice_usbfsrx_tok_crc5_o_crc_good = 1'd0;
+wire usbdevice_usbfsrx_data_put;
+reg [8:0] usbdevice_usbfsrx_data_shifter_shift_reg = 9'd0;
+wire usbdevice_usbfsrx_data_shifter_o_full;
+wire [7:0] usbdevice_usbfsrx_data_shifter_o_output;
+reg usbdevice_usbfsrx_data_shifter_o_put = 1'd0;
+reg [15:0] usbdevice_usbfsrx_data_crc16_crc = 16'd0;
+wire usbdevice_usbfsrx_data_crc16_crc_good;
+wire usbdevice_usbfsrx_data_crc16_crc_invert;
+reg usbdevice_usbfsrx_data_crc16_o_crc_good = 1'd0;
+reg usbdevice_usbfsrx_pkt_bitstuff_good = 1'd0;
+reg usbdevice_usbfsrx_o_pkt_data_put = 1'd0;
+reg usbdevice_usbfsrx_crc16_good = 1'd0;
+reg usbdevice_usbfsrx_o_pkt_start1 = 1'd0;
+reg [3:0] usbdevice_usbfsrx_o_pkt_pid = 4'd0;
+reg [10:0] usbdevice_usbfsrx_o_pkt_token_payload = 11'd0;
+reg [7:0] usbdevice_usbfsrx_o_pkt_data = 8'd0;
+reg usbdevice_usbfsrx_o_pkt_good = 1'd0;
+reg usbdevice_usbfsrx_o_pkt_end1 = 1'd0;
+wire [6:0] usbdevice_rx_addr;
+wire [3:0] usbdevice_rx_endp;
+wire usbdevice_usbfstx_bitstuff_stall;
+reg usbdevice_usbfstx_pkt_active = 1'd0;
+reg usbdevice_usbfstx_shift_sync = 1'd0;
+reg usbdevice_usbfstx_shift_pid = 1'd0;
+reg usbdevice_usbfstx_shift_eop = 1'd0;
+reg usbdevice_usbfstx_load_data = 1'd0;
+reg usbdevice_usbfstx_shift_data = 1'd0;
+reg usbdevice_usbfstx_load_crc16 = 1'd0;
+reg usbdevice_usbfstx_shift_crc16 = 1'd0;
+reg usbdevice_usbfstx_pkt_end = 1'd0;
+reg [8:0] usbdevice_usbfstx_sync_shifter_shifter = 9'd0;
+wire usbdevice_usbfstx_sync_shifter_o_data;
+wire usbdevice_usbfstx_sync_shifter_o_empty;
+reg usbdevice_usbfstx_sync_shifter_not_empty = 1'd0;
+reg [8:0] usbdevice_usbfstx_pid_shifter_shifter = 9'd0;
+wire usbdevice_usbfstx_pid_shifter_o_data;
+wire usbdevice_usbfstx_pid_shifter_o_empty;
+reg usbdevice_usbfstx_pid_shifter_not_empty = 1'd0;
+reg [8:0] usbdevice_usbfstx_data_shifter_shifter = 9'd0;
+wire usbdevice_usbfstx_data_shifter_o_data;
+wire usbdevice_usbfstx_data_shifter_o_empty;
+reg usbdevice_usbfstx_data_shifter_not_empty = 1'd0;
+reg [15:0] usbdevice_usbfstx_crc = 16'd0;
+wire usbdevice_usbfstx_crc_invert;
+reg [15:0] usbdevice_usbfstx_o_crc = 16'd0;
+reg [16:0] usbdevice_usbfstx_crc16_shifter_shifter = 17'd0;
+wire usbdevice_usbfstx_crc16_shifter_o_data;
+wire usbdevice_usbfstx_crc16_shifter_o_empty;
+reg usbdevice_usbfstx_crc16_shifter_not_empty = 1'd0;
+reg usbdevice_usbfstx_pid_is_data = 1'd0;
+reg usbdevice_usbfstx_mux_stuff_oe = 1'd0;
+reg usbdevice_usbfstx_mux_stuff_data = 1'd0;
+reg usbdevice_usbfstx_mux_stuff_se0 = 1'd0;
+reg usbdevice_usbfstx_mux_stuff_bit_strobe = 1'd0;
+reg usbdevice_usbfstx_bitstuffer_stuff_bit = 1'd0;
+wire usbdevice_usbfstx_bitstuffer_o_stall;
+reg usbdevice_usbfstx_bitstuffer_o_data = 1'd0;
+reg usbdevice_usbfstx_bitstuffer_o_se0 = 1'd0;
+reg usbdevice_usbfstx_bitstuffer_o_oe = 1'd0;
+reg usbdevice_usbfstx_nrzi_usbp = 1'd0;
+reg usbdevice_usbfstx_nrzi_usbn = 1'd0;
+reg usbdevice_usbfstx_nrzi_oe = 1'd0;
+reg usbdevice_usbfstx_nrzi_o_usbp = 1'd0;
+reg usbdevice_usbfstx_nrzi_o_usbn = 1'd0;
+reg usbdevice_usbfstx_nrzi_o_oe = 1'd0;
+reg usbdevice_usbfstx_o_data_get = 1'd0;
+reg usbdevice_usbfstx_o_pkt_end = 1'd0;
+reg usbdevice_usbfstx_o_usbp = 1'd0;
+reg usbdevice_usbfstx_o_usbn = 1'd0;
+reg usbdevice_usbfstx_o_oe = 1'd0;
+reg [3:0] usbdevice_current_token = 4'd0;
+reg [3:0] usbdevice_current_endp = 4'd0;
+wire usbdevice_valid_request_token_pre;
+reg usbdevice_valid_request_token = 1'd0;
+wire usbdevice_valid_out_token;
+wire usbdevice_valid_data_packet;
+wire usbdevice_valid_in_token;
+wire usbdevice_valid_ack_packet;
+reg [7:0] io_input = 8'd0;
+wire [7:0] io_output;
+wire [7:0] io_status;
+reg [7:0] io_storage_full = 8'd0;
+wire [7:0] io_storage;
+reg io_re = 1'd0;
+wire scope_clk;
+wire scope_rst;
+wire mux_valid;
+reg mux_ready = 1'd0;
+reg mux_first = 1'd0;
+reg mux_last = 1'd0;
+wire [1:0] mux_payload_data;
+reg mux_payload_hit = 1'd0;
+reg mux_source_valid = 1'd0;
+wire mux_source_ready;
+reg mux_source_first = 1'd0;
+reg mux_source_last = 1'd0;
+reg [1:0] mux_source_payload_data = 2'd0;
+reg mux_source_payload_hit = 1'd0;
+reg mux_value_storage_full = 1'd0;
+wire mux_value_storage;
+reg mux_value_re = 1'd0;
+wire mux_value;
+wire trigger_sink_sink_valid;
+wire trigger_sink_sink_ready;
+wire trigger_sink_sink_first;
+wire trigger_sink_sink_last;
+wire [1:0] trigger_sink_sink_payload_data;
+wire trigger_sink_sink_payload_hit;
+wire trigger_source_source_valid;
+wire trigger_source_source_ready;
+wire trigger_source_source_first;
+wire trigger_source_source_last;
+wire [1:0] trigger_source_source_payload_data;
+reg trigger_source_source_payload_hit = 1'd0;
+reg trigger_enable_storage_full = 1'd0;
+wire trigger_enable_storage;
+reg trigger_enable_re = 1'd0;
+wire trigger_done_status;
+wire trigger_mem_write_re;
+wire trigger_mem_write_r;
+reg trigger_mem_write_w = 1'd0;
+reg [1:0] trigger_mem_mask_storage_full = 2'd0;
+wire [1:0] trigger_mem_mask_storage;
+reg trigger_mem_mask_re = 1'd0;
+reg [1:0] trigger_mem_value_storage_full = 2'd0;
+wire [1:0] trigger_mem_value_storage;
+reg trigger_mem_value_re = 1'd0;
+wire trigger_mem_full_status;
+wire trigger_enable;
+reg trigger_enable_d = 1'd0;
+wire trigger_done0;
+wire trigger_mem_sink_valid;
+wire trigger_mem_sink_ready;
+reg trigger_mem_sink_first = 1'd0;
+reg trigger_mem_sink_last = 1'd0;
+wire [1:0] trigger_mem_sink_payload_mask;
+wire [1:0] trigger_mem_sink_payload_value;
+wire trigger_mem_source_valid;
+wire trigger_mem_source_ready;
+wire trigger_mem_source_first;
+wire trigger_mem_source_last;
+wire [1:0] trigger_mem_source_payload_mask;
+wire [1:0] trigger_mem_source_payload_value;
+wire trigger_mem_asyncfifo_we;
+wire trigger_mem_asyncfifo_writable;
+wire trigger_mem_asyncfifo_re;
+wire trigger_mem_asyncfifo_readable;
+wire [5:0] trigger_mem_asyncfifo_din;
+wire [5:0] trigger_mem_asyncfifo_dout;
+wire trigger_mem_graycounter0_ce;
+reg [4:0] trigger_mem_graycounter0_q = 5'd0;
+wire [4:0] trigger_mem_graycounter0_q_next;
+reg [4:0] trigger_mem_graycounter0_q_binary = 5'd0;
+reg [4:0] trigger_mem_graycounter0_q_next_binary = 5'd0;
+wire trigger_mem_graycounter1_ce;
+reg [4:0] trigger_mem_graycounter1_q = 5'd0;
+wire [4:0] trigger_mem_graycounter1_q_next;
+reg [4:0] trigger_mem_graycounter1_q_binary = 5'd0;
+reg [4:0] trigger_mem_graycounter1_q_next_binary = 5'd0;
+wire [4:0] trigger_mem_produce_rdomain;
+wire [4:0] trigger_mem_consume_wdomain;
+wire [3:0] trigger_mem_wrport_adr;
+wire [5:0] trigger_mem_wrport_dat_r;
+wire trigger_mem_wrport_we;
+wire [5:0] trigger_mem_wrport_dat_w;
+wire [3:0] trigger_mem_rdport_adr;
+wire [5:0] trigger_mem_rdport_dat_r;
+wire [1:0] trigger_mem_fifo_in_payload_mask;
+wire [1:0] trigger_mem_fifo_in_payload_value;
+wire trigger_mem_fifo_in_first;
+wire trigger_mem_fifo_in_last;
+wire [1:0] trigger_mem_fifo_out_payload_mask;
+wire [1:0] trigger_mem_fifo_out_payload_value;
+wire trigger_mem_fifo_out_first;
+wire trigger_mem_fifo_out_last;
+wire trigger_hit;
+wire trigger_wait;
+wire trigger_done1;
+reg [4:0] trigger_count = 5'd16;
+wire subsampler_sink_valid;
+wire subsampler_sink_ready;
+wire subsampler_sink_first;
+wire subsampler_sink_last;
+wire [1:0] subsampler_sink_payload_data;
+wire subsampler_sink_payload_hit;
+wire subsampler_source_valid;
+wire subsampler_source_ready;
+wire subsampler_source_first;
+wire subsampler_source_last;
+wire [1:0] subsampler_source_payload_data;
+wire subsampler_source_payload_hit;
+reg [15:0] subsampler_value_storage_full = 16'd0;
+wire [15:0] subsampler_value_storage;
+reg subsampler_value_re = 1'd0;
+wire [15:0] subsampler_value;
+reg [15:0] subsampler_counter = 16'd0;
+wire subsampler_done;
+wire storage_sink_sink_valid;
+reg storage_sink_sink_ready = 1'd0;
+wire storage_sink_sink_first;
+wire storage_sink_sink_last;
+wire [1:0] storage_sink_sink_payload_data;
+wire storage_sink_sink_payload_hit;
+reg storage_enable_storage_full = 1'd0;
+wire storage_enable_storage;
+reg storage_enable_re = 1'd0;
+wire storage_done_status;
+reg [8:0] storage_length_storage_full = 9'd0;
+wire [8:0] storage_length_storage;
+reg storage_length_re = 1'd0;
+reg [8:0] storage_offset_storage_full = 9'd0;
+wire [8:0] storage_offset_storage;
+reg storage_offset_re = 1'd0;
+wire storage_mem_valid_status;
+wire storage_mem_ready_re;
+wire storage_mem_ready_r;
+reg storage_mem_ready_w = 1'd0;
+wire [1:0] storage_mem_data_status;
+wire storage_enable;
+reg storage_enable_d = 1'd0;
+wire [7:0] storage_length;
+wire [7:0] storage_offset;
+reg storage_done0 = 1'd0;
+reg storage_mem_sink_valid = 1'd0;
+wire storage_mem_sink_ready;
+reg storage_mem_sink_first = 1'd0;
+reg storage_mem_sink_last = 1'd0;
+reg [1:0] storage_mem_sink_payload_data = 2'd0;
+wire storage_mem_source_valid;
+reg storage_mem_source_ready = 1'd0;
+wire storage_mem_source_first;
+wire storage_mem_source_last;
+wire [1:0] storage_mem_source_payload_data;
+wire storage_mem_re;
+reg storage_mem_readable = 1'd0;
+wire storage_mem_syncfifo_we;
+wire storage_mem_syncfifo_writable;
+wire storage_mem_syncfifo_re;
+wire storage_mem_syncfifo_readable;
+wire [3:0] storage_mem_syncfifo_din;
+wire [3:0] storage_mem_syncfifo_dout;
+reg [8:0] storage_mem_level0 = 9'd0;
+reg storage_mem_replace = 1'd0;
+reg [7:0] storage_mem_produce = 8'd0;
+reg [7:0] storage_mem_consume = 8'd0;
+reg [7:0] storage_mem_wrport_adr = 8'd0;
+wire [3:0] storage_mem_wrport_dat_r;
+wire storage_mem_wrport_we;
+wire [3:0] storage_mem_wrport_dat_w;
+wire storage_mem_do_read;
+wire [7:0] storage_mem_rdport_adr;
+wire [3:0] storage_mem_rdport_dat_r;
+wire storage_mem_rdport_re;
+wire [8:0] storage_mem_level1;
+wire [1:0] storage_mem_fifo_in_payload_data;
+wire storage_mem_fifo_in_first;
+wire storage_mem_fifo_in_last;
+wire [1:0] storage_mem_fifo_out_payload_data;
+wire storage_mem_fifo_out_first;
+wire storage_mem_fifo_out_last;
+reg storage_cdc_sink_valid = 1'd0;
+wire storage_cdc_sink_ready;
+reg storage_cdc_sink_first = 1'd0;
+reg storage_cdc_sink_last = 1'd0;
+reg [1:0] storage_cdc_sink_payload_data = 2'd0;
+wire storage_cdc_source_valid;
+wire storage_cdc_source_ready;
+wire storage_cdc_source_first;
+wire storage_cdc_source_last;
+wire [1:0] storage_cdc_source_payload_data;
+wire storage_cdc_asyncfifo_we;
+wire storage_cdc_asyncfifo_writable;
+wire storage_cdc_asyncfifo_re;
+wire storage_cdc_asyncfifo_readable;
+wire [3:0] storage_cdc_asyncfifo_din;
+wire [3:0] storage_cdc_asyncfifo_dout;
+wire storage_cdc_graycounter0_ce;
+reg [2:0] storage_cdc_graycounter0_q = 3'd0;
+wire [2:0] storage_cdc_graycounter0_q_next;
+reg [2:0] storage_cdc_graycounter0_q_binary = 3'd0;
+reg [2:0] storage_cdc_graycounter0_q_next_binary = 3'd0;
+wire storage_cdc_graycounter1_ce;
+reg [2:0] storage_cdc_graycounter1_q = 3'd0;
+wire [2:0] storage_cdc_graycounter1_q_next;
+reg [2:0] storage_cdc_graycounter1_q_binary = 3'd0;
+reg [2:0] storage_cdc_graycounter1_q_next_binary = 3'd0;
+wire [2:0] storage_cdc_produce_rdomain;
+wire [2:0] storage_cdc_consume_wdomain;
+wire [1:0] storage_cdc_wrport_adr;
+wire [3:0] storage_cdc_wrport_dat_r;
+wire storage_cdc_wrport_we;
+wire [3:0] storage_cdc_wrport_dat_w;
+wire [1:0] storage_cdc_rdport_adr;
+wire [3:0] storage_cdc_rdport_dat_r;
+wire [1:0] storage_cdc_fifo_in_payload_data;
+wire storage_cdc_fifo_in_first;
+wire storage_cdc_fifo_in_last;
+wire [1:0] storage_cdc_fifo_out_payload_data;
+wire storage_cdc_fifo_out_first;
+wire storage_cdc_fifo_out_last;
+reg storage_wait = 1'd0;
+wire storage_done1;
+reg [8:0] storage_count = 9'd256;
+reg [2:0] uartwishbonebridge_state = 3'd0;
+reg [2:0] uartwishbonebridge_next_state = 3'd0;
+reg [2:0] rxclockdatarecovery_state = 3'd0;
+reg [2:0] rxclockdatarecovery_next_state = 3'd0;
+reg rxnrzidecoder_state = 1'd0;
+reg rxnrzidecoder_next_state = 1'd0;
+reg [2:0] rxbitstuffremover_state = 3'd0;
+reg [2:0] rxbitstuffremover_next_state = 3'd0;
+reg [2:0] rxpacketdecode_state = 3'd0;
+reg [2:0] rxpacketdecode_next_state = 3'd0;
+reg [2:0] fsm_state = 3'd0;
+reg [2:0] fsm_next_state = 3'd0;
+reg [2:0] txbitstuffer_state = 3'd0;
+reg [2:0] txbitstuffer_next_state = 3'd0;
+reg [2:0] txnrziencoder_state = 3'd0;
+reg [2:0] txnrziencoder_next_state = 3'd0;
+reg [2:0] fsm0_state = 3'd0;
+reg [2:0] fsm0_next_state = 3'd0;
+reg [2:0] fsm1_state = 3'd0;
+reg [2:0] fsm1_next_state = 3'd0;
+reg [1:0] litescopeanalyzer_state = 2'd0;
+reg [1:0] litescopeanalyzer_next_state = 2'd0;
+wire [29:0] shared_adr;
+wire [31:0] shared_dat_w;
+reg [31:0] shared_dat_r = 32'd0;
+wire [3:0] shared_sel;
+wire shared_cyc;
+wire shared_stb;
+reg shared_ack = 1'd0;
+wire shared_we;
+wire [2:0] shared_cti;
+wire [1:0] shared_bte;
+wire shared_err;
+wire request;
+wire grant;
+reg [1:0] slave_sel = 2'd0;
+reg [1:0] slave_sel_r = 2'd0;
+reg error = 1'd0;
+wire wait_1;
+wire done;
+reg [16:0] count = 17'd65536;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [7:0] interface0_bank_bus_dat_w;
+reg [7:0] interface0_bank_bus_dat_r = 8'd0;
+wire csrbank0_mux_value0_re;
+wire csrbank0_mux_value0_r;
+wire csrbank0_mux_value0_w;
+wire csrbank0_trigger_enable0_re;
+wire csrbank0_trigger_enable0_r;
+wire csrbank0_trigger_enable0_w;
+wire csrbank0_trigger_done_re;
+wire csrbank0_trigger_done_r;
+wire csrbank0_trigger_done_w;
+wire csrbank0_trigger_mem_mask0_re;
+wire [1:0] csrbank0_trigger_mem_mask0_r;
+wire [1:0] csrbank0_trigger_mem_mask0_w;
+wire csrbank0_trigger_mem_value0_re;
+wire [1:0] csrbank0_trigger_mem_value0_r;
+wire [1:0] csrbank0_trigger_mem_value0_w;
+wire csrbank0_trigger_mem_full_re;
+wire csrbank0_trigger_mem_full_r;
+wire csrbank0_trigger_mem_full_w;
+wire csrbank0_subsampler_value1_re;
+wire [7:0] csrbank0_subsampler_value1_r;
+wire [7:0] csrbank0_subsampler_value1_w;
+wire csrbank0_subsampler_value0_re;
+wire [7:0] csrbank0_subsampler_value0_r;
+wire [7:0] csrbank0_subsampler_value0_w;
+wire csrbank0_storage_enable0_re;
+wire csrbank0_storage_enable0_r;
+wire csrbank0_storage_enable0_w;
+wire csrbank0_storage_done_re;
+wire csrbank0_storage_done_r;
+wire csrbank0_storage_done_w;
+wire csrbank0_storage_length1_re;
+wire csrbank0_storage_length1_r;
+wire csrbank0_storage_length1_w;
+wire csrbank0_storage_length0_re;
+wire [7:0] csrbank0_storage_length0_r;
+wire [7:0] csrbank0_storage_length0_w;
+wire csrbank0_storage_offset1_re;
+wire csrbank0_storage_offset1_r;
+wire csrbank0_storage_offset1_w;
+wire csrbank0_storage_offset0_re;
+wire [7:0] csrbank0_storage_offset0_r;
+wire [7:0] csrbank0_storage_offset0_w;
+wire csrbank0_storage_mem_valid_re;
+wire csrbank0_storage_mem_valid_r;
+wire csrbank0_storage_mem_valid_w;
+wire csrbank0_storage_mem_data_re;
+wire [1:0] csrbank0_storage_mem_data_r;
+wire [1:0] csrbank0_storage_mem_data_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [7:0] interface1_bank_bus_dat_w;
+reg [7:0] interface1_bank_bus_dat_r = 8'd0;
+wire csrbank1_scratch3_re;
+wire [7:0] csrbank1_scratch3_r;
+wire [7:0] csrbank1_scratch3_w;
+wire csrbank1_scratch2_re;
+wire [7:0] csrbank1_scratch2_r;
+wire [7:0] csrbank1_scratch2_w;
+wire csrbank1_scratch1_re;
+wire [7:0] csrbank1_scratch1_r;
+wire [7:0] csrbank1_scratch1_w;
+wire csrbank1_scratch0_re;
+wire [7:0] csrbank1_scratch0_r;
+wire [7:0] csrbank1_scratch0_w;
+wire csrbank1_bus_errors3_re;
+wire [7:0] csrbank1_bus_errors3_r;
+wire [7:0] csrbank1_bus_errors3_w;
+wire csrbank1_bus_errors2_re;
+wire [7:0] csrbank1_bus_errors2_r;
+wire [7:0] csrbank1_bus_errors2_w;
+wire csrbank1_bus_errors1_re;
+wire [7:0] csrbank1_bus_errors1_r;
+wire [7:0] csrbank1_bus_errors1_w;
+wire csrbank1_bus_errors0_re;
+wire [7:0] csrbank1_bus_errors0_r;
+wire [7:0] csrbank1_bus_errors0_w;
+wire csrbank1_sel;
+wire [13:0] sram_bus_adr;
+wire sram_bus_we;
+wire [7:0] sram_bus_dat_w;
+reg [7:0] sram_bus_dat_r = 8'd0;
+wire [3:0] adr;
+wire [7:0] dat_r;
+wire sel;
+reg sel_r = 1'd0;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [7:0] interface2_bank_bus_dat_w;
+reg [7:0] interface2_bank_bus_dat_r = 8'd0;
+wire csrbank2_git_commit19_re;
+wire [7:0] csrbank2_git_commit19_r;
+wire [7:0] csrbank2_git_commit19_w;
+wire csrbank2_git_commit18_re;
+wire [7:0] csrbank2_git_commit18_r;
+wire [7:0] csrbank2_git_commit18_w;
+wire csrbank2_git_commit17_re;
+wire [7:0] csrbank2_git_commit17_r;
+wire [7:0] csrbank2_git_commit17_w;
+wire csrbank2_git_commit16_re;
+wire [7:0] csrbank2_git_commit16_r;
+wire [7:0] csrbank2_git_commit16_w;
+wire csrbank2_git_commit15_re;
+wire [7:0] csrbank2_git_commit15_r;
+wire [7:0] csrbank2_git_commit15_w;
+wire csrbank2_git_commit14_re;
+wire [7:0] csrbank2_git_commit14_r;
+wire [7:0] csrbank2_git_commit14_w;
+wire csrbank2_git_commit13_re;
+wire [7:0] csrbank2_git_commit13_r;
+wire [7:0] csrbank2_git_commit13_w;
+wire csrbank2_git_commit12_re;
+wire [7:0] csrbank2_git_commit12_r;
+wire [7:0] csrbank2_git_commit12_w;
+wire csrbank2_git_commit11_re;
+wire [7:0] csrbank2_git_commit11_r;
+wire [7:0] csrbank2_git_commit11_w;
+wire csrbank2_git_commit10_re;
+wire [7:0] csrbank2_git_commit10_r;
+wire [7:0] csrbank2_git_commit10_w;
+wire csrbank2_git_commit9_re;
+wire [7:0] csrbank2_git_commit9_r;
+wire [7:0] csrbank2_git_commit9_w;
+wire csrbank2_git_commit8_re;
+wire [7:0] csrbank2_git_commit8_r;
+wire [7:0] csrbank2_git_commit8_w;
+wire csrbank2_git_commit7_re;
+wire [7:0] csrbank2_git_commit7_r;
+wire [7:0] csrbank2_git_commit7_w;
+wire csrbank2_git_commit6_re;
+wire [7:0] csrbank2_git_commit6_r;
+wire [7:0] csrbank2_git_commit6_w;
+wire csrbank2_git_commit5_re;
+wire [7:0] csrbank2_git_commit5_r;
+wire [7:0] csrbank2_git_commit5_w;
+wire csrbank2_git_commit4_re;
+wire [7:0] csrbank2_git_commit4_r;
+wire [7:0] csrbank2_git_commit4_w;
+wire csrbank2_git_commit3_re;
+wire [7:0] csrbank2_git_commit3_r;
+wire [7:0] csrbank2_git_commit3_w;
+wire csrbank2_git_commit2_re;
+wire [7:0] csrbank2_git_commit2_r;
+wire [7:0] csrbank2_git_commit2_w;
+wire csrbank2_git_commit1_re;
+wire [7:0] csrbank2_git_commit1_r;
+wire [7:0] csrbank2_git_commit1_w;
+wire csrbank2_git_commit0_re;
+wire [7:0] csrbank2_git_commit0_r;
+wire [7:0] csrbank2_git_commit0_w;
+wire csrbank2_platform_platform7_re;
+wire [7:0] csrbank2_platform_platform7_r;
+wire [7:0] csrbank2_platform_platform7_w;
+wire csrbank2_platform_platform6_re;
+wire [7:0] csrbank2_platform_platform6_r;
+wire [7:0] csrbank2_platform_platform6_w;
+wire csrbank2_platform_platform5_re;
+wire [7:0] csrbank2_platform_platform5_r;
+wire [7:0] csrbank2_platform_platform5_w;
+wire csrbank2_platform_platform4_re;
+wire [7:0] csrbank2_platform_platform4_r;
+wire [7:0] csrbank2_platform_platform4_w;
+wire csrbank2_platform_platform3_re;
+wire [7:0] csrbank2_platform_platform3_r;
+wire [7:0] csrbank2_platform_platform3_w;
+wire csrbank2_platform_platform2_re;
+wire [7:0] csrbank2_platform_platform2_r;
+wire [7:0] csrbank2_platform_platform2_w;
+wire csrbank2_platform_platform1_re;
+wire [7:0] csrbank2_platform_platform1_r;
+wire [7:0] csrbank2_platform_platform1_w;
+wire csrbank2_platform_platform0_re;
+wire [7:0] csrbank2_platform_platform0_r;
+wire [7:0] csrbank2_platform_platform0_w;
+wire csrbank2_platform_target7_re;
+wire [7:0] csrbank2_platform_target7_r;
+wire [7:0] csrbank2_platform_target7_w;
+wire csrbank2_platform_target6_re;
+wire [7:0] csrbank2_platform_target6_r;
+wire [7:0] csrbank2_platform_target6_w;
+wire csrbank2_platform_target5_re;
+wire [7:0] csrbank2_platform_target5_r;
+wire [7:0] csrbank2_platform_target5_w;
+wire csrbank2_platform_target4_re;
+wire [7:0] csrbank2_platform_target4_r;
+wire [7:0] csrbank2_platform_target4_w;
+wire csrbank2_platform_target3_re;
+wire [7:0] csrbank2_platform_target3_r;
+wire [7:0] csrbank2_platform_target3_w;
+wire csrbank2_platform_target2_re;
+wire [7:0] csrbank2_platform_target2_r;
+wire [7:0] csrbank2_platform_target2_w;
+wire csrbank2_platform_target1_re;
+wire [7:0] csrbank2_platform_target1_r;
+wire [7:0] csrbank2_platform_target1_w;
+wire csrbank2_platform_target0_re;
+wire [7:0] csrbank2_platform_target0_r;
+wire [7:0] csrbank2_platform_target0_w;
+wire csrbank2_sel;
+wire [13:0] interface3_bank_bus_adr;
+wire interface3_bank_bus_we;
+wire [7:0] interface3_bank_bus_dat_w;
+reg [7:0] interface3_bank_bus_dat_r = 8'd0;
+wire csrbank3_in_re;
+wire [7:0] csrbank3_in_r;
+wire [7:0] csrbank3_in_w;
+wire csrbank3_out0_re;
+wire [7:0] csrbank3_out0_r;
+wire [7:0] csrbank3_out0_w;
+wire csrbank3_sel;
+wire [13:0] interface4_bank_bus_adr;
+wire interface4_bank_bus_we;
+wire [7:0] interface4_bank_bus_dat_w;
+reg [7:0] interface4_bank_bus_dat_r = 8'd0;
+wire csrbank4_bitbang0_re;
+wire [3:0] csrbank4_bitbang0_r;
+wire [3:0] csrbank4_bitbang0_w;
+wire csrbank4_miso_re;
+wire csrbank4_miso_r;
+wire csrbank4_miso_w;
+wire csrbank4_bitbang_en0_re;
+wire csrbank4_bitbang_en0_r;
+wire csrbank4_bitbang_en0_w;
+wire csrbank4_sel;
+wire [13:0] interface5_bank_bus_adr;
+wire interface5_bank_bus_we;
+wire [7:0] interface5_bank_bus_dat_w;
+reg [7:0] interface5_bank_bus_dat_r = 8'd0;
+wire csrbank5_load3_re;
+wire [7:0] csrbank5_load3_r;
+wire [7:0] csrbank5_load3_w;
+wire csrbank5_load2_re;
+wire [7:0] csrbank5_load2_r;
+wire [7:0] csrbank5_load2_w;
+wire csrbank5_load1_re;
+wire [7:0] csrbank5_load1_r;
+wire [7:0] csrbank5_load1_w;
+wire csrbank5_load0_re;
+wire [7:0] csrbank5_load0_r;
+wire [7:0] csrbank5_load0_w;
+wire csrbank5_reload3_re;
+wire [7:0] csrbank5_reload3_r;
+wire [7:0] csrbank5_reload3_w;
+wire csrbank5_reload2_re;
+wire [7:0] csrbank5_reload2_r;
+wire [7:0] csrbank5_reload2_w;
+wire csrbank5_reload1_re;
+wire [7:0] csrbank5_reload1_r;
+wire [7:0] csrbank5_reload1_w;
+wire csrbank5_reload0_re;
+wire [7:0] csrbank5_reload0_r;
+wire [7:0] csrbank5_reload0_w;
+wire csrbank5_en0_re;
+wire csrbank5_en0_r;
+wire csrbank5_en0_w;
+wire csrbank5_value3_re;
+wire [7:0] csrbank5_value3_r;
+wire [7:0] csrbank5_value3_w;
+wire csrbank5_value2_re;
+wire [7:0] csrbank5_value2_r;
+wire [7:0] csrbank5_value2_w;
+wire csrbank5_value1_re;
+wire [7:0] csrbank5_value1_r;
+wire [7:0] csrbank5_value1_w;
+wire csrbank5_value0_re;
+wire [7:0] csrbank5_value0_r;
+wire [7:0] csrbank5_value0_w;
+wire csrbank5_ev_enable0_re;
+wire csrbank5_ev_enable0_r;
+wire csrbank5_ev_enable0_w;
+wire csrbank5_sel;
+wire [7:0] slice_proxy0;
+wire [7:0] slice_proxy1;
+reg t_array_muxed = 1'd0;
+reg basiclowerer_array_muxed = 1'd0;
+reg rhs_array_muxed = 1'd0;
+reg [29:0] array_muxed0 = 30'd0;
+reg [31:0] array_muxed1 = 32'd0;
+reg [3:0] array_muxed2 = 4'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg [2:0] array_muxed6 = 3'd0;
+reg [1:0] array_muxed7 = 2'd0;
+wire rst1;
+reg multiregimpl0_regs0 = 1'd0;
+reg multiregimpl0_regs1 = 1'd0;
+reg multiregimpl1_regs0 = 1'd0;
+reg multiregimpl1_regs1 = 1'd0;
+reg multiregimpl1_regs2 = 1'd0;
+reg multiregimpl2_regs0 = 1'd0;
+reg multiregimpl2_regs1 = 1'd0;
+reg multiregimpl2_regs2 = 1'd0;
+reg [7:0] multiregimpl3_regs0 = 8'd0;
+reg [7:0] multiregimpl3_regs1 = 8'd0;
+reg multiregimpl4_regs0 = 1'd0;
+reg multiregimpl4_regs1 = 1'd0;
+reg multiregimpl5_regs0 = 1'd0;
+reg multiregimpl5_regs1 = 1'd0;
+reg multiregimpl6_regs0 = 1'd0;
+reg multiregimpl6_regs1 = 1'd0;
+reg [4:0] multiregimpl7_regs0 = 5'd0;
+reg [4:0] multiregimpl7_regs1 = 5'd0;
+reg [4:0] multiregimpl8_regs0 = 5'd0;
+reg [4:0] multiregimpl8_regs1 = 5'd0;
+reg [15:0] multiregimpl9_regs0 = 16'd0;
+reg [15:0] multiregimpl9_regs1 = 16'd0;
+reg multiregimpl10_regs0 = 1'd0;
+reg multiregimpl10_regs1 = 1'd0;
+reg [8:0] multiregimpl11_regs0 = 9'd0;
+reg [8:0] multiregimpl11_regs1 = 9'd0;
+reg [8:0] multiregimpl12_regs0 = 9'd0;
+reg [8:0] multiregimpl12_regs1 = 9'd0;
+reg multiregimpl13_regs0 = 1'd0;
+reg multiregimpl13_regs1 = 1'd0;
+reg [2:0] multiregimpl14_regs0 = 3'd0;
+reg [2:0] multiregimpl14_regs1 = 3'd0;
+reg [2:0] multiregimpl15_regs0 = 3'd0;
+reg [2:0] multiregimpl15_regs1 = 3'd0;
+
+assign user_led0 = io_output[0];
+assign usb_pullup = io_output[1];
+assign usbtestsoc_usbtestsoc_bus_error = error;
+assign usbtestsoc_usbtestsoc_reset = usbtestsoc_usbtestsoc_reset_reset_re;
+assign usbtestsoc_usbtestsoc_bus_errors_status = usbtestsoc_usbtestsoc_bus_errors;
+assign usbtestsoc_usbtestsoc_zero_trigger = (usbtestsoc_usbtestsoc_value != 1'd0);
+assign usbtestsoc_usbtestsoc_eventmanager_status_w = usbtestsoc_usbtestsoc_zero_status;
+always @(*) begin
+	usbtestsoc_usbtestsoc_zero_clear <= 1'd0;
+	if ((usbtestsoc_usbtestsoc_eventmanager_pending_re & usbtestsoc_usbtestsoc_eventmanager_pending_r)) begin
+		usbtestsoc_usbtestsoc_zero_clear <= 1'd1;
+	end
+end
+assign usbtestsoc_usbtestsoc_eventmanager_pending_w = usbtestsoc_usbtestsoc_zero_pending;
+assign usbtestsoc_usbtestsoc_irq = (usbtestsoc_usbtestsoc_eventmanager_pending_w & usbtestsoc_usbtestsoc_eventmanager_storage);
+assign usbtestsoc_usbtestsoc_zero_status = usbtestsoc_usbtestsoc_zero_trigger;
+assign sys_clk = clk16;
+assign por_clk = sys_clk;
+assign sys_rst = (usbtestsoc_crg_reset_delay != 1'd0);
+assign usbtestsoc_status = 160'd1256218714774539849041605386092237821690702622496;
+assign usbtestsoc_platform_status = 63'd8388357248643000161;
+assign usbtestsoc_target_status = 63'd8463216376817087488;
+assign spiflash_wp = 1'd1;
+assign spiflash_hold = 1'd1;
+assign usbtestsoc_spiflash_bus_dat_r = usbtestsoc_spiflash_sr;
+always @(*) begin
+	usbtestsoc_spiflash_miso_status <= 1'd0;
+	spiflash_mosi <= 1'd0;
+	spiflash_cs_n <= 1'd0;
+	spiflash_clk <= 1'd0;
+	if (usbtestsoc_spiflash_bitbang_en_storage) begin
+		spiflash_clk <= usbtestsoc_spiflash_bitbang_storage[1];
+		spiflash_cs_n <= usbtestsoc_spiflash_bitbang_storage[2];
+		if (usbtestsoc_spiflash_bitbang_storage[1]) begin
+			usbtestsoc_spiflash_miso_status <= spiflash_miso;
+		end
+		spiflash_mosi <= usbtestsoc_spiflash_bitbang_storage[0];
+	end else begin
+		spiflash_clk <= usbtestsoc_spiflash_clk1;
+		spiflash_cs_n <= usbtestsoc_spiflash_cs_n1;
+		spiflash_mosi <= usbtestsoc_spiflash_sr[31];
+	end
+end
+assign uartwishbonebridge_reset = uartwishbonebridge_done;
+assign uartwishbonebridge_source_ready = 1'd1;
+assign uartwishbonebridge_wishbone_adr = (uartwishbonebridge_address + uartwishbonebridge_word_counter);
+assign uartwishbonebridge_wishbone_dat_w = uartwishbonebridge_data;
+assign uartwishbonebridge_wishbone_sel = 4'd15;
+always @(*) begin
+	uartwishbonebridge_sink_payload_data <= 8'd0;
+	case (uartwishbonebridge_byte_counter)
+		1'd0: begin
+			uartwishbonebridge_sink_payload_data <= uartwishbonebridge_data[31:24];
+		end
+		1'd1: begin
+			uartwishbonebridge_sink_payload_data <= uartwishbonebridge_data[23:16];
+		end
+		2'd2: begin
+			uartwishbonebridge_sink_payload_data <= uartwishbonebridge_data[15:8];
+		end
+		default: begin
+			uartwishbonebridge_sink_payload_data <= uartwishbonebridge_data[7:0];
+		end
+	endcase
+end
+assign uartwishbonebridge_wait = (~uartwishbonebridge_is_ongoing);
+assign uartwishbonebridge_sink_last = ((uartwishbonebridge_byte_counter == 2'd3) & (uartwishbonebridge_word_counter == (uartwishbonebridge_length - 1'd1)));
+always @(*) begin
+	uartwishbonebridge_wishbone_we <= 1'd0;
+	uartwishbonebridge_byte_counter_reset <= 1'd0;
+	uartwishbonebridge_byte_counter_ce <= 1'd0;
+	uartwishbonebridge_word_counter_reset <= 1'd0;
+	uartwishbonebridge_sink_valid <= 1'd0;
+	uartwishbonebridge_word_counter_ce <= 1'd0;
+	uartwishbonebridge_cmd_ce <= 1'd0;
+	uartwishbonebridge_next_state <= 3'd0;
+	uartwishbonebridge_length_ce <= 1'd0;
+	uartwishbonebridge_address_ce <= 1'd0;
+	uartwishbonebridge_rx_data_ce <= 1'd0;
+	uartwishbonebridge_tx_data_ce <= 1'd0;
+	uartwishbonebridge_is_ongoing <= 1'd0;
+	uartwishbonebridge_wishbone_cyc <= 1'd0;
+	uartwishbonebridge_wishbone_stb <= 1'd0;
+	uartwishbonebridge_next_state <= uartwishbonebridge_state;
+	case (uartwishbonebridge_state)
+		1'd1: begin
+			if (uartwishbonebridge_source_valid) begin
+				uartwishbonebridge_length_ce <= 1'd1;
+				uartwishbonebridge_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (uartwishbonebridge_source_valid) begin
+				uartwishbonebridge_address_ce <= 1'd1;
+				uartwishbonebridge_byte_counter_ce <= 1'd1;
+				if ((uartwishbonebridge_byte_counter == 2'd3)) begin
+					if ((uartwishbonebridge_cmd == 1'd1)) begin
+						uartwishbonebridge_next_state <= 2'd3;
+					end else begin
+						if ((uartwishbonebridge_cmd == 2'd2)) begin
+							uartwishbonebridge_next_state <= 3'd5;
+						end
+					end
+					uartwishbonebridge_byte_counter_reset <= 1'd1;
+				end
+			end
+		end
+		2'd3: begin
+			if (uartwishbonebridge_source_valid) begin
+				uartwishbonebridge_rx_data_ce <= 1'd1;
+				uartwishbonebridge_byte_counter_ce <= 1'd1;
+				if ((uartwishbonebridge_byte_counter == 2'd3)) begin
+					uartwishbonebridge_next_state <= 3'd4;
+					uartwishbonebridge_byte_counter_reset <= 1'd1;
+				end
+			end
+		end
+		3'd4: begin
+			uartwishbonebridge_wishbone_stb <= 1'd1;
+			uartwishbonebridge_wishbone_we <= 1'd1;
+			uartwishbonebridge_wishbone_cyc <= 1'd1;
+			if (uartwishbonebridge_wishbone_ack) begin
+				uartwishbonebridge_word_counter_ce <= 1'd1;
+				if ((uartwishbonebridge_word_counter == (uartwishbonebridge_length - 1'd1))) begin
+					uartwishbonebridge_next_state <= 1'd0;
+				end else begin
+					uartwishbonebridge_next_state <= 2'd3;
+				end
+			end
+		end
+		3'd5: begin
+			uartwishbonebridge_wishbone_stb <= 1'd1;
+			uartwishbonebridge_wishbone_we <= 1'd0;
+			uartwishbonebridge_wishbone_cyc <= 1'd1;
+			if (uartwishbonebridge_wishbone_ack) begin
+				uartwishbonebridge_tx_data_ce <= 1'd1;
+				uartwishbonebridge_next_state <= 3'd6;
+			end
+		end
+		3'd6: begin
+			uartwishbonebridge_sink_valid <= 1'd1;
+			if (uartwishbonebridge_sink_ready) begin
+				uartwishbonebridge_byte_counter_ce <= 1'd1;
+				if ((uartwishbonebridge_byte_counter == 2'd3)) begin
+					uartwishbonebridge_word_counter_ce <= 1'd1;
+					if ((uartwishbonebridge_word_counter == (uartwishbonebridge_length - 1'd1))) begin
+						uartwishbonebridge_next_state <= 1'd0;
+					end else begin
+						uartwishbonebridge_next_state <= 3'd5;
+						uartwishbonebridge_byte_counter_reset <= 1'd1;
+					end
+				end
+			end
+		end
+		default: begin
+			if (uartwishbonebridge_source_valid) begin
+				uartwishbonebridge_cmd_ce <= 1'd1;
+				if (((uartwishbonebridge_source_payload_data == 1'd1) | (uartwishbonebridge_source_payload_data == 2'd2))) begin
+					uartwishbonebridge_next_state <= 1'd1;
+				end
+				uartwishbonebridge_byte_counter_reset <= 1'd1;
+				uartwishbonebridge_word_counter_reset <= 1'd1;
+			end
+			uartwishbonebridge_is_ongoing <= 1'd1;
+		end
+	endcase
+end
+assign uartwishbonebridge_done = (uartwishbonebridge_count == 1'd0);
+always @(*) begin
+	usbdevice_usb_p_rx <= 1'd0;
+	usbdevice_usb_n_rx <= 1'd0;
+	if (usbdevice_usb_tx_en) begin
+		usbdevice_usb_p_rx <= 1'd1;
+		usbdevice_usb_n_rx <= 1'd0;
+	end else begin
+		usbdevice_usb_p_rx <= usbdevice_usb_p_rx_io;
+		usbdevice_usb_n_rx <= usbdevice_usb_n_rx_io;
+	end
+end
+assign usbdevice_rx_addr = usbdevice_usbfsrx_o_pkt_token_payload[10:4];
+assign usbdevice_rx_endp = usbdevice_usbfsrx_o_pkt_token_payload[3:0];
+assign usbdevice_usb_tx_en = usbdevice_usbfstx_o_oe;
+assign usbdevice_usb_p_tx = usbdevice_usbfstx_o_usbp;
+assign usbdevice_usb_n_tx = usbdevice_usbfstx_o_usbn;
+assign usbdevice_tx_pkt_end = usbdevice_usbfstx_o_pkt_end;
+assign usbdevice_tx_data_get = usbdevice_usbfstx_o_data_get;
+assign usbdevice_valid_request_token_pre = (usbdevice_usbfsrx_o_pkt_good == 1'd1);
+assign usbdevice_valid_out_token = (usbdevice_valid_request_token & (usbdevice_current_token == 4'd13));
+assign usbdevice_valid_data_packet = (usbdevice_usbfsrx_o_pkt_good == 1'd1);
+assign usbdevice_valid_in_token = ((usbdevice_valid_request_token & usbdevice_current_token) == 4'd9);
+assign usbdevice_valid_ack_packet = (usbdevice_usbfsrx_o_pkt_good == 1'd1);
+assign usbdevice_usbfsrx_dpair = {usbdevice_usbfsrx_usbp, usbdevice_usbfsrx_usbn};
+always @(*) begin
+	rxclockdatarecovery_next_state <= 3'd0;
+	usbdevice_usbfsrx_line_state_dt <= 1'd0;
+	usbdevice_usbfsrx_line_state_dj0 <= 1'd0;
+	usbdevice_usbfsrx_line_state_dk0 <= 1'd0;
+	usbdevice_usbfsrx_line_state_se00 <= 1'd0;
+	usbdevice_usbfsrx_line_state_se10 <= 1'd0;
+	rxclockdatarecovery_next_state <= rxclockdatarecovery_state;
+	case (rxclockdatarecovery_state)
+		1'd1: begin
+			usbdevice_usbfsrx_line_state_dj0 <= 1'd1;
+			if ((usbdevice_usbfsrx_dpair != 2'd2)) begin
+				rxclockdatarecovery_next_state <= 1'd0;
+			end
+		end
+		2'd2: begin
+			usbdevice_usbfsrx_line_state_dk0 <= 1'd1;
+			if ((usbdevice_usbfsrx_dpair != 1'd1)) begin
+				rxclockdatarecovery_next_state <= 1'd0;
+			end
+		end
+		2'd3: begin
+			usbdevice_usbfsrx_line_state_se00 <= 1'd1;
+			if ((usbdevice_usbfsrx_dpair != 1'd0)) begin
+				rxclockdatarecovery_next_state <= 1'd0;
+			end
+		end
+		3'd4: begin
+			usbdevice_usbfsrx_line_state_se10 <= 1'd1;
+			if ((usbdevice_usbfsrx_dpair != 2'd3)) begin
+				rxclockdatarecovery_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			usbdevice_usbfsrx_line_state_dt <= 1'd1;
+			case (usbdevice_usbfsrx_dpair)
+				1'd0: begin
+					rxclockdatarecovery_next_state <= 2'd3;
+				end
+				1'd1: begin
+					rxclockdatarecovery_next_state <= 2'd2;
+				end
+				2'd2: begin
+					rxclockdatarecovery_next_state <= 1'd1;
+				end
+				2'd3: begin
+					rxclockdatarecovery_next_state <= 3'd4;
+				end
+			endcase
+		end
+	endcase
+end
+always @(*) begin
+	usbdevice_usbfsrx_nrzi_o_valid0 <= 1'd0;
+	usbdevice_usbfsrx_nrzi_o_data0 <= 1'd0;
+	rxnrzidecoder_next_state <= 1'd0;
+	rxnrzidecoder_next_state <= rxnrzidecoder_state;
+	case (rxnrzidecoder_state)
+		1'd1: begin
+			if (usbdevice_usbfsrx_line_state_valid) begin
+				usbdevice_usbfsrx_nrzi_o_valid0 <= 1'd1;
+				if (usbdevice_usbfsrx_line_state_dj1) begin
+					usbdevice_usbfsrx_nrzi_o_data0 <= 1'd0;
+					rxnrzidecoder_next_state <= 1'd0;
+				end else begin
+					if (usbdevice_usbfsrx_line_state_dk1) begin
+						usbdevice_usbfsrx_nrzi_o_data0 <= 1'd1;
+					end
+				end
+			end
+		end
+		default: begin
+			if (usbdevice_usbfsrx_line_state_valid) begin
+				usbdevice_usbfsrx_nrzi_o_valid0 <= 1'd1;
+				if (usbdevice_usbfsrx_line_state_dj1) begin
+					usbdevice_usbfsrx_nrzi_o_data0 <= 1'd1;
+				end else begin
+					if (usbdevice_usbfsrx_line_state_dk1) begin
+						usbdevice_usbfsrx_nrzi_o_data0 <= 1'd0;
+						rxnrzidecoder_next_state <= 1'd1;
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	usbdevice_usbfsrx_bitstuff_drop_bit <= 1'd0;
+	rxbitstuffremover_next_state <= 3'd0;
+	rxbitstuffremover_next_state <= rxbitstuffremover_state;
+	case (rxbitstuffremover_state)
+		1'd1: begin
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				if (usbdevice_usbfsrx_nrzi_o_data1) begin
+					rxbitstuffremover_next_state <= 2'd2;
+				end else begin
+					rxbitstuffremover_next_state <= 1'd0;
+				end
+			end
+		end
+		2'd2: begin
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				if (usbdevice_usbfsrx_nrzi_o_data1) begin
+					rxbitstuffremover_next_state <= 2'd3;
+				end else begin
+					rxbitstuffremover_next_state <= 1'd0;
+				end
+			end
+		end
+		2'd3: begin
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				if (usbdevice_usbfsrx_nrzi_o_data1) begin
+					rxbitstuffremover_next_state <= 3'd4;
+				end else begin
+					rxbitstuffremover_next_state <= 1'd0;
+				end
+			end
+		end
+		3'd4: begin
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				if (usbdevice_usbfsrx_nrzi_o_data1) begin
+					rxbitstuffremover_next_state <= 3'd5;
+				end else begin
+					rxbitstuffremover_next_state <= 1'd0;
+				end
+			end
+		end
+		3'd5: begin
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				if (usbdevice_usbfsrx_nrzi_o_data1) begin
+					rxbitstuffremover_next_state <= 3'd6;
+				end else begin
+					rxbitstuffremover_next_state <= 1'd0;
+				end
+			end
+		end
+		3'd6: begin
+			usbdevice_usbfsrx_bitstuff_drop_bit <= 1'd1;
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				rxbitstuffremover_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			if (usbdevice_usbfsrx_nrzi_o_valid1) begin
+				if (usbdevice_usbfsrx_nrzi_o_data1) begin
+					rxbitstuffremover_next_state <= 1'd1;
+				end else begin
+					rxbitstuffremover_next_state <= 1'd0;
+				end
+			end
+		end
+	endcase
+end
+assign usbdevice_usbfsrx_data_put = usbdevice_usbfsrx_data_shifter_o_full;
+always @(*) begin
+	rxpacketdecode_next_state <= 3'd0;
+	usbdevice_usbfsrx_pkt_start <= 1'd0;
+	usbdevice_usbfsrx_pkt_active0 <= 1'd0;
+	usbdevice_usbfsrx_pkt_end0 <= 1'd0;
+	rxpacketdecode_next_state <= rxpacketdecode_state;
+	case (rxpacketdecode_state)
+		1'd1: begin
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if ((usbdevice_usbfsrx_bitstuff_o_data | usbdevice_usbfsrx_bitstuff_o_se0)) begin
+					rxpacketdecode_next_state <= 1'd0;
+				end else begin
+					rxpacketdecode_next_state <= 2'd2;
+				end
+			end
+		end
+		2'd2: begin
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if ((usbdevice_usbfsrx_bitstuff_o_data | usbdevice_usbfsrx_bitstuff_o_se0)) begin
+					rxpacketdecode_next_state <= 1'd0;
+				end else begin
+					rxpacketdecode_next_state <= 2'd3;
+				end
+			end
+		end
+		2'd3: begin
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if ((usbdevice_usbfsrx_bitstuff_o_data | usbdevice_usbfsrx_bitstuff_o_se0)) begin
+					rxpacketdecode_next_state <= 1'd0;
+				end else begin
+					rxpacketdecode_next_state <= 3'd4;
+				end
+			end
+		end
+		3'd4: begin
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if ((usbdevice_usbfsrx_bitstuff_o_data | usbdevice_usbfsrx_bitstuff_o_se0)) begin
+					rxpacketdecode_next_state <= 1'd0;
+				end else begin
+					rxpacketdecode_next_state <= 3'd5;
+				end
+			end
+		end
+		3'd5: begin
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if (usbdevice_usbfsrx_bitstuff_o_data) begin
+					usbdevice_usbfsrx_pkt_start <= 1'd1;
+					usbdevice_usbfsrx_pkt_active0 <= 1'd1;
+					rxpacketdecode_next_state <= 3'd6;
+				end
+			end
+		end
+		3'd6: begin
+			usbdevice_usbfsrx_pkt_active0 <= 1'd1;
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if (usbdevice_usbfsrx_bitstuff_o_se0) begin
+					usbdevice_usbfsrx_pkt_end0 <= 1'd1;
+					usbdevice_usbfsrx_pkt_active0 <= 1'd0;
+					rxpacketdecode_next_state <= 1'd0;
+				end
+			end
+		end
+		default: begin
+			if (usbdevice_usbfsrx_bitstuff_o_valid) begin
+				if ((usbdevice_usbfsrx_bitstuff_o_data | usbdevice_usbfsrx_bitstuff_o_se0)) begin
+					rxpacketdecode_next_state <= 1'd0;
+				end else begin
+					rxpacketdecode_next_state <= 1'd1;
+				end
+			end
+		end
+	endcase
+end
+assign usbdevice_usbfsrx_pid_shifter_o_full = usbdevice_usbfsrx_pid_shifter_shift_reg[0];
+assign usbdevice_usbfsrx_pid_shifter_o_output = usbdevice_usbfsrx_pid_shifter_shift_reg[8:1];
+assign usbdevice_usbfsrx_tok_shifter_o_full = usbdevice_usbfsrx_tok_shifter_shift_reg[0];
+assign usbdevice_usbfsrx_tok_shifter_o_output = usbdevice_usbfsrx_tok_shifter_shift_reg[16:1];
+assign usbdevice_usbfsrx_tok_crc5_crc_good = (usbdevice_usbfsrx_tok_crc5_crc == 4'd12);
+assign usbdevice_usbfsrx_tok_crc5_crc_invert = (usbdevice_usbfsrx_data ^ usbdevice_usbfsrx_tok_crc5_crc[4]);
+assign usbdevice_usbfsrx_data_shifter_o_full = usbdevice_usbfsrx_data_shifter_shift_reg[0];
+assign usbdevice_usbfsrx_data_shifter_o_output = usbdevice_usbfsrx_data_shifter_shift_reg[8:1];
+assign usbdevice_usbfsrx_data_crc16_crc_good = (usbdevice_usbfsrx_data_crc16_crc == 16'd32781);
+assign usbdevice_usbfsrx_data_crc16_crc_invert = (usbdevice_usbfsrx_data ^ usbdevice_usbfsrx_data_crc16_crc[15]);
+assign usbdevice_usbfstx_bitstuff_stall = usbdevice_usbfstx_bitstuffer_o_stall;
+always @(*) begin
+	usbdevice_usbfstx_pkt_active <= 1'd0;
+	usbdevice_usbfstx_shift_sync <= 1'd0;
+	usbdevice_usbfstx_shift_pid <= 1'd0;
+	usbdevice_usbfstx_shift_eop <= 1'd0;
+	usbdevice_usbfstx_load_data <= 1'd0;
+	usbdevice_usbfstx_shift_data <= 1'd0;
+	usbdevice_usbfstx_load_crc16 <= 1'd0;
+	usbdevice_usbfstx_shift_crc16 <= 1'd0;
+	usbdevice_usbfstx_pkt_end <= 1'd0;
+	fsm_next_state <= 3'd0;
+	fsm_next_state <= fsm_state;
+	case (fsm_state)
+		1'd1: begin
+			usbdevice_usbfstx_pkt_active <= 1'd1;
+			usbdevice_usbfstx_shift_sync <= 1'd1;
+			if (usbdevice_usbfstx_sync_shifter_o_empty) begin
+				fsm_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			usbdevice_usbfstx_pkt_active <= 1'd1;
+			usbdevice_usbfstx_shift_pid <= 1'd1;
+			if (usbdevice_usbfstx_pid_shifter_o_empty) begin
+				if (usbdevice_usbfstx_pid_is_data) begin
+					if (usbdevice_tx_data_avail) begin
+						usbdevice_usbfstx_load_data <= 1'd1;
+						fsm_next_state <= 2'd3;
+					end else begin
+						usbdevice_usbfstx_load_crc16 <= 1'd1;
+						fsm_next_state <= 3'd4;
+					end
+				end else begin
+					fsm_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd3: begin
+			usbdevice_usbfstx_pkt_active <= 1'd1;
+			usbdevice_usbfstx_shift_data <= 1'd1;
+			if (usbdevice_usbfstx_data_shifter_o_empty) begin
+				if (usbdevice_tx_data_avail) begin
+					usbdevice_usbfstx_load_data <= 1'd1;
+				end else begin
+					usbdevice_usbfstx_load_crc16 <= 1'd1;
+					fsm_next_state <= 3'd4;
+				end
+			end
+		end
+		3'd4: begin
+			usbdevice_usbfstx_pkt_active <= 1'd1;
+			usbdevice_usbfstx_shift_crc16 <= 1'd1;
+			if (usbdevice_usbfstx_crc16_shifter_o_empty) begin
+				fsm_next_state <= 3'd5;
+			end
+		end
+		3'd5: begin
+			usbdevice_usbfstx_pkt_active <= 1'd1;
+			usbdevice_usbfstx_shift_eop <= 1'd1;
+			if (usbdevice_usbfsrx_line_state_valid) begin
+				fsm_next_state <= 3'd6;
+			end
+		end
+		3'd6: begin
+			usbdevice_usbfstx_pkt_active <= 1'd1;
+			usbdevice_usbfstx_shift_eop <= 1'd1;
+			usbdevice_usbfstx_pkt_end <= 1'd1;
+			if (usbdevice_usbfsrx_line_state_valid) begin
+				fsm_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			if (usbdevice_tx_pkt_start) begin
+				fsm_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+assign usbdevice_usbfstx_sync_shifter_o_data = usbdevice_usbfstx_sync_shifter_shifter[0];
+assign usbdevice_usbfstx_sync_shifter_o_empty = (~usbdevice_usbfstx_sync_shifter_not_empty);
+assign usbdevice_usbfstx_pid_shifter_o_data = usbdevice_usbfstx_pid_shifter_shifter[0];
+assign usbdevice_usbfstx_pid_shifter_o_empty = (~usbdevice_usbfstx_pid_shifter_not_empty);
+assign usbdevice_usbfstx_data_shifter_o_data = usbdevice_usbfstx_data_shifter_shifter[0];
+assign usbdevice_usbfstx_data_shifter_o_empty = (~usbdevice_usbfstx_data_shifter_not_empty);
+assign usbdevice_usbfstx_crc_invert = (usbdevice_usbfstx_data_shifter_o_data ^ usbdevice_usbfstx_crc[15]);
+always @(*) begin
+	usbdevice_usbfstx_o_crc <= 16'd0;
+	usbdevice_usbfstx_o_crc[0] <= (1'd1 ^ usbdevice_usbfstx_crc[15]);
+	usbdevice_usbfstx_o_crc[1] <= (1'd1 ^ usbdevice_usbfstx_crc[14]);
+	usbdevice_usbfstx_o_crc[2] <= (1'd1 ^ usbdevice_usbfstx_crc[13]);
+	usbdevice_usbfstx_o_crc[3] <= (1'd1 ^ usbdevice_usbfstx_crc[12]);
+	usbdevice_usbfstx_o_crc[4] <= (1'd1 ^ usbdevice_usbfstx_crc[11]);
+	usbdevice_usbfstx_o_crc[5] <= (1'd1 ^ usbdevice_usbfstx_crc[10]);
+	usbdevice_usbfstx_o_crc[6] <= (1'd1 ^ usbdevice_usbfstx_crc[9]);
+	usbdevice_usbfstx_o_crc[7] <= (1'd1 ^ usbdevice_usbfstx_crc[8]);
+	usbdevice_usbfstx_o_crc[8] <= (1'd1 ^ usbdevice_usbfstx_crc[7]);
+	usbdevice_usbfstx_o_crc[9] <= (1'd1 ^ usbdevice_usbfstx_crc[6]);
+	usbdevice_usbfstx_o_crc[10] <= (1'd1 ^ usbdevice_usbfstx_crc[5]);
+	usbdevice_usbfstx_o_crc[11] <= (1'd1 ^ usbdevice_usbfstx_crc[4]);
+	usbdevice_usbfstx_o_crc[12] <= (1'd1 ^ usbdevice_usbfstx_crc[3]);
+	usbdevice_usbfstx_o_crc[13] <= (1'd1 ^ usbdevice_usbfstx_crc[2]);
+	usbdevice_usbfstx_o_crc[14] <= (1'd1 ^ usbdevice_usbfstx_crc[1]);
+	usbdevice_usbfstx_o_crc[15] <= (1'd1 ^ usbdevice_usbfstx_crc[0]);
+end
+assign usbdevice_usbfstx_crc16_shifter_o_data = usbdevice_usbfstx_crc16_shifter_shifter[0];
+assign usbdevice_usbfstx_crc16_shifter_o_empty = (~usbdevice_usbfstx_crc16_shifter_not_empty);
+assign usbdevice_usbfstx_bitstuffer_o_stall = usbdevice_usbfstx_bitstuffer_stuff_bit;
+always @(*) begin
+	txbitstuffer_next_state <= 3'd0;
+	usbdevice_usbfstx_bitstuffer_stuff_bit <= 1'd0;
+	txbitstuffer_next_state <= txbitstuffer_state;
+	case (txbitstuffer_state)
+		1'd1: begin
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_mux_stuff_data) begin
+					txbitstuffer_next_state <= 2'd2;
+				end else begin
+					txbitstuffer_next_state <= 1'd0;
+				end
+			end
+		end
+		2'd2: begin
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_mux_stuff_data) begin
+					txbitstuffer_next_state <= 2'd3;
+				end else begin
+					txbitstuffer_next_state <= 1'd0;
+				end
+			end
+		end
+		2'd3: begin
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_mux_stuff_data) begin
+					txbitstuffer_next_state <= 3'd4;
+				end else begin
+					txbitstuffer_next_state <= 1'd0;
+				end
+			end
+		end
+		3'd4: begin
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_mux_stuff_data) begin
+					txbitstuffer_next_state <= 3'd5;
+				end else begin
+					txbitstuffer_next_state <= 1'd0;
+				end
+			end
+		end
+		3'd5: begin
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_mux_stuff_data) begin
+					txbitstuffer_next_state <= 3'd6;
+				end else begin
+					txbitstuffer_next_state <= 1'd0;
+				end
+			end
+		end
+		3'd6: begin
+			usbdevice_usbfstx_bitstuffer_stuff_bit <= 1'd1;
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				txbitstuffer_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_mux_stuff_data) begin
+					txbitstuffer_next_state <= 1'd1;
+				end else begin
+					txbitstuffer_next_state <= 1'd0;
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	usbdevice_usbfstx_nrzi_usbn <= 1'd0;
+	usbdevice_usbfstx_nrzi_oe <= 1'd0;
+	txnrziencoder_next_state <= 3'd0;
+	usbdevice_usbfstx_nrzi_usbp <= 1'd0;
+	txnrziencoder_next_state <= txnrziencoder_state;
+	case (txnrziencoder_state)
+		1'd1: begin
+			usbdevice_usbfstx_nrzi_usbp <= 1'd1;
+			usbdevice_usbfstx_nrzi_usbn <= 1'd0;
+			usbdevice_usbfstx_nrzi_oe <= 1'd1;
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_bitstuffer_o_se0) begin
+					txnrziencoder_next_state <= 2'd3;
+				end else begin
+					if (usbdevice_usbfstx_bitstuffer_o_data) begin
+						txnrziencoder_next_state <= 1'd1;
+					end else begin
+						txnrziencoder_next_state <= 2'd2;
+					end
+				end
+			end
+		end
+		2'd2: begin
+			usbdevice_usbfstx_nrzi_usbp <= 1'd0;
+			usbdevice_usbfstx_nrzi_usbn <= 1'd1;
+			usbdevice_usbfstx_nrzi_oe <= 1'd1;
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_bitstuffer_o_se0) begin
+					txnrziencoder_next_state <= 2'd3;
+				end else begin
+					if (usbdevice_usbfstx_bitstuffer_o_data) begin
+						txnrziencoder_next_state <= 2'd2;
+					end else begin
+						txnrziencoder_next_state <= 1'd1;
+					end
+				end
+			end
+		end
+		2'd3: begin
+			usbdevice_usbfstx_nrzi_usbp <= 1'd0;
+			usbdevice_usbfstx_nrzi_usbn <= 1'd0;
+			usbdevice_usbfstx_nrzi_oe <= 1'd1;
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_bitstuffer_o_se0) begin
+					txnrziencoder_next_state <= 2'd3;
+				end else begin
+					txnrziencoder_next_state <= 3'd4;
+				end
+			end
+		end
+		3'd4: begin
+			usbdevice_usbfstx_nrzi_usbp <= 1'd1;
+			usbdevice_usbfstx_nrzi_usbn <= 1'd0;
+			usbdevice_usbfstx_nrzi_oe <= 1'd1;
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				txnrziencoder_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			usbdevice_usbfstx_nrzi_usbp <= 1'd1;
+			usbdevice_usbfstx_nrzi_usbn <= 1'd0;
+			usbdevice_usbfstx_nrzi_oe <= 1'd0;
+			if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+				if (usbdevice_usbfstx_bitstuffer_o_oe) begin
+					txnrziencoder_next_state <= 2'd2;
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	usbdevice_out_tx_pkt_start <= 1'd0;
+	usbdevice_out_tx_pid <= 4'd0;
+	fsm0_next_state <= 3'd0;
+	usbdevice_o_out_commit <= 1'd0;
+	usbdevice_o_out_rollback <= 1'd0;
+	fsm0_next_state <= fsm0_state;
+	case (fsm0_state)
+		1'd1: begin
+			if (usbdevice_usbfsrx_o_pkt_end1) begin
+				if (usbdevice_valid_data_packet) begin
+					fsm0_next_state <= 2'd2;
+				end else begin
+					fsm0_next_state <= 3'd5;
+				end
+				fsm0_next_state <= 1'd0;
+			end
+		end
+		2'd2: begin
+			usbdevice_out_tx_pid <= 2'd2;
+			usbdevice_out_tx_pkt_start <= 1'd1;
+			usbdevice_o_out_commit <= 1'd1;
+			fsm0_next_state <= 1'd0;
+		end
+		2'd3: begin
+			if (usbdevice_usbfsrx_o_pkt_end1) begin
+				if (usbdevice_valid_data_packet) begin
+					fsm0_next_state <= 3'd4;
+				end else begin
+					fsm0_next_state <= 3'd5;
+				end
+			end
+		end
+		3'd4: begin
+			usbdevice_out_tx_pid <= 4'd10;
+			usbdevice_out_tx_pkt_start <= 1'd1;
+			fsm0_next_state <= 3'd5;
+		end
+		3'd5: begin
+			usbdevice_o_out_rollback <= 1'd1;
+			fsm0_next_state <= 1'd0;
+		end
+		default: begin
+			if ((usbdevice_usbfsrx_o_pkt_end1 & usbdevice_valid_out_token)) begin
+				if (t_array_muxed) begin
+					fsm0_next_state <= 1'd1;
+				end else begin
+					fsm0_next_state <= 2'd3;
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
+	usbdevice_in_tx_pkt_start <= 1'd0;
+	fsm1_next_state <= 3'd0;
+	usbdevice_in_tx_pid <= 4'd0;
+	usbdevice_o_in_commit <= 1'd0;
+	usbdevice_o_in_rollback <= 1'd0;
+	fsm1_next_state <= fsm1_state;
+	case (fsm1_state)
+		1'd1: begin
+			if (basiclowerer_array_muxed) begin
+				fsm1_next_state <= 2'd2;
+			end else begin
+				fsm1_next_state <= 2'd3;
+			end
+		end
+		2'd2: begin
+			usbdevice_in_tx_pid <= (rhs_array_muxed ? 4'd11 : 2'd3);
+			usbdevice_in_tx_pkt_start <= 1'd1;
+			fsm1_next_state <= 3'd4;
+		end
+		2'd3: begin
+			usbdevice_in_tx_pid <= 4'd10;
+			usbdevice_in_tx_pkt_start <= 1'd1;
+			fsm1_next_state <= 1'd0;
+		end
+		3'd4: begin
+			if (usbdevice_usbfsrx_o_pkt_end1) begin
+				if (usbdevice_valid_ack_packet) begin
+					usbdevice_o_in_commit <= 1'd1;
+					fsm1_next_state <= 1'd0;
+				end else begin
+					if (usbdevice_valid_in_token) begin
+						usbdevice_o_in_rollback <= 1'd1;
+						fsm1_next_state <= 1'd1;
+					end else begin
+						usbdevice_o_in_rollback <= 1'd1;
+						fsm1_next_state <= 1'd0;
+					end
+				end
+			end
+		end
+		default: begin
+			if ((usbdevice_usbfsrx_o_pkt_end1 & usbdevice_valid_in_token)) begin
+				fsm1_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+assign io_output = io_storage;
+assign scope_clk = sys_clk;
+assign scope_rst = sys_rst;
+assign mux_valid = 1'd1;
+assign mux_payload_data = {usb_d_n, usb_d_p};
+always @(*) begin
+	mux_source_first <= 1'd0;
+	mux_source_last <= 1'd0;
+	mux_source_payload_data <= 2'd0;
+	mux_source_payload_hit <= 1'd0;
+	mux_ready <= 1'd0;
+	mux_source_valid <= 1'd0;
+	case (mux_value)
+		1'd0: begin
+			mux_source_valid <= mux_valid;
+			mux_ready <= mux_source_ready;
+			mux_source_first <= mux_first;
+			mux_source_last <= mux_last;
+			mux_source_payload_data <= mux_payload_data;
+			mux_source_payload_hit <= mux_payload_hit;
+		end
+	endcase
+end
+assign trigger_mem_sink_valid = trigger_mem_write_re;
+assign trigger_mem_sink_payload_mask = trigger_mem_mask_storage;
+assign trigger_mem_sink_payload_value = trigger_mem_value_storage;
+assign trigger_mem_full_status = (~trigger_mem_sink_ready);
+assign trigger_wait = (~((~trigger_enable) & trigger_enable_d));
+assign trigger_hit = ((trigger_sink_sink_payload_data & trigger_mem_source_payload_mask) == trigger_mem_source_payload_value);
+assign trigger_mem_source_ready = (trigger_enable & (trigger_hit | (~trigger_done1)));
+assign trigger_source_source_valid = trigger_sink_sink_valid;
+assign trigger_sink_sink_ready = trigger_source_source_ready;
+assign trigger_source_source_first = trigger_sink_sink_first;
+assign trigger_source_source_last = trigger_sink_sink_last;
+assign trigger_source_source_payload_data = trigger_sink_sink_payload_data;
+assign trigger_done0 = (~trigger_mem_source_valid);
+always @(*) begin
+	trigger_source_source_payload_hit <= 1'd0;
+	trigger_source_source_payload_hit <= trigger_sink_sink_payload_hit;
+	trigger_source_source_payload_hit <= trigger_done0;
+end
+assign trigger_mem_asyncfifo_din = {trigger_mem_fifo_in_last, trigger_mem_fifo_in_first, trigger_mem_fifo_in_payload_value, trigger_mem_fifo_in_payload_mask};
+assign {trigger_mem_fifo_out_last, trigger_mem_fifo_out_first, trigger_mem_fifo_out_payload_value, trigger_mem_fifo_out_payload_mask} = trigger_mem_asyncfifo_dout;
+assign trigger_mem_sink_ready = trigger_mem_asyncfifo_writable;
+assign trigger_mem_asyncfifo_we = trigger_mem_sink_valid;
+assign trigger_mem_fifo_in_first = trigger_mem_sink_first;
+assign trigger_mem_fifo_in_last = trigger_mem_sink_last;
+assign trigger_mem_fifo_in_payload_mask = trigger_mem_sink_payload_mask;
+assign trigger_mem_fifo_in_payload_value = trigger_mem_sink_payload_value;
+assign trigger_mem_source_valid = trigger_mem_asyncfifo_readable;
+assign trigger_mem_source_first = trigger_mem_fifo_out_first;
+assign trigger_mem_source_last = trigger_mem_fifo_out_last;
+assign trigger_mem_source_payload_mask = trigger_mem_fifo_out_payload_mask;
+assign trigger_mem_source_payload_value = trigger_mem_fifo_out_payload_value;
+assign trigger_mem_asyncfifo_re = trigger_mem_source_ready;
+assign trigger_mem_graycounter0_ce = (trigger_mem_asyncfifo_writable & trigger_mem_asyncfifo_we);
+assign trigger_mem_graycounter1_ce = (trigger_mem_asyncfifo_readable & trigger_mem_asyncfifo_re);
+assign trigger_mem_asyncfifo_writable = (((trigger_mem_graycounter0_q[4] == trigger_mem_consume_wdomain[4]) | (trigger_mem_graycounter0_q[3] == trigger_mem_consume_wdomain[3])) | (trigger_mem_graycounter0_q[2:0] != trigger_mem_consume_wdomain[2:0]));
+assign trigger_mem_asyncfifo_readable = (trigger_mem_graycounter1_q != trigger_mem_produce_rdomain);
+assign trigger_mem_wrport_adr = trigger_mem_graycounter0_q_binary[3:0];
+assign trigger_mem_wrport_dat_w = trigger_mem_asyncfifo_din;
+assign trigger_mem_wrport_we = trigger_mem_graycounter0_ce;
+assign trigger_mem_rdport_adr = trigger_mem_graycounter1_q_next_binary[3:0];
+assign trigger_mem_asyncfifo_dout = trigger_mem_rdport_dat_r;
+always @(*) begin
+	trigger_mem_graycounter0_q_next_binary <= 5'd0;
+	if (trigger_mem_graycounter0_ce) begin
+		trigger_mem_graycounter0_q_next_binary <= (trigger_mem_graycounter0_q_binary + 1'd1);
+	end else begin
+		trigger_mem_graycounter0_q_next_binary <= trigger_mem_graycounter0_q_binary;
+	end
+end
+assign trigger_mem_graycounter0_q_next = (trigger_mem_graycounter0_q_next_binary ^ trigger_mem_graycounter0_q_next_binary[4:1]);
+always @(*) begin
+	trigger_mem_graycounter1_q_next_binary <= 5'd0;
+	if (trigger_mem_graycounter1_ce) begin
+		trigger_mem_graycounter1_q_next_binary <= (trigger_mem_graycounter1_q_binary + 1'd1);
+	end else begin
+		trigger_mem_graycounter1_q_next_binary <= trigger_mem_graycounter1_q_binary;
+	end
+end
+assign trigger_mem_graycounter1_q_next = (trigger_mem_graycounter1_q_next_binary ^ trigger_mem_graycounter1_q_next_binary[4:1]);
+assign trigger_done1 = (trigger_count == 1'd0);
+assign subsampler_done = (subsampler_counter == subsampler_value);
+assign subsampler_sink_ready = subsampler_source_ready;
+assign subsampler_source_first = subsampler_sink_first;
+assign subsampler_source_last = subsampler_sink_last;
+assign subsampler_source_payload_data = subsampler_sink_payload_data;
+assign subsampler_source_payload_hit = subsampler_sink_payload_hit;
+assign subsampler_source_valid = (subsampler_sink_valid & subsampler_done);
+assign storage_mem_valid_status = storage_cdc_source_valid;
+assign storage_cdc_source_ready = (storage_mem_ready_re | (~storage_enable_storage));
+assign storage_mem_data_status = storage_cdc_source_payload_data;
+assign storage_mem_syncfifo_din = {storage_mem_fifo_in_last, storage_mem_fifo_in_first, storage_mem_fifo_in_payload_data};
+assign {storage_mem_fifo_out_last, storage_mem_fifo_out_first, storage_mem_fifo_out_payload_data} = storage_mem_syncfifo_dout;
+assign storage_mem_sink_ready = storage_mem_syncfifo_writable;
+assign storage_mem_syncfifo_we = storage_mem_sink_valid;
+assign storage_mem_fifo_in_first = storage_mem_sink_first;
+assign storage_mem_fifo_in_last = storage_mem_sink_last;
+assign storage_mem_fifo_in_payload_data = storage_mem_sink_payload_data;
+assign storage_mem_source_valid = storage_mem_readable;
+assign storage_mem_source_first = storage_mem_fifo_out_first;
+assign storage_mem_source_last = storage_mem_fifo_out_last;
+assign storage_mem_source_payload_data = storage_mem_fifo_out_payload_data;
+assign storage_mem_re = storage_mem_source_ready;
+assign storage_mem_syncfifo_re = (storage_mem_syncfifo_readable & ((~storage_mem_readable) | storage_mem_re));
+assign storage_mem_level1 = (storage_mem_level0 + storage_mem_readable);
+always @(*) begin
+	storage_mem_wrport_adr <= 8'd0;
+	if (storage_mem_replace) begin
+		storage_mem_wrport_adr <= (storage_mem_produce - 1'd1);
+	end else begin
+		storage_mem_wrport_adr <= storage_mem_produce;
+	end
+end
+assign storage_mem_wrport_dat_w = storage_mem_syncfifo_din;
+assign storage_mem_wrport_we = (storage_mem_syncfifo_we & (storage_mem_syncfifo_writable | storage_mem_replace));
+assign storage_mem_do_read = (storage_mem_syncfifo_readable & storage_mem_syncfifo_re);
+assign storage_mem_rdport_adr = storage_mem_consume;
+assign storage_mem_syncfifo_dout = storage_mem_rdport_dat_r;
+assign storage_mem_rdport_re = storage_mem_do_read;
+assign storage_mem_syncfifo_writable = (storage_mem_level0 != 9'd256);
+assign storage_mem_syncfifo_readable = (storage_mem_level0 != 1'd0);
+assign storage_cdc_asyncfifo_din = {storage_cdc_fifo_in_last, storage_cdc_fifo_in_first, storage_cdc_fifo_in_payload_data};
+assign {storage_cdc_fifo_out_last, storage_cdc_fifo_out_first, storage_cdc_fifo_out_payload_data} = storage_cdc_asyncfifo_dout;
+assign storage_cdc_sink_ready = storage_cdc_asyncfifo_writable;
+assign storage_cdc_asyncfifo_we = storage_cdc_sink_valid;
+assign storage_cdc_fifo_in_first = storage_cdc_sink_first;
+assign storage_cdc_fifo_in_last = storage_cdc_sink_last;
+assign storage_cdc_fifo_in_payload_data = storage_cdc_sink_payload_data;
+assign storage_cdc_source_valid = storage_cdc_asyncfifo_readable;
+assign storage_cdc_source_first = storage_cdc_fifo_out_first;
+assign storage_cdc_source_last = storage_cdc_fifo_out_last;
+assign storage_cdc_source_payload_data = storage_cdc_fifo_out_payload_data;
+assign storage_cdc_asyncfifo_re = storage_cdc_source_ready;
+assign storage_cdc_graycounter0_ce = (storage_cdc_asyncfifo_writable & storage_cdc_asyncfifo_we);
+assign storage_cdc_graycounter1_ce = (storage_cdc_asyncfifo_readable & storage_cdc_asyncfifo_re);
+assign storage_cdc_asyncfifo_writable = (((storage_cdc_graycounter0_q[2] == storage_cdc_consume_wdomain[2]) | (storage_cdc_graycounter0_q[1] == storage_cdc_consume_wdomain[1])) | (storage_cdc_graycounter0_q[0] != storage_cdc_consume_wdomain[0]));
+assign storage_cdc_asyncfifo_readable = (storage_cdc_graycounter1_q != storage_cdc_produce_rdomain);
+assign storage_cdc_wrport_adr = storage_cdc_graycounter0_q_binary[1:0];
+assign storage_cdc_wrport_dat_w = storage_cdc_asyncfifo_din;
+assign storage_cdc_wrport_we = storage_cdc_graycounter0_ce;
+assign storage_cdc_rdport_adr = storage_cdc_graycounter1_q_next_binary[1:0];
+assign storage_cdc_asyncfifo_dout = storage_cdc_rdport_dat_r;
+always @(*) begin
+	storage_cdc_graycounter0_q_next_binary <= 3'd0;
+	if (storage_cdc_graycounter0_ce) begin
+		storage_cdc_graycounter0_q_next_binary <= (storage_cdc_graycounter0_q_binary + 1'd1);
+	end else begin
+		storage_cdc_graycounter0_q_next_binary <= storage_cdc_graycounter0_q_binary;
+	end
+end
+assign storage_cdc_graycounter0_q_next = (storage_cdc_graycounter0_q_next_binary ^ storage_cdc_graycounter0_q_next_binary[2:1]);
+always @(*) begin
+	storage_cdc_graycounter1_q_next_binary <= 3'd0;
+	if (storage_cdc_graycounter1_ce) begin
+		storage_cdc_graycounter1_q_next_binary <= (storage_cdc_graycounter1_q_binary + 1'd1);
+	end else begin
+		storage_cdc_graycounter1_q_next_binary <= storage_cdc_graycounter1_q_binary;
+	end
+end
+assign storage_cdc_graycounter1_q_next = (storage_cdc_graycounter1_q_next_binary ^ storage_cdc_graycounter1_q_next_binary[2:1]);
+assign storage_done1 = (storage_count == 1'd0);
+always @(*) begin
+	storage_wait <= 1'd0;
+	storage_cdc_sink_valid <= 1'd0;
+	storage_cdc_sink_first <= 1'd0;
+	litescopeanalyzer_next_state <= 2'd0;
+	storage_cdc_sink_last <= 1'd0;
+	storage_sink_sink_ready <= 1'd0;
+	storage_done0 <= 1'd0;
+	storage_cdc_sink_payload_data <= 2'd0;
+	storage_mem_sink_valid <= 1'd0;
+	storage_mem_sink_first <= 1'd0;
+	storage_mem_sink_last <= 1'd0;
+	storage_mem_sink_payload_data <= 2'd0;
+	storage_mem_source_ready <= 1'd0;
+	litescopeanalyzer_next_state <= litescopeanalyzer_state;
+	case (litescopeanalyzer_state)
+		1'd1: begin
+			storage_sink_sink_ready <= 1'd1;
+			storage_wait <= 1'd1;
+			storage_mem_source_ready <= 1'd1;
+			if (storage_done1) begin
+				litescopeanalyzer_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			storage_mem_sink_valid <= storage_sink_sink_valid;
+			storage_sink_sink_ready <= storage_mem_sink_ready;
+			storage_mem_sink_first <= storage_sink_sink_first;
+			storage_mem_sink_last <= storage_sink_sink_last;
+			storage_mem_sink_payload_data <= storage_sink_sink_payload_data;
+			if ((storage_sink_sink_valid & storage_sink_sink_payload_hit)) begin
+				litescopeanalyzer_next_state <= 2'd3;
+			end
+			storage_mem_source_ready <= (storage_mem_level1 >= storage_offset_storage);
+		end
+		2'd3: begin
+			storage_mem_sink_valid <= storage_sink_sink_valid;
+			storage_sink_sink_ready <= storage_mem_sink_ready;
+			storage_mem_sink_first <= storage_sink_sink_first;
+			storage_mem_sink_last <= storage_sink_sink_last;
+			storage_mem_sink_payload_data <= storage_sink_sink_payload_data;
+			if ((storage_mem_level1 >= storage_length_storage)) begin
+				litescopeanalyzer_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			storage_done0 <= 1'd1;
+			if ((storage_enable & (~storage_enable_d))) begin
+				litescopeanalyzer_next_state <= 1'd1;
+			end
+			storage_sink_sink_ready <= 1'd1;
+			storage_cdc_sink_valid <= storage_mem_source_valid;
+			storage_mem_source_ready <= storage_cdc_sink_ready;
+			storage_cdc_sink_first <= storage_mem_source_first;
+			storage_cdc_sink_last <= storage_mem_source_last;
+			storage_cdc_sink_payload_data <= storage_mem_source_payload_data;
+		end
+	endcase
+end
+assign trigger_sink_sink_valid = mux_source_valid;
+assign mux_source_ready = trigger_sink_sink_ready;
+assign trigger_sink_sink_first = mux_source_first;
+assign trigger_sink_sink_last = mux_source_last;
+assign trigger_sink_sink_payload_data = mux_source_payload_data;
+assign trigger_sink_sink_payload_hit = mux_source_payload_hit;
+assign subsampler_sink_valid = trigger_source_source_valid;
+assign trigger_source_source_ready = subsampler_sink_ready;
+assign subsampler_sink_first = trigger_source_source_first;
+assign subsampler_sink_last = trigger_source_source_last;
+assign subsampler_sink_payload_data = trigger_source_source_payload_data;
+assign subsampler_sink_payload_hit = trigger_source_source_payload_hit;
+assign storage_sink_sink_valid = subsampler_source_valid;
+assign subsampler_source_ready = storage_sink_sink_ready;
+assign storage_sink_sink_first = subsampler_source_first;
+assign storage_sink_sink_last = subsampler_source_last;
+assign storage_sink_sink_payload_data = subsampler_source_payload_data;
+assign storage_sink_sink_payload_hit = subsampler_source_payload_hit;
+assign shared_adr = array_muxed0;
+assign shared_dat_w = array_muxed1;
+assign shared_sel = array_muxed2;
+assign shared_cyc = array_muxed3;
+assign shared_stb = array_muxed4;
+assign shared_we = array_muxed5;
+assign shared_cti = array_muxed6;
+assign shared_bte = array_muxed7;
+assign uartwishbonebridge_wishbone_dat_r = shared_dat_r;
+assign uartwishbonebridge_wishbone_ack = (shared_ack & (grant == 1'd0));
+assign uartwishbonebridge_wishbone_err = (shared_err & (grant == 1'd0));
+assign request = {uartwishbonebridge_wishbone_cyc};
+assign grant = 1'd0;
+always @(*) begin
+	slave_sel <= 2'd0;
+	slave_sel[0] <= (shared_adr[28:26] == 3'd6);
+	slave_sel[1] <= (shared_adr[28:26] == 2'd2);
+end
+assign usbtestsoc_usbtestsoc_bus_wishbone_adr = shared_adr;
+assign usbtestsoc_usbtestsoc_bus_wishbone_dat_w = shared_dat_w;
+assign usbtestsoc_usbtestsoc_bus_wishbone_sel = shared_sel;
+assign usbtestsoc_usbtestsoc_bus_wishbone_stb = shared_stb;
+assign usbtestsoc_usbtestsoc_bus_wishbone_we = shared_we;
+assign usbtestsoc_usbtestsoc_bus_wishbone_cti = shared_cti;
+assign usbtestsoc_usbtestsoc_bus_wishbone_bte = shared_bte;
+assign usbtestsoc_spiflash_bus_adr = shared_adr;
+assign usbtestsoc_spiflash_bus_dat_w = shared_dat_w;
+assign usbtestsoc_spiflash_bus_sel = shared_sel;
+assign usbtestsoc_spiflash_bus_stb = shared_stb;
+assign usbtestsoc_spiflash_bus_we = shared_we;
+assign usbtestsoc_spiflash_bus_cti = shared_cti;
+assign usbtestsoc_spiflash_bus_bte = shared_bte;
+assign usbtestsoc_usbtestsoc_bus_wishbone_cyc = (shared_cyc & slave_sel[0]);
+assign usbtestsoc_spiflash_bus_cyc = (shared_cyc & slave_sel[1]);
+assign shared_err = (usbtestsoc_usbtestsoc_bus_wishbone_err | usbtestsoc_spiflash_bus_err);
+assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
+always @(*) begin
+	shared_dat_r <= 32'd0;
+	shared_ack <= 1'd0;
+	error <= 1'd0;
+	shared_ack <= (usbtestsoc_usbtestsoc_bus_wishbone_ack | usbtestsoc_spiflash_bus_ack);
+	shared_dat_r <= (({32{slave_sel_r[0]}} & usbtestsoc_usbtestsoc_bus_wishbone_dat_r) | ({32{slave_sel_r[1]}} & usbtestsoc_spiflash_bus_dat_r));
+	if (done) begin
+		shared_dat_r <= 32'd4294967295;
+		shared_ack <= 1'd1;
+		error <= 1'd1;
+	end
+end
+assign done = (count == 1'd0);
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 4'd10);
+assign csrbank0_mux_value0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_mux_value0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 1'd0));
+assign csrbank0_trigger_enable0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_trigger_enable0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 1'd1));
+assign csrbank0_trigger_done_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_trigger_done_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 2'd2));
+assign trigger_mem_write_r = interface0_bank_bus_dat_w[0];
+assign trigger_mem_write_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 2'd3));
+assign csrbank0_trigger_mem_mask0_r = interface0_bank_bus_dat_w[1:0];
+assign csrbank0_trigger_mem_mask0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 3'd4));
+assign csrbank0_trigger_mem_value0_r = interface0_bank_bus_dat_w[1:0];
+assign csrbank0_trigger_mem_value0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 3'd5));
+assign csrbank0_trigger_mem_full_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_trigger_mem_full_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 3'd6));
+assign csrbank0_subsampler_value1_r = interface0_bank_bus_dat_w[7:0];
+assign csrbank0_subsampler_value1_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 3'd7));
+assign csrbank0_subsampler_value0_r = interface0_bank_bus_dat_w[7:0];
+assign csrbank0_subsampler_value0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd8));
+assign csrbank0_storage_enable0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_storage_enable0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd9));
+assign csrbank0_storage_done_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_storage_done_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd10));
+assign csrbank0_storage_length1_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_storage_length1_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd11));
+assign csrbank0_storage_length0_r = interface0_bank_bus_dat_w[7:0];
+assign csrbank0_storage_length0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd12));
+assign csrbank0_storage_offset1_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_storage_offset1_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd13));
+assign csrbank0_storage_offset0_r = interface0_bank_bus_dat_w[7:0];
+assign csrbank0_storage_offset0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd14));
+assign csrbank0_storage_mem_valid_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_storage_mem_valid_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 4'd15));
+assign storage_mem_ready_r = interface0_bank_bus_dat_w[0];
+assign storage_mem_ready_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 5'd16));
+assign csrbank0_storage_mem_data_r = interface0_bank_bus_dat_w[1:0];
+assign csrbank0_storage_mem_data_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[4:0] == 5'd17));
+assign mux_value_storage = mux_value_storage_full;
+assign csrbank0_mux_value0_w = mux_value_storage_full;
+assign trigger_enable_storage = trigger_enable_storage_full;
+assign csrbank0_trigger_enable0_w = trigger_enable_storage_full;
+assign csrbank0_trigger_done_w = trigger_done_status;
+assign trigger_mem_mask_storage = trigger_mem_mask_storage_full[1:0];
+assign csrbank0_trigger_mem_mask0_w = trigger_mem_mask_storage_full[1:0];
+assign trigger_mem_value_storage = trigger_mem_value_storage_full[1:0];
+assign csrbank0_trigger_mem_value0_w = trigger_mem_value_storage_full[1:0];
+assign csrbank0_trigger_mem_full_w = trigger_mem_full_status;
+assign subsampler_value_storage = subsampler_value_storage_full[15:0];
+assign csrbank0_subsampler_value1_w = subsampler_value_storage_full[15:8];
+assign csrbank0_subsampler_value0_w = subsampler_value_storage_full[7:0];
+assign storage_enable_storage = storage_enable_storage_full;
+assign csrbank0_storage_enable0_w = storage_enable_storage_full;
+assign csrbank0_storage_done_w = storage_done_status;
+assign storage_length_storage = storage_length_storage_full[8:0];
+assign csrbank0_storage_length1_w = storage_length_storage_full[8];
+assign csrbank0_storage_length0_w = storage_length_storage_full[7:0];
+assign storage_offset_storage = storage_offset_storage_full[8:0];
+assign csrbank0_storage_offset1_w = storage_offset_storage_full[8];
+assign csrbank0_storage_offset0_w = storage_offset_storage_full[7:0];
+assign csrbank0_storage_mem_valid_w = storage_mem_valid_status;
+assign csrbank0_storage_mem_data_w = storage_mem_data_status[1:0];
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
+assign usbtestsoc_usbtestsoc_reset_reset_r = interface1_bank_bus_dat_w[0];
+assign usbtestsoc_usbtestsoc_reset_reset_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0));
+assign csrbank1_scratch3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_scratch3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1));
+assign csrbank1_scratch2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_scratch2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2));
+assign csrbank1_scratch1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_scratch1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3));
+assign csrbank1_scratch0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_scratch0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4));
+assign csrbank1_bus_errors3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_bus_errors3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5));
+assign csrbank1_bus_errors2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_bus_errors2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6));
+assign csrbank1_bus_errors1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_bus_errors1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7));
+assign csrbank1_bus_errors0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_bus_errors0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8));
+assign usbtestsoc_usbtestsoc_storage = usbtestsoc_usbtestsoc_storage_full[31:0];
+assign csrbank1_scratch3_w = usbtestsoc_usbtestsoc_storage_full[31:24];
+assign csrbank1_scratch2_w = usbtestsoc_usbtestsoc_storage_full[23:16];
+assign csrbank1_scratch1_w = usbtestsoc_usbtestsoc_storage_full[15:8];
+assign csrbank1_scratch0_w = usbtestsoc_usbtestsoc_storage_full[7:0];
+assign csrbank1_bus_errors3_w = usbtestsoc_usbtestsoc_bus_errors_status[31:24];
+assign csrbank1_bus_errors2_w = usbtestsoc_usbtestsoc_bus_errors_status[23:16];
+assign csrbank1_bus_errors1_w = usbtestsoc_usbtestsoc_bus_errors_status[15:8];
+assign csrbank1_bus_errors0_w = usbtestsoc_usbtestsoc_bus_errors_status[7:0];
+assign sel = (sram_bus_adr[13:9] == 3'd4);
+always @(*) begin
+	sram_bus_dat_r <= 8'd0;
+	if (sel_r) begin
+		sram_bus_dat_r <= dat_r;
+	end
+end
+assign adr = sram_bus_adr[3:0];
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 4'd9);
+assign csrbank2_git_commit19_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit19_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 1'd0));
+assign csrbank2_git_commit18_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit18_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 1'd1));
+assign csrbank2_git_commit17_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit17_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 2'd2));
+assign csrbank2_git_commit16_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit16_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 2'd3));
+assign csrbank2_git_commit15_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit15_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 3'd4));
+assign csrbank2_git_commit14_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit14_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 3'd5));
+assign csrbank2_git_commit13_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit13_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 3'd6));
+assign csrbank2_git_commit12_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit12_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 3'd7));
+assign csrbank2_git_commit11_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit11_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd8));
+assign csrbank2_git_commit10_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit10_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd9));
+assign csrbank2_git_commit9_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit9_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd10));
+assign csrbank2_git_commit8_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit8_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd11));
+assign csrbank2_git_commit7_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit7_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd12));
+assign csrbank2_git_commit6_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit6_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd13));
+assign csrbank2_git_commit5_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit5_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd14));
+assign csrbank2_git_commit4_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit4_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 4'd15));
+assign csrbank2_git_commit3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd16));
+assign csrbank2_git_commit2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd17));
+assign csrbank2_git_commit1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd18));
+assign csrbank2_git_commit0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_git_commit0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd19));
+assign csrbank2_platform_platform7_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform7_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd20));
+assign csrbank2_platform_platform6_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform6_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd21));
+assign csrbank2_platform_platform5_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform5_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd22));
+assign csrbank2_platform_platform4_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform4_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd23));
+assign csrbank2_platform_platform3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd24));
+assign csrbank2_platform_platform2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd25));
+assign csrbank2_platform_platform1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd26));
+assign csrbank2_platform_platform0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_platform0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd27));
+assign csrbank2_platform_target7_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target7_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd28));
+assign csrbank2_platform_target6_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target6_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd29));
+assign csrbank2_platform_target5_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target5_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd30));
+assign csrbank2_platform_target4_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target4_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 5'd31));
+assign csrbank2_platform_target3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 6'd32));
+assign csrbank2_platform_target2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 6'd33));
+assign csrbank2_platform_target1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 6'd34));
+assign csrbank2_platform_target0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_platform_target0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:0] == 6'd35));
+assign csrbank2_git_commit19_w = usbtestsoc_status[159:152];
+assign csrbank2_git_commit18_w = usbtestsoc_status[151:144];
+assign csrbank2_git_commit17_w = usbtestsoc_status[143:136];
+assign csrbank2_git_commit16_w = usbtestsoc_status[135:128];
+assign csrbank2_git_commit15_w = usbtestsoc_status[127:120];
+assign csrbank2_git_commit14_w = usbtestsoc_status[119:112];
+assign csrbank2_git_commit13_w = usbtestsoc_status[111:104];
+assign csrbank2_git_commit12_w = usbtestsoc_status[103:96];
+assign csrbank2_git_commit11_w = usbtestsoc_status[95:88];
+assign csrbank2_git_commit10_w = usbtestsoc_status[87:80];
+assign csrbank2_git_commit9_w = usbtestsoc_status[79:72];
+assign csrbank2_git_commit8_w = usbtestsoc_status[71:64];
+assign csrbank2_git_commit7_w = usbtestsoc_status[63:56];
+assign csrbank2_git_commit6_w = usbtestsoc_status[55:48];
+assign csrbank2_git_commit5_w = usbtestsoc_status[47:40];
+assign csrbank2_git_commit4_w = usbtestsoc_status[39:32];
+assign csrbank2_git_commit3_w = usbtestsoc_status[31:24];
+assign csrbank2_git_commit2_w = usbtestsoc_status[23:16];
+assign csrbank2_git_commit1_w = usbtestsoc_status[15:8];
+assign csrbank2_git_commit0_w = usbtestsoc_status[7:0];
+assign csrbank2_platform_platform7_w = usbtestsoc_platform_status[63:56];
+assign csrbank2_platform_platform6_w = usbtestsoc_platform_status[55:48];
+assign csrbank2_platform_platform5_w = usbtestsoc_platform_status[47:40];
+assign csrbank2_platform_platform4_w = usbtestsoc_platform_status[39:32];
+assign csrbank2_platform_platform3_w = usbtestsoc_platform_status[31:24];
+assign csrbank2_platform_platform2_w = usbtestsoc_platform_status[23:16];
+assign csrbank2_platform_platform1_w = usbtestsoc_platform_status[15:8];
+assign csrbank2_platform_platform0_w = usbtestsoc_platform_status[7:0];
+assign csrbank2_platform_target7_w = usbtestsoc_target_status[63:56];
+assign csrbank2_platform_target6_w = usbtestsoc_target_status[55:48];
+assign csrbank2_platform_target5_w = usbtestsoc_target_status[47:40];
+assign csrbank2_platform_target4_w = usbtestsoc_target_status[39:32];
+assign csrbank2_platform_target3_w = usbtestsoc_target_status[31:24];
+assign csrbank2_platform_target2_w = usbtestsoc_target_status[23:16];
+assign csrbank2_platform_target1_w = usbtestsoc_target_status[15:8];
+assign csrbank2_platform_target0_w = usbtestsoc_target_status[7:0];
+assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 4'd11);
+assign csrbank3_in_r = interface3_bank_bus_dat_w[7:0];
+assign csrbank3_in_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[0] == 1'd0));
+assign csrbank3_out0_r = interface3_bank_bus_dat_w[7:0];
+assign csrbank3_out0_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[0] == 1'd1));
+assign csrbank3_in_w = io_status[7:0];
+assign io_storage = io_storage_full[7:0];
+assign csrbank3_out0_w = io_storage_full[7:0];
+assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 4'd8);
+assign csrbank4_bitbang0_r = interface4_bank_bus_dat_w[3:0];
+assign csrbank4_bitbang0_re = ((csrbank4_sel & interface4_bank_bus_we) & (interface4_bank_bus_adr[1:0] == 1'd0));
+assign csrbank4_miso_r = interface4_bank_bus_dat_w[0];
+assign csrbank4_miso_re = ((csrbank4_sel & interface4_bank_bus_we) & (interface4_bank_bus_adr[1:0] == 1'd1));
+assign csrbank4_bitbang_en0_r = interface4_bank_bus_dat_w[0];
+assign csrbank4_bitbang_en0_re = ((csrbank4_sel & interface4_bank_bus_we) & (interface4_bank_bus_adr[1:0] == 2'd2));
+assign usbtestsoc_spiflash_bitbang_storage = usbtestsoc_spiflash_bitbang_storage_full[3:0];
+assign csrbank4_bitbang0_w = usbtestsoc_spiflash_bitbang_storage_full[3:0];
+assign csrbank4_miso_w = usbtestsoc_spiflash_miso_status;
+assign usbtestsoc_spiflash_bitbang_en_storage = usbtestsoc_spiflash_bitbang_en_storage_full;
+assign csrbank4_bitbang_en0_w = usbtestsoc_spiflash_bitbang_en_storage_full;
+assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5);
+assign csrbank5_load3_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_load3_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 1'd0));
+assign csrbank5_load2_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_load2_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 1'd1));
+assign csrbank5_load1_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_load1_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 2'd2));
+assign csrbank5_load0_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_load0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 2'd3));
+assign csrbank5_reload3_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_reload3_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 3'd4));
+assign csrbank5_reload2_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_reload2_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 3'd5));
+assign csrbank5_reload1_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_reload1_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 3'd6));
+assign csrbank5_reload0_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_reload0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 3'd7));
+assign csrbank5_en0_r = interface5_bank_bus_dat_w[0];
+assign csrbank5_en0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd8));
+assign usbtestsoc_usbtestsoc_update_value_r = interface5_bank_bus_dat_w[0];
+assign usbtestsoc_usbtestsoc_update_value_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd9));
+assign csrbank5_value3_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_value3_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd10));
+assign csrbank5_value2_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_value2_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd11));
+assign csrbank5_value1_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_value1_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd12));
+assign csrbank5_value0_r = interface5_bank_bus_dat_w[7:0];
+assign csrbank5_value0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd13));
+assign usbtestsoc_usbtestsoc_eventmanager_status_r = interface5_bank_bus_dat_w[0];
+assign usbtestsoc_usbtestsoc_eventmanager_status_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd14));
+assign usbtestsoc_usbtestsoc_eventmanager_pending_r = interface5_bank_bus_dat_w[0];
+assign usbtestsoc_usbtestsoc_eventmanager_pending_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 4'd15));
+assign csrbank5_ev_enable0_r = interface5_bank_bus_dat_w[0];
+assign csrbank5_ev_enable0_re = ((csrbank5_sel & interface5_bank_bus_we) & (interface5_bank_bus_adr[4:0] == 5'd16));
+assign usbtestsoc_usbtestsoc_load_storage = usbtestsoc_usbtestsoc_load_storage_full[31:0];
+assign csrbank5_load3_w = usbtestsoc_usbtestsoc_load_storage_full[31:24];
+assign csrbank5_load2_w = usbtestsoc_usbtestsoc_load_storage_full[23:16];
+assign csrbank5_load1_w = usbtestsoc_usbtestsoc_load_storage_full[15:8];
+assign csrbank5_load0_w = usbtestsoc_usbtestsoc_load_storage_full[7:0];
+assign usbtestsoc_usbtestsoc_reload_storage = usbtestsoc_usbtestsoc_reload_storage_full[31:0];
+assign csrbank5_reload3_w = usbtestsoc_usbtestsoc_reload_storage_full[31:24];
+assign csrbank5_reload2_w = usbtestsoc_usbtestsoc_reload_storage_full[23:16];
+assign csrbank5_reload1_w = usbtestsoc_usbtestsoc_reload_storage_full[15:8];
+assign csrbank5_reload0_w = usbtestsoc_usbtestsoc_reload_storage_full[7:0];
+assign usbtestsoc_usbtestsoc_en_storage = usbtestsoc_usbtestsoc_en_storage_full;
+assign csrbank5_en0_w = usbtestsoc_usbtestsoc_en_storage_full;
+assign csrbank5_value3_w = usbtestsoc_usbtestsoc_value_status[31:24];
+assign csrbank5_value2_w = usbtestsoc_usbtestsoc_value_status[23:16];
+assign csrbank5_value1_w = usbtestsoc_usbtestsoc_value_status[15:8];
+assign csrbank5_value0_w = usbtestsoc_usbtestsoc_value_status[7:0];
+assign usbtestsoc_usbtestsoc_eventmanager_storage = usbtestsoc_usbtestsoc_eventmanager_storage_full;
+assign csrbank5_ev_enable0_w = usbtestsoc_usbtestsoc_eventmanager_storage_full;
+assign interface0_bank_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign interface1_bank_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign interface2_bank_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign interface3_bank_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign interface4_bank_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign interface5_bank_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign sram_bus_adr = usbtestsoc_usbtestsoc_adr;
+assign interface0_bank_bus_we = usbtestsoc_usbtestsoc_we;
+assign interface1_bank_bus_we = usbtestsoc_usbtestsoc_we;
+assign interface2_bank_bus_we = usbtestsoc_usbtestsoc_we;
+assign interface3_bank_bus_we = usbtestsoc_usbtestsoc_we;
+assign interface4_bank_bus_we = usbtestsoc_usbtestsoc_we;
+assign interface5_bank_bus_we = usbtestsoc_usbtestsoc_we;
+assign sram_bus_we = usbtestsoc_usbtestsoc_we;
+assign interface0_bank_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign interface1_bank_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign interface2_bank_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign interface3_bank_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign interface4_bank_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign interface5_bank_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign sram_bus_dat_w = usbtestsoc_usbtestsoc_dat_w;
+assign usbtestsoc_usbtestsoc_dat_r = ((((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r) | sram_bus_dat_r);
+assign slice_proxy0 = 8'd128;
+assign slice_proxy1 = {(4'd15 ^ usbdevice_tx_pid), usbdevice_tx_pid};
+always @(*) begin
+	t_array_muxed <= 1'd0;
+	case (usbdevice_current_endp)
+		1'd0: begin
+			t_array_muxed <= usbdevice0;
+		end
+		1'd1: begin
+			t_array_muxed <= usbdevice1;
+		end
+		2'd2: begin
+			t_array_muxed <= usbdevice2;
+		end
+		2'd3: begin
+			t_array_muxed <= usbdevice3;
+		end
+		3'd4: begin
+			t_array_muxed <= usbdevice4;
+		end
+		3'd5: begin
+			t_array_muxed <= usbdevice5;
+		end
+		3'd6: begin
+			t_array_muxed <= usbdevice6;
+		end
+		3'd7: begin
+			t_array_muxed <= usbdevice7;
+		end
+		4'd8: begin
+			t_array_muxed <= usbdevice8;
+		end
+		4'd9: begin
+			t_array_muxed <= usbdevice9;
+		end
+		4'd10: begin
+			t_array_muxed <= usbdevice10;
+		end
+		4'd11: begin
+			t_array_muxed <= usbdevice11;
+		end
+		4'd12: begin
+			t_array_muxed <= usbdevice12;
+		end
+		4'd13: begin
+			t_array_muxed <= usbdevice13;
+		end
+		4'd14: begin
+			t_array_muxed <= usbdevice14;
+		end
+		default: begin
+			t_array_muxed <= usbdevice15;
+		end
+	endcase
+end
+always @(*) begin
+	basiclowerer_array_muxed <= 1'd0;
+	case (usbdevice_current_endp)
+		1'd0: begin
+			basiclowerer_array_muxed <= usbdevice32;
+		end
+		1'd1: begin
+			basiclowerer_array_muxed <= usbdevice33;
+		end
+		2'd2: begin
+			basiclowerer_array_muxed <= usbdevice34;
+		end
+		2'd3: begin
+			basiclowerer_array_muxed <= usbdevice35;
+		end
+		3'd4: begin
+			basiclowerer_array_muxed <= usbdevice36;
+		end
+		3'd5: begin
+			basiclowerer_array_muxed <= usbdevice37;
+		end
+		3'd6: begin
+			basiclowerer_array_muxed <= usbdevice38;
+		end
+		3'd7: begin
+			basiclowerer_array_muxed <= usbdevice39;
+		end
+		4'd8: begin
+			basiclowerer_array_muxed <= usbdevice40;
+		end
+		4'd9: begin
+			basiclowerer_array_muxed <= usbdevice41;
+		end
+		4'd10: begin
+			basiclowerer_array_muxed <= usbdevice42;
+		end
+		4'd11: begin
+			basiclowerer_array_muxed <= usbdevice43;
+		end
+		4'd12: begin
+			basiclowerer_array_muxed <= usbdevice44;
+		end
+		4'd13: begin
+			basiclowerer_array_muxed <= usbdevice45;
+		end
+		4'd14: begin
+			basiclowerer_array_muxed <= usbdevice46;
+		end
+		default: begin
+			basiclowerer_array_muxed <= usbdevice47;
+		end
+	endcase
+end
+always @(*) begin
+	rhs_array_muxed <= 1'd0;
+	case (usbdevice_current_endp)
+		1'd0: begin
+			rhs_array_muxed <= usbdevice16;
+		end
+		1'd1: begin
+			rhs_array_muxed <= usbdevice17;
+		end
+		2'd2: begin
+			rhs_array_muxed <= usbdevice18;
+		end
+		2'd3: begin
+			rhs_array_muxed <= usbdevice19;
+		end
+		3'd4: begin
+			rhs_array_muxed <= usbdevice20;
+		end
+		3'd5: begin
+			rhs_array_muxed <= usbdevice21;
+		end
+		3'd6: begin
+			rhs_array_muxed <= usbdevice22;
+		end
+		3'd7: begin
+			rhs_array_muxed <= usbdevice23;
+		end
+		4'd8: begin
+			rhs_array_muxed <= usbdevice24;
+		end
+		4'd9: begin
+			rhs_array_muxed <= usbdevice25;
+		end
+		4'd10: begin
+			rhs_array_muxed <= usbdevice26;
+		end
+		4'd11: begin
+			rhs_array_muxed <= usbdevice27;
+		end
+		4'd12: begin
+			rhs_array_muxed <= usbdevice28;
+		end
+		4'd13: begin
+			rhs_array_muxed <= usbdevice29;
+		end
+		4'd14: begin
+			rhs_array_muxed <= usbdevice30;
+		end
+		default: begin
+			rhs_array_muxed <= usbdevice31;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed0 <= 30'd0;
+	case (grant)
+		default: begin
+			array_muxed0 <= uartwishbonebridge_wishbone_adr;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed1 <= 32'd0;
+	case (grant)
+		default: begin
+			array_muxed1 <= uartwishbonebridge_wishbone_dat_w;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed2 <= 4'd0;
+	case (grant)
+		default: begin
+			array_muxed2 <= uartwishbonebridge_wishbone_sel;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed3 <= 1'd0;
+	case (grant)
+		default: begin
+			array_muxed3 <= uartwishbonebridge_wishbone_cyc;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed4 <= 1'd0;
+	case (grant)
+		default: begin
+			array_muxed4 <= uartwishbonebridge_wishbone_stb;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed5 <= 1'd0;
+	case (grant)
+		default: begin
+			array_muxed5 <= uartwishbonebridge_wishbone_we;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed6 <= 3'd0;
+	case (grant)
+		default: begin
+			array_muxed6 <= uartwishbonebridge_wishbone_cti;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed7 <= 2'd0;
+	case (grant)
+		default: begin
+			array_muxed7 <= uartwishbonebridge_wishbone_bte;
+		end
+	endcase
+end
+assign uartwishbonebridge_rx = multiregimpl0_regs1;
+assign usbdevice_usbfsrx_usbp = multiregimpl1_regs2;
+assign usbdevice_usbfsrx_usbn = multiregimpl2_regs2;
+assign io_status = multiregimpl3_regs1;
+assign mux_value = multiregimpl4_regs1;
+assign trigger_enable = multiregimpl5_regs1;
+assign trigger_done_status = multiregimpl6_regs1;
+assign trigger_mem_produce_rdomain = multiregimpl7_regs1;
+assign trigger_mem_consume_wdomain = multiregimpl8_regs1;
+assign subsampler_value = multiregimpl9_regs1;
+assign storage_enable = multiregimpl10_regs1;
+assign storage_length = multiregimpl11_regs1;
+assign storage_offset = multiregimpl12_regs1;
+assign storage_done_status = multiregimpl13_regs1;
+assign storage_cdc_produce_rdomain = multiregimpl14_regs1;
+assign storage_cdc_consume_wdomain = multiregimpl15_regs1;
+
+always @(posedge por_clk) begin
+	if ((usbtestsoc_crg_reset_delay != 1'd0)) begin
+		usbtestsoc_crg_reset_delay <= (usbtestsoc_crg_reset_delay - 1'd1);
+	end
+	if (por_rst) begin
+		usbtestsoc_crg_reset_delay <= 12'd4095;
+	end
+end
+
+always @(posedge scope_clk) begin
+	trigger_enable_d <= trigger_enable;
+	trigger_mem_graycounter1_q_binary <= trigger_mem_graycounter1_q_next_binary;
+	trigger_mem_graycounter1_q <= trigger_mem_graycounter1_q_next;
+	if (subsampler_source_ready) begin
+		if (subsampler_done) begin
+			subsampler_counter <= 1'd0;
+		end else begin
+			if (subsampler_sink_valid) begin
+				subsampler_counter <= (subsampler_counter + 1'd1);
+			end
+		end
+	end
+	storage_enable_d <= storage_enable;
+	if (storage_mem_syncfifo_re) begin
+		storage_mem_readable <= 1'd1;
+	end else begin
+		if (storage_mem_re) begin
+			storage_mem_readable <= 1'd0;
+		end
+	end
+	if (((storage_mem_syncfifo_we & storage_mem_syncfifo_writable) & (~storage_mem_replace))) begin
+		storage_mem_produce <= (storage_mem_produce + 1'd1);
+	end
+	if (storage_mem_do_read) begin
+		storage_mem_consume <= (storage_mem_consume + 1'd1);
+	end
+	if (((storage_mem_syncfifo_we & storage_mem_syncfifo_writable) & (~storage_mem_replace))) begin
+		if ((~storage_mem_do_read)) begin
+			storage_mem_level0 <= (storage_mem_level0 + 1'd1);
+		end
+	end else begin
+		if (storage_mem_do_read) begin
+			storage_mem_level0 <= (storage_mem_level0 - 1'd1);
+		end
+	end
+	storage_cdc_graycounter0_q_binary <= storage_cdc_graycounter0_q_next_binary;
+	storage_cdc_graycounter0_q <= storage_cdc_graycounter0_q_next;
+	if (storage_wait) begin
+		if ((~storage_done1)) begin
+			storage_count <= (storage_count - 1'd1);
+		end
+	end else begin
+		storage_count <= 9'd256;
+	end
+	litescopeanalyzer_state <= litescopeanalyzer_next_state;
+	if (scope_rst) begin
+		trigger_enable_d <= 1'd0;
+		trigger_mem_graycounter1_q <= 5'd0;
+		trigger_mem_graycounter1_q_binary <= 5'd0;
+		subsampler_counter <= 16'd0;
+		storage_enable_d <= 1'd0;
+		storage_mem_readable <= 1'd0;
+		storage_mem_level0 <= 9'd0;
+		storage_mem_produce <= 8'd0;
+		storage_mem_consume <= 8'd0;
+		storage_cdc_graycounter0_q <= 3'd0;
+		storage_cdc_graycounter0_q_binary <= 3'd0;
+		storage_count <= 9'd256;
+		litescopeanalyzer_state <= 2'd0;
+	end
+	multiregimpl4_regs0 <= mux_value_storage;
+	multiregimpl4_regs1 <= multiregimpl4_regs0;
+	multiregimpl5_regs0 <= trigger_enable_storage;
+	multiregimpl5_regs1 <= multiregimpl5_regs0;
+	multiregimpl7_regs0 <= trigger_mem_graycounter0_q;
+	multiregimpl7_regs1 <= multiregimpl7_regs0;
+	multiregimpl9_regs0 <= subsampler_value_storage;
+	multiregimpl9_regs1 <= multiregimpl9_regs0;
+	multiregimpl10_regs0 <= storage_enable_storage;
+	multiregimpl10_regs1 <= multiregimpl10_regs0;
+	multiregimpl11_regs0 <= storage_length_storage;
+	multiregimpl11_regs1 <= multiregimpl11_regs0;
+	multiregimpl12_regs0 <= storage_offset_storage;
+	multiregimpl12_regs1 <= multiregimpl12_regs0;
+	multiregimpl15_regs0 <= storage_cdc_graycounter1_q;
+	multiregimpl15_regs1 <= multiregimpl15_regs0;
+end
+
+always @(posedge sys_clk) begin
+	if ((usbtestsoc_usbtestsoc_bus_errors != 32'd4294967295)) begin
+		if (usbtestsoc_usbtestsoc_bus_error) begin
+			usbtestsoc_usbtestsoc_bus_errors <= (usbtestsoc_usbtestsoc_bus_errors + 1'd1);
+		end
+	end
+	usbtestsoc_usbtestsoc_we <= 1'd0;
+	usbtestsoc_usbtestsoc_dat_w <= usbtestsoc_usbtestsoc_bus_wishbone_dat_w;
+	usbtestsoc_usbtestsoc_adr <= usbtestsoc_usbtestsoc_bus_wishbone_adr;
+	usbtestsoc_usbtestsoc_bus_wishbone_dat_r <= usbtestsoc_usbtestsoc_dat_r;
+	if ((usbtestsoc_usbtestsoc_counter == 1'd1)) begin
+		usbtestsoc_usbtestsoc_we <= usbtestsoc_usbtestsoc_bus_wishbone_we;
+	end
+	if ((usbtestsoc_usbtestsoc_counter == 2'd2)) begin
+		usbtestsoc_usbtestsoc_bus_wishbone_ack <= 1'd1;
+	end
+	if ((usbtestsoc_usbtestsoc_counter == 2'd3)) begin
+		usbtestsoc_usbtestsoc_bus_wishbone_ack <= 1'd0;
+	end
+	if ((usbtestsoc_usbtestsoc_counter != 1'd0)) begin
+		usbtestsoc_usbtestsoc_counter <= (usbtestsoc_usbtestsoc_counter + 1'd1);
+	end else begin
+		if ((usbtestsoc_usbtestsoc_bus_wishbone_cyc & usbtestsoc_usbtestsoc_bus_wishbone_stb)) begin
+			usbtestsoc_usbtestsoc_counter <= 1'd1;
+		end
+	end
+	if (usbtestsoc_usbtestsoc_en_storage) begin
+		if ((usbtestsoc_usbtestsoc_value == 1'd0)) begin
+			usbtestsoc_usbtestsoc_value <= usbtestsoc_usbtestsoc_reload_storage;
+		end else begin
+			usbtestsoc_usbtestsoc_value <= (usbtestsoc_usbtestsoc_value - 1'd1);
+		end
+	end else begin
+		usbtestsoc_usbtestsoc_value <= usbtestsoc_usbtestsoc_load_storage;
+	end
+	if (usbtestsoc_usbtestsoc_update_value_re) begin
+		usbtestsoc_usbtestsoc_value_status <= usbtestsoc_usbtestsoc_value;
+	end
+	if (usbtestsoc_usbtestsoc_zero_clear) begin
+		usbtestsoc_usbtestsoc_zero_pending <= 1'd0;
+	end
+	usbtestsoc_usbtestsoc_zero_old_trigger <= usbtestsoc_usbtestsoc_zero_trigger;
+	if (((~usbtestsoc_usbtestsoc_zero_trigger) & usbtestsoc_usbtestsoc_zero_old_trigger)) begin
+		usbtestsoc_usbtestsoc_zero_pending <= 1'd1;
+	end
+	if ((usbtestsoc_spiflash_i == 1'd0)) begin
+		usbtestsoc_spiflash_clk1 <= 1'd1;
+		usbtestsoc_spiflash_miso1 <= spiflash_miso;
+	end
+	if ((usbtestsoc_spiflash_i == 1'd1)) begin
+		usbtestsoc_spiflash_i <= 1'd0;
+		usbtestsoc_spiflash_clk1 <= 1'd0;
+		usbtestsoc_spiflash_sr <= {usbtestsoc_spiflash_sr[30:0], usbtestsoc_spiflash_miso1};
+	end else begin
+		usbtestsoc_spiflash_i <= (usbtestsoc_spiflash_i + 1'd1);
+	end
+	if ((((usbtestsoc_spiflash_bus_cyc & usbtestsoc_spiflash_bus_stb) & (usbtestsoc_spiflash_i == 1'd1)) & (usbtestsoc_spiflash_counter == 1'd0))) begin
+		usbtestsoc_spiflash_cs_n1 <= 1'd0;
+		usbtestsoc_spiflash_sr[31:24] <= 4'd11;
+	end
+	if ((usbtestsoc_spiflash_counter == 5'd16)) begin
+		usbtestsoc_spiflash_sr[31:8] <= {usbtestsoc_spiflash_bus_adr, {2{1'd0}}};
+	end
+	if ((usbtestsoc_spiflash_counter == 7'd64)) begin
+	end
+	if ((usbtestsoc_spiflash_counter == 8'd144)) begin
+		usbtestsoc_spiflash_bus_ack <= 1'd1;
+		usbtestsoc_spiflash_cs_n1 <= 1'd1;
+	end
+	if ((usbtestsoc_spiflash_counter == 8'd145)) begin
+		usbtestsoc_spiflash_bus_ack <= 1'd0;
+	end
+	if ((usbtestsoc_spiflash_counter == 8'd147)) begin
+	end
+	if ((usbtestsoc_spiflash_counter == 8'd147)) begin
+		usbtestsoc_spiflash_counter <= 1'd0;
+	end else begin
+		if ((usbtestsoc_spiflash_counter != 1'd0)) begin
+			usbtestsoc_spiflash_counter <= (usbtestsoc_spiflash_counter + 1'd1);
+		end else begin
+			if (((usbtestsoc_spiflash_bus_cyc & usbtestsoc_spiflash_bus_stb) & (usbtestsoc_spiflash_i == 1'd1))) begin
+				usbtestsoc_spiflash_counter <= 1'd1;
+			end
+		end
+	end
+	if (uartwishbonebridge_byte_counter_reset) begin
+		uartwishbonebridge_byte_counter <= 1'd0;
+	end else begin
+		if (uartwishbonebridge_byte_counter_ce) begin
+			uartwishbonebridge_byte_counter <= (uartwishbonebridge_byte_counter + 1'd1);
+		end
+	end
+	if (uartwishbonebridge_word_counter_reset) begin
+		uartwishbonebridge_word_counter <= 1'd0;
+	end else begin
+		if (uartwishbonebridge_word_counter_ce) begin
+			uartwishbonebridge_word_counter <= (uartwishbonebridge_word_counter + 1'd1);
+		end
+	end
+	if (uartwishbonebridge_cmd_ce) begin
+		uartwishbonebridge_cmd <= uartwishbonebridge_source_payload_data;
+	end
+	if (uartwishbonebridge_length_ce) begin
+		uartwishbonebridge_length <= uartwishbonebridge_source_payload_data;
+	end
+	if (uartwishbonebridge_address_ce) begin
+		uartwishbonebridge_address <= {uartwishbonebridge_address[23:0], uartwishbonebridge_source_payload_data};
+	end
+	if (uartwishbonebridge_rx_data_ce) begin
+		uartwishbonebridge_data <= {uartwishbonebridge_data[23:0], uartwishbonebridge_source_payload_data};
+	end else begin
+		if (uartwishbonebridge_tx_data_ce) begin
+			uartwishbonebridge_data <= uartwishbonebridge_wishbone_dat_r;
+		end
+	end
+	uartwishbonebridge_sink_ready <= 1'd0;
+	if (((uartwishbonebridge_sink_valid & (~uartwishbonebridge_tx_busy)) & (~uartwishbonebridge_sink_ready))) begin
+		uartwishbonebridge_tx_reg <= uartwishbonebridge_sink_payload_data;
+		uartwishbonebridge_tx_bitcount <= 1'd0;
+		uartwishbonebridge_tx_busy <= 1'd1;
+		serial_tx <= 1'd0;
+	end else begin
+		if ((uartwishbonebridge_uart_clk_txen & uartwishbonebridge_tx_busy)) begin
+			uartwishbonebridge_tx_bitcount <= (uartwishbonebridge_tx_bitcount + 1'd1);
+			if ((uartwishbonebridge_tx_bitcount == 4'd8)) begin
+				serial_tx <= 1'd1;
+			end else begin
+				if ((uartwishbonebridge_tx_bitcount == 4'd9)) begin
+					serial_tx <= 1'd1;
+					uartwishbonebridge_tx_busy <= 1'd0;
+					uartwishbonebridge_sink_ready <= 1'd1;
+				end else begin
+					serial_tx <= uartwishbonebridge_tx_reg[0];
+					uartwishbonebridge_tx_reg <= {1'd0, uartwishbonebridge_tx_reg[7:1]};
+				end
+			end
+		end
+	end
+	if (uartwishbonebridge_tx_busy) begin
+		{uartwishbonebridge_uart_clk_txen, uartwishbonebridge_phase_accumulator_tx} <= (uartwishbonebridge_phase_accumulator_tx + uartwishbonebridge_storage);
+	end else begin
+		{uartwishbonebridge_uart_clk_txen, uartwishbonebridge_phase_accumulator_tx} <= 1'd0;
+	end
+	uartwishbonebridge_source_valid <= 1'd0;
+	uartwishbonebridge_rx_r <= uartwishbonebridge_rx;
+	if ((~uartwishbonebridge_rx_busy)) begin
+		if (((~uartwishbonebridge_rx) & uartwishbonebridge_rx_r)) begin
+			uartwishbonebridge_rx_busy <= 1'd1;
+			uartwishbonebridge_rx_bitcount <= 1'd0;
+		end
+	end else begin
+		if (uartwishbonebridge_uart_clk_rxen) begin
+			uartwishbonebridge_rx_bitcount <= (uartwishbonebridge_rx_bitcount + 1'd1);
+			if ((uartwishbonebridge_rx_bitcount == 1'd0)) begin
+				if (uartwishbonebridge_rx) begin
+					uartwishbonebridge_rx_busy <= 1'd0;
+				end
+			end else begin
+				if ((uartwishbonebridge_rx_bitcount == 4'd9)) begin
+					uartwishbonebridge_rx_busy <= 1'd0;
+					if (uartwishbonebridge_rx) begin
+						uartwishbonebridge_source_payload_data <= uartwishbonebridge_rx_reg;
+						uartwishbonebridge_source_valid <= 1'd1;
+					end
+				end else begin
+					uartwishbonebridge_rx_reg <= {uartwishbonebridge_rx, uartwishbonebridge_rx_reg[7:1]};
+				end
+			end
+		end
+	end
+	if (uartwishbonebridge_rx_busy) begin
+		{uartwishbonebridge_uart_clk_rxen, uartwishbonebridge_phase_accumulator_rx} <= (uartwishbonebridge_phase_accumulator_rx + uartwishbonebridge_storage);
+	end else begin
+		{uartwishbonebridge_uart_clk_rxen, uartwishbonebridge_phase_accumulator_rx} <= 32'd2147483648;
+	end
+	uartwishbonebridge_state <= uartwishbonebridge_next_state;
+	if (uartwishbonebridge_reset) begin
+		uartwishbonebridge_state <= 3'd0;
+	end
+	if (uartwishbonebridge_wait) begin
+		if ((~uartwishbonebridge_done)) begin
+			uartwishbonebridge_count <= (uartwishbonebridge_count - 1'd1);
+		end
+	end else begin
+		uartwishbonebridge_count <= 21'd1600000;
+	end
+	usbdevice_tx_pkt_start <= (usbdevice_in_tx_pkt_start | usbdevice_out_tx_pkt_start);
+	usbdevice_tx_pid <= (usbdevice_out_tx_pkt_start ? usbdevice_out_tx_pid : usbdevice_in_tx_pid);
+	usbdevice_valid_request_token <= usbdevice_valid_request_token_pre;
+	if (usbdevice_valid_request_token) begin
+		usbdevice_current_token <= usbdevice_usbfsrx_o_pkt_pid;
+		usbdevice_current_endp <= usbdevice_rx_endp;
+	end
+	usbdevice_usbfsrx_line_state_valid <= (usbdevice_usbfsrx_line_state_phase == 1'd1);
+	if (usbdevice_usbfsrx_line_state_dt) begin
+		usbdevice_usbfsrx_line_state_phase <= 1'd0;
+		usbdevice_usbfsrx_line_state_valid <= 1'd0;
+	end else begin
+		usbdevice_usbfsrx_line_state_phase <= (usbdevice_usbfsrx_line_state_phase + 1'd1);
+	end
+	usbdevice_usbfsrx_line_state_dj1 <= usbdevice_usbfsrx_line_state_dj0;
+	usbdevice_usbfsrx_line_state_dk1 <= usbdevice_usbfsrx_line_state_dk0;
+	usbdevice_usbfsrx_line_state_se01 <= usbdevice_usbfsrx_line_state_se00;
+	usbdevice_usbfsrx_line_state_se11 <= usbdevice_usbfsrx_line_state_se10;
+	rxclockdatarecovery_state <= rxclockdatarecovery_next_state;
+	usbdevice_usbfsrx_nrzi_o_se0 <= usbdevice_usbfsrx_line_state_se01;
+	usbdevice_usbfsrx_nrzi_o_valid1 <= usbdevice_usbfsrx_nrzi_o_valid0;
+	usbdevice_usbfsrx_nrzi_o_data1 <= usbdevice_usbfsrx_nrzi_o_data0;
+	rxnrzidecoder_state <= rxnrzidecoder_next_state;
+	usbdevice_usbfsrx_bitstuff_o_se0 <= usbdevice_usbfsrx_nrzi_o_se0;
+	usbdevice_usbfsrx_bitstuff_o_valid <= (usbdevice_usbfsrx_nrzi_o_valid1 & (~usbdevice_usbfsrx_bitstuff_drop_bit));
+	usbdevice_usbfsrx_bitstuff_o_data <= usbdevice_usbfsrx_nrzi_o_data1;
+	usbdevice_usbfsrx_bitstuff_o_bitstuff_error <= (usbdevice_usbfsrx_bitstuff_drop_bit & usbdevice_usbfsrx_nrzi_o_data1);
+	rxbitstuffremover_state <= rxbitstuffremover_next_state;
+	usbdevice_usbfsrx_valid <= usbdevice_usbfsrx_bitstuff_o_valid;
+	usbdevice_usbfsrx_data <= usbdevice_usbfsrx_bitstuff_o_data;
+	usbdevice_usbfsrx_se0 <= usbdevice_usbfsrx_bitstuff_o_se0;
+	usbdevice_usbfsrx_bitstuff_error <= usbdevice_usbfsrx_bitstuff_o_bitstuff_error;
+	usbdevice_usbfsrx_pkt_active1 <= usbdevice_usbfsrx_o_pkt_active;
+	usbdevice_usbfsrx_pkt_end1 <= usbdevice_usbfsrx_o_pkt_end0;
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_pkt_bitstuff_good <= 1'd1;
+	end else begin
+		if ((usbdevice_usbfsrx_pkt_active1 & usbdevice_usbfsrx_bitstuff_error)) begin
+			usbdevice_usbfsrx_pkt_bitstuff_good <= 1'd0;
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_data_put) begin
+		usbdevice_usbfsrx_crc16_good <= usbdevice_usbfsrx_data_crc16_o_crc_good;
+	end
+	usbdevice_usbfsrx_o_pkt_start1 <= usbdevice_usbfsrx_o_pkt_start0;
+	usbdevice_usbfsrx_o_pkt_pid <= usbdevice_usbfsrx_pid_shifter_o_output[3:0];
+	usbdevice_usbfsrx_o_pkt_token_payload <= usbdevice_usbfsrx_tok_shifter_o_output[10:0];
+	usbdevice_usbfsrx_o_pkt_data <= usbdevice_usbfsrx_data_shifter_o_output[7:0];
+	usbdevice_usbfsrx_o_pkt_data_put <= usbdevice_usbfsrx_data_put;
+	usbdevice_usbfsrx_o_pkt_good <= ((((usbdevice_usbfsrx_pid_shifter_o_output[3:0] == (usbdevice_usbfsrx_pid_shifter_o_output[7:4] ^ 4'd15)) & usbdevice_usbfsrx_pkt_bitstuff_good) & (usbdevice_usbfsrx_tok_crc5_o_crc_good | (~(usbdevice_usbfsrx_pid_shifter_o_output[1:0] == 1'd1)))) & (usbdevice_usbfsrx_crc16_good | (~(usbdevice_usbfsrx_pid_shifter_o_output[1:0] == 2'd3))));
+	usbdevice_usbfsrx_o_pkt_end1 <= usbdevice_usbfsrx_pkt_end1;
+	usbdevice_usbfsrx_o_pkt_start0 <= usbdevice_usbfsrx_pkt_start;
+	usbdevice_usbfsrx_o_pkt_active <= usbdevice_usbfsrx_pkt_active0;
+	usbdevice_usbfsrx_o_pkt_end0 <= usbdevice_usbfsrx_pkt_end0;
+	rxpacketdecode_state <= rxpacketdecode_next_state;
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_pid_shifter_shift_reg <= 9'd256;
+	end else begin
+		if (((usbdevice_usbfsrx_pkt_active1 & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_pid_shifter_o_full))) begin
+			usbdevice_usbfsrx_pid_shifter_shift_reg <= {usbdevice_usbfsrx_data, usbdevice_usbfsrx_pid_shifter_shift_reg[8:1]};
+		end
+	end
+	usbdevice_usbfsrx_pid_shifter_o_put <= ((usbdevice_usbfsrx_pid_shifter_shift_reg[1:0] == 2'd2) & (usbdevice_usbfsrx_pkt_active1 & usbdevice_usbfsrx_valid));
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_tok_shifter_shift_reg <= 17'd65536;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_tok_shifter_o_full))) begin
+			usbdevice_usbfsrx_tok_shifter_shift_reg <= {usbdevice_usbfsrx_data, usbdevice_usbfsrx_tok_shifter_shift_reg[16:1]};
+		end
+	end
+	usbdevice_usbfsrx_tok_shifter_o_put <= ((usbdevice_usbfsrx_tok_shifter_shift_reg[1:0] == 2'd2) & (usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid));
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_tok_crc5_crc[0] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_tok_shifter_o_full))) begin
+			usbdevice_usbfsrx_tok_crc5_crc[0] <= usbdevice_usbfsrx_tok_crc5_crc_invert;
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_tok_crc5_crc[1] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_tok_shifter_o_full))) begin
+			usbdevice_usbfsrx_tok_crc5_crc[1] <= usbdevice_usbfsrx_tok_crc5_crc[0];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_tok_crc5_crc[2] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_tok_shifter_o_full))) begin
+			usbdevice_usbfsrx_tok_crc5_crc[2] <= (usbdevice_usbfsrx_tok_crc5_crc[1] ^ usbdevice_usbfsrx_tok_crc5_crc_invert);
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_tok_crc5_crc[3] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_tok_shifter_o_full))) begin
+			usbdevice_usbfsrx_tok_crc5_crc[3] <= usbdevice_usbfsrx_tok_crc5_crc[2];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_tok_crc5_crc[4] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_tok_shifter_o_full))) begin
+			usbdevice_usbfsrx_tok_crc5_crc[4] <= usbdevice_usbfsrx_tok_crc5_crc[3];
+		end
+	end
+	usbdevice_usbfsrx_tok_crc5_o_crc_good <= usbdevice_usbfsrx_tok_crc5_crc_good;
+	if ((usbdevice_usbfsrx_o_pkt_start0 | usbdevice_usbfsrx_data_put)) begin
+		usbdevice_usbfsrx_data_shifter_shift_reg <= 9'd256;
+	end else begin
+		if (((((usbdevice_usbfsrx_pid_shifter_o_output[1:0] == 2'd3) & usbdevice_usbfsrx_pid_shifter_o_full) & usbdevice_usbfsrx_valid) & (~usbdevice_usbfsrx_data_shifter_o_full))) begin
+			usbdevice_usbfsrx_data_shifter_shift_reg <= {usbdevice_usbfsrx_data, usbdevice_usbfsrx_data_shifter_shift_reg[8:1]};
+		end
+	end
+	usbdevice_usbfsrx_data_shifter_o_put <= ((usbdevice_usbfsrx_data_shifter_shift_reg[1:0] == 2'd2) & (((usbdevice_usbfsrx_pid_shifter_o_output[1:0] == 2'd3) & usbdevice_usbfsrx_pid_shifter_o_full) & usbdevice_usbfsrx_valid));
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[0] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[0] <= usbdevice_usbfsrx_data_crc16_crc_invert;
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[1] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[1] <= usbdevice_usbfsrx_data_crc16_crc[0];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[2] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[2] <= (usbdevice_usbfsrx_data_crc16_crc[1] ^ usbdevice_usbfsrx_data_crc16_crc_invert);
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[3] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[3] <= usbdevice_usbfsrx_data_crc16_crc[2];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[4] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[4] <= usbdevice_usbfsrx_data_crc16_crc[3];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[5] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[5] <= usbdevice_usbfsrx_data_crc16_crc[4];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[6] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[6] <= usbdevice_usbfsrx_data_crc16_crc[5];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[7] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[7] <= usbdevice_usbfsrx_data_crc16_crc[6];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[8] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[8] <= usbdevice_usbfsrx_data_crc16_crc[7];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[9] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[9] <= usbdevice_usbfsrx_data_crc16_crc[8];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[10] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[10] <= usbdevice_usbfsrx_data_crc16_crc[9];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[11] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[11] <= usbdevice_usbfsrx_data_crc16_crc[10];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[12] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[12] <= usbdevice_usbfsrx_data_crc16_crc[11];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[13] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[13] <= usbdevice_usbfsrx_data_crc16_crc[12];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[14] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[14] <= usbdevice_usbfsrx_data_crc16_crc[13];
+		end
+	end
+	if (usbdevice_usbfsrx_o_pkt_start0) begin
+		usbdevice_usbfsrx_data_crc16_crc[15] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfsrx_pid_shifter_o_full & usbdevice_usbfsrx_valid) & usbdevice_usbfsrx_pkt_active1)) begin
+			usbdevice_usbfsrx_data_crc16_crc[15] <= (usbdevice_usbfsrx_data_crc16_crc[14] ^ usbdevice_usbfsrx_data_crc16_crc_invert);
+		end
+	end
+	usbdevice_usbfsrx_data_crc16_o_crc_good <= usbdevice_usbfsrx_data_crc16_crc_good;
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_pid_is_data <= (usbdevice_tx_pid[1:0] == 2'd3);
+	end
+	usbdevice_usbfstx_mux_stuff_bit_strobe <= usbdevice_usbfsrx_line_state_valid;
+	usbdevice_usbfstx_mux_stuff_oe <= usbdevice_usbfstx_pkt_active;
+	usbdevice_usbfstx_mux_stuff_se0 <= 1'd0;
+	usbdevice_usbfstx_mux_stuff_data <= 1'd0;
+	if (usbdevice_usbfstx_shift_sync) begin
+		usbdevice_usbfstx_mux_stuff_se0 <= 1'd0;
+		usbdevice_usbfstx_mux_stuff_data <= usbdevice_usbfstx_sync_shifter_o_data;
+	end else begin
+		if (usbdevice_usbfstx_shift_pid) begin
+			usbdevice_usbfstx_mux_stuff_se0 <= 1'd0;
+			usbdevice_usbfstx_mux_stuff_data <= usbdevice_usbfstx_pid_shifter_o_data;
+		end else begin
+			if (usbdevice_usbfstx_shift_data) begin
+				usbdevice_usbfstx_mux_stuff_se0 <= 1'd0;
+				usbdevice_usbfstx_mux_stuff_data <= usbdevice_usbfstx_data_shifter_o_data;
+			end else begin
+				if (usbdevice_usbfstx_shift_crc16) begin
+					usbdevice_usbfstx_mux_stuff_se0 <= 1'd0;
+					usbdevice_usbfstx_mux_stuff_data <= usbdevice_usbfstx_crc16_shifter_o_data;
+				end else begin
+					if (usbdevice_usbfstx_shift_eop) begin
+						usbdevice_usbfstx_mux_stuff_se0 <= 1'd1;
+						usbdevice_usbfstx_mux_stuff_data <= 1'd0;
+					end
+				end
+			end
+		end
+	end
+	usbdevice_usbfstx_o_data_get <= usbdevice_usbfstx_load_data;
+	usbdevice_usbfstx_o_usbp <= usbdevice_usbfstx_nrzi_o_usbp;
+	usbdevice_usbfstx_o_usbn <= usbdevice_usbfstx_nrzi_o_usbn;
+	usbdevice_usbfstx_o_oe <= usbdevice_usbfstx_nrzi_o_oe;
+	fsm_state <= fsm_next_state;
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_sync_shifter_shifter <= {1'd1, slice_proxy0[7:0]};
+	end else begin
+		if (((usbdevice_usbfstx_shift_sync & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_sync_shifter_shifter <= (usbdevice_usbfstx_sync_shifter_shifter >>> 1'd1);
+		end
+	end
+	if (((usbdevice_usbfstx_sync_shifter_shifter[8:1] == 8'd1) & ((usbdevice_usbfstx_shift_sync & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall)))) begin
+		usbdevice_usbfstx_sync_shifter_not_empty <= 1'd0;
+	end else begin
+		if (usbdevice_tx_pkt_start) begin
+			usbdevice_usbfstx_sync_shifter_not_empty <= 1'd1;
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_pid_shifter_shifter <= {1'd1, slice_proxy1[7:0]};
+	end else begin
+		if (((usbdevice_usbfstx_shift_pid & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_pid_shifter_shifter <= (usbdevice_usbfstx_pid_shifter_shifter >>> 1'd1);
+		end
+	end
+	if (((usbdevice_usbfstx_pid_shifter_shifter[8:1] == 8'd1) & ((usbdevice_usbfstx_shift_pid & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall)))) begin
+		usbdevice_usbfstx_pid_shifter_not_empty <= 1'd0;
+	end else begin
+		if (usbdevice_tx_pkt_start) begin
+			usbdevice_usbfstx_pid_shifter_not_empty <= 1'd1;
+		end
+	end
+	if (usbdevice_usbfstx_load_data) begin
+		usbdevice_usbfstx_data_shifter_shifter <= {1'd1, usbdevice_tx_data[7:0]};
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_data_shifter_shifter <= (usbdevice_usbfstx_data_shifter_shifter >>> 1'd1);
+		end
+	end
+	if (((usbdevice_usbfstx_data_shifter_shifter[8:1] == 8'd1) & ((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall)))) begin
+		usbdevice_usbfstx_data_shifter_not_empty <= 1'd0;
+	end else begin
+		if (usbdevice_usbfstx_load_data) begin
+			usbdevice_usbfstx_data_shifter_not_empty <= 1'd1;
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[0] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[0] <= usbdevice_usbfstx_crc_invert;
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[1] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[1] <= usbdevice_usbfstx_crc[0];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[2] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[2] <= (usbdevice_usbfstx_crc[1] ^ usbdevice_usbfstx_crc_invert);
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[3] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[3] <= usbdevice_usbfstx_crc[2];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[4] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[4] <= usbdevice_usbfstx_crc[3];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[5] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[5] <= usbdevice_usbfstx_crc[4];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[6] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[6] <= usbdevice_usbfstx_crc[5];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[7] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[7] <= usbdevice_usbfstx_crc[6];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[8] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[8] <= usbdevice_usbfstx_crc[7];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[9] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[9] <= usbdevice_usbfstx_crc[8];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[10] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[10] <= usbdevice_usbfstx_crc[9];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[11] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[11] <= usbdevice_usbfstx_crc[10];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[12] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[12] <= usbdevice_usbfstx_crc[11];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[13] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[13] <= usbdevice_usbfstx_crc[12];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[14] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[14] <= usbdevice_usbfstx_crc[13];
+		end
+	end
+	if (usbdevice_tx_pkt_start) begin
+		usbdevice_usbfstx_crc[15] <= 1'd1;
+	end else begin
+		if (((usbdevice_usbfstx_shift_data & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc[15] <= (usbdevice_usbfstx_crc[14] ^ usbdevice_usbfstx_crc_invert);
+		end
+	end
+	if (usbdevice_usbfstx_load_crc16) begin
+		usbdevice_usbfstx_crc16_shifter_shifter <= {1'd1, usbdevice_usbfstx_o_crc[15:0]};
+	end else begin
+		if (((usbdevice_usbfstx_shift_crc16 & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall))) begin
+			usbdevice_usbfstx_crc16_shifter_shifter <= (usbdevice_usbfstx_crc16_shifter_shifter >>> 1'd1);
+		end
+	end
+	if (((usbdevice_usbfstx_crc16_shifter_shifter[16:1] == 16'd1) & ((usbdevice_usbfstx_shift_crc16 & usbdevice_usbfsrx_line_state_valid) & (~usbdevice_usbfstx_bitstuff_stall)))) begin
+		usbdevice_usbfstx_crc16_shifter_not_empty <= 1'd0;
+	end else begin
+		if (usbdevice_usbfstx_load_crc16) begin
+			usbdevice_usbfstx_crc16_shifter_not_empty <= 1'd1;
+		end
+	end
+	if (usbdevice_usbfstx_mux_stuff_bit_strobe) begin
+		usbdevice_usbfstx_bitstuffer_o_data <= (usbdevice_usbfstx_mux_stuff_data & (~usbdevice_usbfstx_bitstuffer_stuff_bit));
+		usbdevice_usbfstx_bitstuffer_o_se0 <= usbdevice_usbfstx_mux_stuff_se0;
+		usbdevice_usbfstx_bitstuffer_o_oe <= usbdevice_usbfstx_mux_stuff_oe;
+	end
+	txbitstuffer_state <= txbitstuffer_next_state;
+	usbdevice_usbfstx_nrzi_o_oe <= usbdevice_usbfstx_nrzi_oe;
+	usbdevice_usbfstx_nrzi_o_usbp <= usbdevice_usbfstx_nrzi_usbp;
+	usbdevice_usbfstx_nrzi_o_usbn <= usbdevice_usbfstx_nrzi_usbn;
+	txnrziencoder_state <= txnrziencoder_next_state;
+	fsm0_state <= fsm0_next_state;
+	fsm1_state <= fsm1_next_state;
+	trigger_mem_graycounter0_q_binary <= trigger_mem_graycounter0_q_next_binary;
+	trigger_mem_graycounter0_q <= trigger_mem_graycounter0_q_next;
+	if (trigger_wait) begin
+		if ((~trigger_done1)) begin
+			trigger_count <= (trigger_count - 1'd1);
+		end
+	end else begin
+		trigger_count <= 5'd16;
+	end
+	storage_cdc_graycounter1_q_binary <= storage_cdc_graycounter1_q_next_binary;
+	storage_cdc_graycounter1_q <= storage_cdc_graycounter1_q_next;
+	slave_sel_r <= slave_sel;
+	if (wait_1) begin
+		if ((~done)) begin
+			count <= (count - 1'd1);
+		end
+	end else begin
+		count <= 17'd65536;
+	end
+	interface0_bank_bus_dat_r <= 1'd0;
+	if (csrbank0_sel) begin
+		case (interface0_bank_bus_adr[4:0])
+			1'd0: begin
+				interface0_bank_bus_dat_r <= csrbank0_mux_value0_w;
+			end
+			1'd1: begin
+				interface0_bank_bus_dat_r <= csrbank0_trigger_enable0_w;
+			end
+			2'd2: begin
+				interface0_bank_bus_dat_r <= csrbank0_trigger_done_w;
+			end
+			2'd3: begin
+				interface0_bank_bus_dat_r <= trigger_mem_write_w;
+			end
+			3'd4: begin
+				interface0_bank_bus_dat_r <= csrbank0_trigger_mem_mask0_w;
+			end
+			3'd5: begin
+				interface0_bank_bus_dat_r <= csrbank0_trigger_mem_value0_w;
+			end
+			3'd6: begin
+				interface0_bank_bus_dat_r <= csrbank0_trigger_mem_full_w;
+			end
+			3'd7: begin
+				interface0_bank_bus_dat_r <= csrbank0_subsampler_value1_w;
+			end
+			4'd8: begin
+				interface0_bank_bus_dat_r <= csrbank0_subsampler_value0_w;
+			end
+			4'd9: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_enable0_w;
+			end
+			4'd10: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_done_w;
+			end
+			4'd11: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_length1_w;
+			end
+			4'd12: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_length0_w;
+			end
+			4'd13: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_offset1_w;
+			end
+			4'd14: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_offset0_w;
+			end
+			4'd15: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_mem_valid_w;
+			end
+			5'd16: begin
+				interface0_bank_bus_dat_r <= storage_mem_ready_w;
+			end
+			5'd17: begin
+				interface0_bank_bus_dat_r <= csrbank0_storage_mem_data_w;
+			end
+		endcase
+	end
+	if (csrbank0_mux_value0_re) begin
+		mux_value_storage_full <= csrbank0_mux_value0_r;
+	end
+	mux_value_re <= csrbank0_mux_value0_re;
+	if (csrbank0_trigger_enable0_re) begin
+		trigger_enable_storage_full <= csrbank0_trigger_enable0_r;
+	end
+	trigger_enable_re <= csrbank0_trigger_enable0_re;
+	if (csrbank0_trigger_mem_mask0_re) begin
+		trigger_mem_mask_storage_full[1:0] <= csrbank0_trigger_mem_mask0_r;
+	end
+	trigger_mem_mask_re <= csrbank0_trigger_mem_mask0_re;
+	if (csrbank0_trigger_mem_value0_re) begin
+		trigger_mem_value_storage_full[1:0] <= csrbank0_trigger_mem_value0_r;
+	end
+	trigger_mem_value_re <= csrbank0_trigger_mem_value0_re;
+	if (csrbank0_subsampler_value1_re) begin
+		subsampler_value_storage_full[15:8] <= csrbank0_subsampler_value1_r;
+	end
+	if (csrbank0_subsampler_value0_re) begin
+		subsampler_value_storage_full[7:0] <= csrbank0_subsampler_value0_r;
+	end
+	subsampler_value_re <= csrbank0_subsampler_value0_re;
+	if (csrbank0_storage_enable0_re) begin
+		storage_enable_storage_full <= csrbank0_storage_enable0_r;
+	end
+	storage_enable_re <= csrbank0_storage_enable0_re;
+	if (csrbank0_storage_length1_re) begin
+		storage_length_storage_full[8] <= csrbank0_storage_length1_r;
+	end
+	if (csrbank0_storage_length0_re) begin
+		storage_length_storage_full[7:0] <= csrbank0_storage_length0_r;
+	end
+	storage_length_re <= csrbank0_storage_length0_re;
+	if (csrbank0_storage_offset1_re) begin
+		storage_offset_storage_full[8] <= csrbank0_storage_offset1_r;
+	end
+	if (csrbank0_storage_offset0_re) begin
+		storage_offset_storage_full[7:0] <= csrbank0_storage_offset0_r;
+	end
+	storage_offset_re <= csrbank0_storage_offset0_re;
+	interface1_bank_bus_dat_r <= 1'd0;
+	if (csrbank1_sel) begin
+		case (interface1_bank_bus_adr[3:0])
+			1'd0: begin
+				interface1_bank_bus_dat_r <= usbtestsoc_usbtestsoc_reset_reset_w;
+			end
+			1'd1: begin
+				interface1_bank_bus_dat_r <= csrbank1_scratch3_w;
+			end
+			2'd2: begin
+				interface1_bank_bus_dat_r <= csrbank1_scratch2_w;
+			end
+			2'd3: begin
+				interface1_bank_bus_dat_r <= csrbank1_scratch1_w;
+			end
+			3'd4: begin
+				interface1_bank_bus_dat_r <= csrbank1_scratch0_w;
+			end
+			3'd5: begin
+				interface1_bank_bus_dat_r <= csrbank1_bus_errors3_w;
+			end
+			3'd6: begin
+				interface1_bank_bus_dat_r <= csrbank1_bus_errors2_w;
+			end
+			3'd7: begin
+				interface1_bank_bus_dat_r <= csrbank1_bus_errors1_w;
+			end
+			4'd8: begin
+				interface1_bank_bus_dat_r <= csrbank1_bus_errors0_w;
+			end
+		endcase
+	end
+	if (csrbank1_scratch3_re) begin
+		usbtestsoc_usbtestsoc_storage_full[31:24] <= csrbank1_scratch3_r;
+	end
+	if (csrbank1_scratch2_re) begin
+		usbtestsoc_usbtestsoc_storage_full[23:16] <= csrbank1_scratch2_r;
+	end
+	if (csrbank1_scratch1_re) begin
+		usbtestsoc_usbtestsoc_storage_full[15:8] <= csrbank1_scratch1_r;
+	end
+	if (csrbank1_scratch0_re) begin
+		usbtestsoc_usbtestsoc_storage_full[7:0] <= csrbank1_scratch0_r;
+	end
+	usbtestsoc_usbtestsoc_re <= csrbank1_scratch0_re;
+	sel_r <= sel;
+	interface2_bank_bus_dat_r <= 1'd0;
+	if (csrbank2_sel) begin
+		case (interface2_bank_bus_adr[5:0])
+			1'd0: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit19_w;
+			end
+			1'd1: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit18_w;
+			end
+			2'd2: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit17_w;
+			end
+			2'd3: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit16_w;
+			end
+			3'd4: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit15_w;
+			end
+			3'd5: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit14_w;
+			end
+			3'd6: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit13_w;
+			end
+			3'd7: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit12_w;
+			end
+			4'd8: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit11_w;
+			end
+			4'd9: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit10_w;
+			end
+			4'd10: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit9_w;
+			end
+			4'd11: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit8_w;
+			end
+			4'd12: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit7_w;
+			end
+			4'd13: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit6_w;
+			end
+			4'd14: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit5_w;
+			end
+			4'd15: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit4_w;
+			end
+			5'd16: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit3_w;
+			end
+			5'd17: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit2_w;
+			end
+			5'd18: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit1_w;
+			end
+			5'd19: begin
+				interface2_bank_bus_dat_r <= csrbank2_git_commit0_w;
+			end
+			5'd20: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform7_w;
+			end
+			5'd21: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform6_w;
+			end
+			5'd22: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform5_w;
+			end
+			5'd23: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform4_w;
+			end
+			5'd24: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform3_w;
+			end
+			5'd25: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform2_w;
+			end
+			5'd26: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform1_w;
+			end
+			5'd27: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_platform0_w;
+			end
+			5'd28: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target7_w;
+			end
+			5'd29: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target6_w;
+			end
+			5'd30: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target5_w;
+			end
+			5'd31: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target4_w;
+			end
+			6'd32: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target3_w;
+			end
+			6'd33: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target2_w;
+			end
+			6'd34: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target1_w;
+			end
+			6'd35: begin
+				interface2_bank_bus_dat_r <= csrbank2_platform_target0_w;
+			end
+		endcase
+	end
+	interface3_bank_bus_dat_r <= 1'd0;
+	if (csrbank3_sel) begin
+		case (interface3_bank_bus_adr[0])
+			1'd0: begin
+				interface3_bank_bus_dat_r <= csrbank3_in_w;
+			end
+			1'd1: begin
+				interface3_bank_bus_dat_r <= csrbank3_out0_w;
+			end
+		endcase
+	end
+	if (csrbank3_out0_re) begin
+		io_storage_full[7:0] <= csrbank3_out0_r;
+	end
+	io_re <= csrbank3_out0_re;
+	interface4_bank_bus_dat_r <= 1'd0;
+	if (csrbank4_sel) begin
+		case (interface4_bank_bus_adr[1:0])
+			1'd0: begin
+				interface4_bank_bus_dat_r <= csrbank4_bitbang0_w;
+			end
+			1'd1: begin
+				interface4_bank_bus_dat_r <= csrbank4_miso_w;
+			end
+			2'd2: begin
+				interface4_bank_bus_dat_r <= csrbank4_bitbang_en0_w;
+			end
+		endcase
+	end
+	if (csrbank4_bitbang0_re) begin
+		usbtestsoc_spiflash_bitbang_storage_full[3:0] <= csrbank4_bitbang0_r;
+	end
+	usbtestsoc_spiflash_bitbang_re <= csrbank4_bitbang0_re;
+	if (csrbank4_bitbang_en0_re) begin
+		usbtestsoc_spiflash_bitbang_en_storage_full <= csrbank4_bitbang_en0_r;
+	end
+	usbtestsoc_spiflash_bitbang_en_re <= csrbank4_bitbang_en0_re;
+	interface5_bank_bus_dat_r <= 1'd0;
+	if (csrbank5_sel) begin
+		case (interface5_bank_bus_adr[4:0])
+			1'd0: begin
+				interface5_bank_bus_dat_r <= csrbank5_load3_w;
+			end
+			1'd1: begin
+				interface5_bank_bus_dat_r <= csrbank5_load2_w;
+			end
+			2'd2: begin
+				interface5_bank_bus_dat_r <= csrbank5_load1_w;
+			end
+			2'd3: begin
+				interface5_bank_bus_dat_r <= csrbank5_load0_w;
+			end
+			3'd4: begin
+				interface5_bank_bus_dat_r <= csrbank5_reload3_w;
+			end
+			3'd5: begin
+				interface5_bank_bus_dat_r <= csrbank5_reload2_w;
+			end
+			3'd6: begin
+				interface5_bank_bus_dat_r <= csrbank5_reload1_w;
+			end
+			3'd7: begin
+				interface5_bank_bus_dat_r <= csrbank5_reload0_w;
+			end
+			4'd8: begin
+				interface5_bank_bus_dat_r <= csrbank5_en0_w;
+			end
+			4'd9: begin
+				interface5_bank_bus_dat_r <= usbtestsoc_usbtestsoc_update_value_w;
+			end
+			4'd10: begin
+				interface5_bank_bus_dat_r <= csrbank5_value3_w;
+			end
+			4'd11: begin
+				interface5_bank_bus_dat_r <= csrbank5_value2_w;
+			end
+			4'd12: begin
+				interface5_bank_bus_dat_r <= csrbank5_value1_w;
+			end
+			4'd13: begin
+				interface5_bank_bus_dat_r <= csrbank5_value0_w;
+			end
+			4'd14: begin
+				interface5_bank_bus_dat_r <= usbtestsoc_usbtestsoc_eventmanager_status_w;
+			end
+			4'd15: begin
+				interface5_bank_bus_dat_r <= usbtestsoc_usbtestsoc_eventmanager_pending_w;
+			end
+			5'd16: begin
+				interface5_bank_bus_dat_r <= csrbank5_ev_enable0_w;
+			end
+		endcase
+	end
+	if (csrbank5_load3_re) begin
+		usbtestsoc_usbtestsoc_load_storage_full[31:24] <= csrbank5_load3_r;
+	end
+	if (csrbank5_load2_re) begin
+		usbtestsoc_usbtestsoc_load_storage_full[23:16] <= csrbank5_load2_r;
+	end
+	if (csrbank5_load1_re) begin
+		usbtestsoc_usbtestsoc_load_storage_full[15:8] <= csrbank5_load1_r;
+	end
+	if (csrbank5_load0_re) begin
+		usbtestsoc_usbtestsoc_load_storage_full[7:0] <= csrbank5_load0_r;
+	end
+	usbtestsoc_usbtestsoc_load_re <= csrbank5_load0_re;
+	if (csrbank5_reload3_re) begin
+		usbtestsoc_usbtestsoc_reload_storage_full[31:24] <= csrbank5_reload3_r;
+	end
+	if (csrbank5_reload2_re) begin
+		usbtestsoc_usbtestsoc_reload_storage_full[23:16] <= csrbank5_reload2_r;
+	end
+	if (csrbank5_reload1_re) begin
+		usbtestsoc_usbtestsoc_reload_storage_full[15:8] <= csrbank5_reload1_r;
+	end
+	if (csrbank5_reload0_re) begin
+		usbtestsoc_usbtestsoc_reload_storage_full[7:0] <= csrbank5_reload0_r;
+	end
+	usbtestsoc_usbtestsoc_reload_re <= csrbank5_reload0_re;
+	if (csrbank5_en0_re) begin
+		usbtestsoc_usbtestsoc_en_storage_full <= csrbank5_en0_r;
+	end
+	usbtestsoc_usbtestsoc_en_re <= csrbank5_en0_re;
+	if (csrbank5_ev_enable0_re) begin
+		usbtestsoc_usbtestsoc_eventmanager_storage_full <= csrbank5_ev_enable0_r;
+	end
+	usbtestsoc_usbtestsoc_eventmanager_re <= csrbank5_ev_enable0_re;
+	if (sys_rst) begin
+		usbtestsoc_usbtestsoc_storage_full <= 32'd305419896;
+		usbtestsoc_usbtestsoc_re <= 1'd0;
+		usbtestsoc_usbtestsoc_bus_errors <= 32'd0;
+		usbtestsoc_usbtestsoc_adr <= 14'd0;
+		usbtestsoc_usbtestsoc_we <= 1'd0;
+		usbtestsoc_usbtestsoc_dat_w <= 8'd0;
+		usbtestsoc_usbtestsoc_bus_wishbone_dat_r <= 32'd0;
+		usbtestsoc_usbtestsoc_bus_wishbone_ack <= 1'd0;
+		usbtestsoc_usbtestsoc_counter <= 2'd0;
+		usbtestsoc_usbtestsoc_load_storage_full <= 32'd0;
+		usbtestsoc_usbtestsoc_load_re <= 1'd0;
+		usbtestsoc_usbtestsoc_reload_storage_full <= 32'd0;
+		usbtestsoc_usbtestsoc_reload_re <= 1'd0;
+		usbtestsoc_usbtestsoc_en_storage_full <= 1'd0;
+		usbtestsoc_usbtestsoc_en_re <= 1'd0;
+		usbtestsoc_usbtestsoc_value_status <= 32'd0;
+		usbtestsoc_usbtestsoc_zero_pending <= 1'd0;
+		usbtestsoc_usbtestsoc_zero_old_trigger <= 1'd0;
+		usbtestsoc_usbtestsoc_eventmanager_storage_full <= 1'd0;
+		usbtestsoc_usbtestsoc_eventmanager_re <= 1'd0;
+		usbtestsoc_usbtestsoc_value <= 32'd0;
+		usbtestsoc_spiflash_bus_ack <= 1'd0;
+		usbtestsoc_spiflash_bitbang_storage_full <= 4'd0;
+		usbtestsoc_spiflash_bitbang_re <= 1'd0;
+		usbtestsoc_spiflash_bitbang_en_storage_full <= 1'd0;
+		usbtestsoc_spiflash_bitbang_en_re <= 1'd0;
+		usbtestsoc_spiflash_cs_n1 <= 1'd1;
+		usbtestsoc_spiflash_clk1 <= 1'd0;
+		usbtestsoc_spiflash_sr <= 32'd0;
+		usbtestsoc_spiflash_i <= 1'd0;
+		usbtestsoc_spiflash_miso1 <= 1'd0;
+		usbtestsoc_spiflash_counter <= 8'd0;
+		serial_tx <= 1'd1;
+		uartwishbonebridge_sink_ready <= 1'd0;
+		uartwishbonebridge_uart_clk_txen <= 1'd0;
+		uartwishbonebridge_phase_accumulator_tx <= 32'd0;
+		uartwishbonebridge_tx_reg <= 8'd0;
+		uartwishbonebridge_tx_bitcount <= 4'd0;
+		uartwishbonebridge_tx_busy <= 1'd0;
+		uartwishbonebridge_source_valid <= 1'd0;
+		uartwishbonebridge_source_payload_data <= 8'd0;
+		uartwishbonebridge_uart_clk_rxen <= 1'd0;
+		uartwishbonebridge_phase_accumulator_rx <= 32'd0;
+		uartwishbonebridge_rx_r <= 1'd0;
+		uartwishbonebridge_rx_reg <= 8'd0;
+		uartwishbonebridge_rx_bitcount <= 4'd0;
+		uartwishbonebridge_rx_busy <= 1'd0;
+		uartwishbonebridge_count <= 21'd1600000;
+		usbdevice_tx_pkt_start <= 1'd0;
+		usbdevice_tx_pid <= 4'd0;
+		usbdevice_usbfsrx_line_state_phase <= 2'd0;
+		usbdevice_usbfsrx_line_state_valid <= 1'd0;
+		usbdevice_usbfsrx_line_state_dj1 <= 1'd0;
+		usbdevice_usbfsrx_line_state_dk1 <= 1'd0;
+		usbdevice_usbfsrx_line_state_se01 <= 1'd0;
+		usbdevice_usbfsrx_line_state_se11 <= 1'd0;
+		usbdevice_usbfsrx_nrzi_o_valid1 <= 1'd0;
+		usbdevice_usbfsrx_nrzi_o_data1 <= 1'd0;
+		usbdevice_usbfsrx_nrzi_o_se0 <= 1'd0;
+		usbdevice_usbfsrx_bitstuff_o_valid <= 1'd0;
+		usbdevice_usbfsrx_bitstuff_o_data <= 1'd0;
+		usbdevice_usbfsrx_bitstuff_o_se0 <= 1'd0;
+		usbdevice_usbfsrx_bitstuff_o_bitstuff_error <= 1'd0;
+		usbdevice_usbfsrx_valid <= 1'd0;
+		usbdevice_usbfsrx_data <= 1'd0;
+		usbdevice_usbfsrx_se0 <= 1'd0;
+		usbdevice_usbfsrx_bitstuff_error <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_start0 <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_active <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_end0 <= 1'd0;
+		usbdevice_usbfsrx_pkt_active1 <= 1'd0;
+		usbdevice_usbfsrx_pkt_end1 <= 1'd0;
+		usbdevice_usbfsrx_pid_shifter_shift_reg <= 9'd0;
+		usbdevice_usbfsrx_pid_shifter_o_put <= 1'd0;
+		usbdevice_usbfsrx_tok_shifter_shift_reg <= 17'd0;
+		usbdevice_usbfsrx_tok_shifter_o_put <= 1'd0;
+		usbdevice_usbfsrx_tok_crc5_crc <= 5'd0;
+		usbdevice_usbfsrx_tok_crc5_o_crc_good <= 1'd0;
+		usbdevice_usbfsrx_data_shifter_shift_reg <= 9'd0;
+		usbdevice_usbfsrx_data_shifter_o_put <= 1'd0;
+		usbdevice_usbfsrx_data_crc16_crc <= 16'd0;
+		usbdevice_usbfsrx_data_crc16_o_crc_good <= 1'd0;
+		usbdevice_usbfsrx_pkt_bitstuff_good <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_data_put <= 1'd0;
+		usbdevice_usbfsrx_crc16_good <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_start1 <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_pid <= 4'd0;
+		usbdevice_usbfsrx_o_pkt_token_payload <= 11'd0;
+		usbdevice_usbfsrx_o_pkt_data <= 8'd0;
+		usbdevice_usbfsrx_o_pkt_good <= 1'd0;
+		usbdevice_usbfsrx_o_pkt_end1 <= 1'd0;
+		usbdevice_usbfstx_sync_shifter_shifter <= 9'd0;
+		usbdevice_usbfstx_sync_shifter_not_empty <= 1'd0;
+		usbdevice_usbfstx_pid_shifter_shifter <= 9'd0;
+		usbdevice_usbfstx_pid_shifter_not_empty <= 1'd0;
+		usbdevice_usbfstx_data_shifter_shifter <= 9'd0;
+		usbdevice_usbfstx_data_shifter_not_empty <= 1'd0;
+		usbdevice_usbfstx_crc <= 16'd0;
+		usbdevice_usbfstx_crc16_shifter_shifter <= 17'd0;
+		usbdevice_usbfstx_crc16_shifter_not_empty <= 1'd0;
+		usbdevice_usbfstx_pid_is_data <= 1'd0;
+		usbdevice_usbfstx_mux_stuff_oe <= 1'd0;
+		usbdevice_usbfstx_mux_stuff_data <= 1'd0;
+		usbdevice_usbfstx_mux_stuff_se0 <= 1'd0;
+		usbdevice_usbfstx_mux_stuff_bit_strobe <= 1'd0;
+		usbdevice_usbfstx_bitstuffer_o_data <= 1'd0;
+		usbdevice_usbfstx_bitstuffer_o_se0 <= 1'd0;
+		usbdevice_usbfstx_bitstuffer_o_oe <= 1'd0;
+		usbdevice_usbfstx_nrzi_o_usbp <= 1'd0;
+		usbdevice_usbfstx_nrzi_o_usbn <= 1'd0;
+		usbdevice_usbfstx_nrzi_o_oe <= 1'd0;
+		usbdevice_usbfstx_o_data_get <= 1'd0;
+		usbdevice_usbfstx_o_usbp <= 1'd0;
+		usbdevice_usbfstx_o_usbn <= 1'd0;
+		usbdevice_usbfstx_o_oe <= 1'd0;
+		usbdevice_current_token <= 4'd0;
+		usbdevice_current_endp <= 4'd0;
+		usbdevice_valid_request_token <= 1'd0;
+		io_storage_full <= 8'd0;
+		io_re <= 1'd0;
+		mux_value_storage_full <= 1'd0;
+		mux_value_re <= 1'd0;
+		trigger_enable_storage_full <= 1'd0;
+		trigger_enable_re <= 1'd0;
+		trigger_mem_mask_storage_full <= 2'd0;
+		trigger_mem_mask_re <= 1'd0;
+		trigger_mem_value_storage_full <= 2'd0;
+		trigger_mem_value_re <= 1'd0;
+		trigger_mem_graycounter0_q <= 5'd0;
+		trigger_mem_graycounter0_q_binary <= 5'd0;
+		trigger_count <= 5'd16;
+		subsampler_value_storage_full <= 16'd0;
+		subsampler_value_re <= 1'd0;
+		storage_enable_storage_full <= 1'd0;
+		storage_enable_re <= 1'd0;
+		storage_length_storage_full <= 9'd0;
+		storage_length_re <= 1'd0;
+		storage_offset_storage_full <= 9'd0;
+		storage_offset_re <= 1'd0;
+		storage_cdc_graycounter1_q <= 3'd0;
+		storage_cdc_graycounter1_q_binary <= 3'd0;
+		uartwishbonebridge_state <= 3'd0;
+		rxclockdatarecovery_state <= 3'd0;
+		rxnrzidecoder_state <= 1'd0;
+		rxbitstuffremover_state <= 3'd0;
+		rxpacketdecode_state <= 3'd0;
+		fsm_state <= 3'd0;
+		txbitstuffer_state <= 3'd0;
+		txnrziencoder_state <= 3'd0;
+		fsm0_state <= 3'd0;
+		fsm1_state <= 3'd0;
+		slave_sel_r <= 2'd0;
+		count <= 17'd65536;
+		interface0_bank_bus_dat_r <= 8'd0;
+		interface1_bank_bus_dat_r <= 8'd0;
+		sel_r <= 1'd0;
+		interface2_bank_bus_dat_r <= 8'd0;
+		interface3_bank_bus_dat_r <= 8'd0;
+		interface4_bank_bus_dat_r <= 8'd0;
+		interface5_bank_bus_dat_r <= 8'd0;
+	end
+	multiregimpl0_regs0 <= serial_rx;
+	multiregimpl0_regs1 <= multiregimpl0_regs0;
+	multiregimpl1_regs0 <= usbdevice_usb_p_rx;
+	multiregimpl1_regs1 <= multiregimpl1_regs0;
+	multiregimpl1_regs2 <= multiregimpl1_regs1;
+	multiregimpl2_regs0 <= usbdevice_usb_n_rx;
+	multiregimpl2_regs1 <= multiregimpl2_regs0;
+	multiregimpl2_regs2 <= multiregimpl2_regs1;
+	multiregimpl3_regs0 <= io_input;
+	multiregimpl3_regs1 <= multiregimpl3_regs0;
+	multiregimpl6_regs0 <= trigger_done0;
+	multiregimpl6_regs1 <= multiregimpl6_regs0;
+	multiregimpl8_regs0 <= trigger_mem_graycounter1_q;
+	multiregimpl8_regs1 <= multiregimpl8_regs0;
+	multiregimpl13_regs0 <= storage_done0;
+	multiregimpl13_regs1 <= multiregimpl13_regs0;
+	multiregimpl14_regs0 <= storage_cdc_graycounter0_q;
+	multiregimpl14_regs1 <= multiregimpl14_regs0;
+end
+
+reg [7:0] mem[0:10];
+reg [3:0] memadr;
+always @(posedge sys_clk) begin
+	memadr <= adr;
+end
+
+assign dat_r = mem[memadr];
+
+initial begin
+	$readmemh("mem.init", mem);
+end
+
+SB_PLL40_CORE #(
+	.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+	.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+	.DIVF(6'd47),
+	.DIVQ(3'd4),
+	.DIVR(1'd0),
+	.ENABLE_ICEGATE(1'd0),
+	.FDA_FEEDBACK(1'd0),
+	.FDA_RELATIVE(1'd0),
+	.FEEDBACK_PATH("SIMPLE"),
+	.FILTER_RANGE(1'd1),
+	.PLLOUT_SELECT("GENCLK"),
+	.SHIFTREG_DIV_MODE(1'd0)
+) SB_PLL40_CORE (
+	.BYPASS(1'd0),
+	.REFERENCECLK(clk16),
+	.RESETB(1'd1),
+	.PLLOUTCORE(usb_48_clk)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'b101001),
+	.PULLUP(1'd0)
+) SB_IO (
+	.D_OUT_0(usbdevice_usb_p_tx),
+	.OUTPUT_ENABLE(usbdevice_usb_tx_en),
+	.PACKAGE_PIN(usb_d_p),
+	.D_IN_0(usbdevice_usb_p_rx_io)
+);
+
+SB_IO #(
+	.PIN_TYPE(6'b101001),
+	.PULLUP(1'd0)
+) SB_IO_1 (
+	.D_OUT_0(usbdevice_usb_n_tx),
+	.OUTPUT_ENABLE(usbdevice_usb_tx_en),
+	.PACKAGE_PIN(usb_d_n),
+	.D_IN_0(usbdevice_usb_n_rx_io)
+);
+
+reg [5:0] storage[0:15];
+reg [3:0] memadr_1;
+reg [3:0] memadr_2;
+always @(posedge sys_clk) begin
+	if (trigger_mem_wrport_we)
+		storage[trigger_mem_wrport_adr] <= trigger_mem_wrport_dat_w;
+	memadr_1 <= trigger_mem_wrport_adr;
+end
+
+always @(posedge scope_clk) begin
+	memadr_2 <= trigger_mem_rdport_adr;
+end
+
+assign trigger_mem_wrport_dat_r = storage[memadr_1];
+assign trigger_mem_rdport_dat_r = storage[memadr_2];
+
+reg [3:0] storage_1[0:255];
+reg [3:0] memdat;
+reg [3:0] memdat_1;
+always @(posedge scope_clk) begin
+	if (storage_mem_wrport_we)
+		storage_1[storage_mem_wrport_adr] <= storage_mem_wrport_dat_w;
+	memdat <= storage_1[storage_mem_wrport_adr];
+end
+
+always @(posedge scope_clk) begin
+	if (storage_mem_rdport_re)
+		memdat_1 <= storage_1[storage_mem_rdport_adr];
+end
+
+assign storage_mem_wrport_dat_r = memdat;
+assign storage_mem_rdport_dat_r = memdat_1;
+
+reg [3:0] storage_2[0:3];
+reg [1:0] memadr_3;
+reg [1:0] memadr_4;
+always @(posedge scope_clk) begin
+	if (storage_cdc_wrport_we)
+		storage_2[storage_cdc_wrport_adr] <= storage_cdc_wrport_dat_w;
+	memadr_3 <= storage_cdc_wrport_adr;
+end
+
+always @(posedge sys_clk) begin
+	memadr_4 <= storage_cdc_rdport_adr;
+end
+
+assign storage_cdc_wrport_dat_r = storage_2[memadr_3];
+assign storage_cdc_rdport_dat_r = storage_2[memadr_4];
+
+SB_DFFS SB_DFFS(
+	.C(por_clk),
+	.D(1'd0),
+	.S(usbtestsoc_crg_reset),
+	.Q(rst1)
+);
+
+SB_DFFS SB_DFFS_1(
+	.C(por_clk),
+	.D(rst1),
+	.S(usbtestsoc_crg_reset),
+	.Q(por_rst)
+);
+
+endmodule
diff --git a/ice40/regressions/issue0120/top.ys b/ice40/regressions/issue0120/top.ys
new file mode 100644
index 0000000..b22a82d
--- /dev/null
+++ b/ice40/regressions/issue0120/top.ys
@@ -0,0 +1,3 @@
+read_verilog top.v
+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
+synth_ice40 -top top -json top.json
\ No newline at end of file
diff --git a/ice40/regressions/issue0121/serv_0.json b/ice40/regressions/issue0121/serv_0.json
new file mode 100644
index 0000000..5e9a4d1
--- /dev/null
+++ b/ice40/regressions/issue0121/serv_0.json
@@ -0,0 +1,48290 @@
+{
+  "creator": "Yosys 0.8+17 (git sha1 11c8a9eb, gcc 7.3.0-r3 -fPIC -Os)",
+  "modules": {
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+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:648"
+      },
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+        "I0": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "I1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I2": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "I3": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "CIN": {
+          "direction": "input",
+          "bits": [ 6 ]
+        },
+        "CLK": {
+          "direction": "input",
+          "bits": [ 7 ]
+        },
+        "CEN": {
+          "direction": "input",
+          "bits": [ 8 ]
+        },
+        "SR": {
+          "direction": "input",
+          "bits": [ 9 ]
+        },
+        "LO": {
+          "direction": "output",
+          "bits": [ 10 ]
+        },
+        "O": {
+          "direction": "output",
+          "bits": [ 11 ]
+        },
+        "COUT": {
+          "direction": "output",
+          "bits": [ 12 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "CEN": {
+          "hide_name": 0,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "CIN": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "CLK": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        },
+        "COUT": {
+          "hide_name": 0,
+          "bits": [ 12 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:650"
+          }
+        },
+        "I0": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
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+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
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+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
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+        },
+        "I3": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
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+          "hide_name": 0,
+          "bits": [ 10 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:650"
+          }
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+          "bits": [ 11 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:650"
+          }
+        },
+        "SR": {
+          "hide_name": 0,
+          "bits": [ 9 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:649"
+          }
+        }
+      }
+    },
+    "SB_CARRY": {
+      "attributes": {
+        "blackbox": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:129"
+      },
+      "ports": {
+        "CO": {
+          "direction": "output",
+          "bits": [ 2 ]
+        },
+        "I0": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I1": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "CI": {
+          "direction": "input",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
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+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
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+          "bits": [ 2 ],
+          "attributes": {
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+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:129"
+          }
+        },
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+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:129"
+          }
+        }
+      }
+    },
+    "SB_DFF": {
+      "attributes": {
+        "blackbox": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:135"
+      },
+      "ports": {
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+          "bits": [ 2 ]
+        },
+        "C": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "D": {
+          "direction": "input",
+          "bits": [ 4 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "C": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:135"
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+          "attributes": {
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+          "bits": [ 2 ],
+          "attributes": {
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+        }
+      }
+    },
+    "SB_DFFE": {
+      "attributes": {
+        "blackbox": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:140"
+      },
+      "ports": {
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+          "direction": "output",
+          "bits": [ 2 ]
+        },
+        "C": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "E": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "D": {
+          "direction": "input",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "C": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:140"
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+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
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+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:140"
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+        "Q": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:140"
+          }
+        }
+      }
+    },
+    "SB_DFFER": {
+      "attributes": {
+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:188"
+      },
+      "ports": {
+        "Q": {
+          "direction": "output",
+          "bits": [ 2 ]
+        },
+        "C": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "E": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "R": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "D": {
+          "direction": "input",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "C": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:188"
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+        },
+        "D": {
+          "hide_name": 0,
+          "bits": [ 6 ],
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+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:188"
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+        },
+        "Q": {
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+          "bits": [ 2 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:188"
+          }
+        },
+        "R": {
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+          "bits": [ 5 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:188"
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+        }
+      }
+    },
+    "SB_DFFES": {
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+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:206"
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+      "ports": {
+        "Q": {
+          "direction": "output",
+          "bits": [ 2 ]
+        },
+        "C": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "E": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "S": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "D": {
+          "direction": "input",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "C": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:206"
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+        },
+        "D": {
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+          "bits": [ 6 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:206"
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+        },
+        "E": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:206"
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+        },
+        "Q": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:206"
+          }
+        },
+        "S": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:206"
+          }
+        }
+      }
+    },
+    "SB_DFFESR": {
+      "attributes": {
+        "blackbox": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:178"
+      },
+      "ports": {
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+          "direction": "output",
+          "bits": [ 2 ]
+        },
+        "C": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "E": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "R": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "D": {
+          "direction": "input",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "C": {
+          "hide_name": 0,
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+          }
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+        "wb_s2m_timer_dat": {
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+            "src": "../src/serv-wb_intercon_0/wb_intercon.vh:71",
+            "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31"
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+    }
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+}
diff --git a/ice40/regressions/issue0121/serv_0.npnr b/ice40/regressions/issue0121/serv_0.npnr
new file mode 100644
index 0000000..b557bf9
--- /dev/null
+++ b/ice40/regressions/issue0121/serv_0.npnr
@@ -0,0 +1 @@
+--lp8k --package cm81 --freq 16 --pcf-allow-unconstrained
diff --git a/ice40/regressions/issue0121/serv_0.pcf b/ice40/regressions/issue0121/serv_0.pcf
new file mode 100644
index 0000000..7a56754
--- /dev/null
+++ b/ice40/regressions/issue0121/serv_0.pcf
@@ -0,0 +1,2 @@
+set_io q A6
+set_io i_clk B2
diff --git a/ice40/regressions/issue0126/pll-test.json b/ice40/regressions/issue0126/pll-test.json
new file mode 100644
index 0000000..eb8b14d
--- /dev/null
+++ b/ice40/regressions/issue0126/pll-test.json
@@ -0,0 +1,5415 @@
+{
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+          "bits": [ 35 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1092"
+          }
+        }
+      }
+    },
+    "SB_SPRAM256KA": {
+      "attributes": {
+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:942"
+      },
+      "ports": {
+        "ADDRESS": {
+          "direction": "input",
+          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ]
+        },
+        "DATAIN": {
+          "direction": "input",
+          "bits": [ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ]
+        },
+        "MASKWREN": {
+          "direction": "input",
+          "bits": [ 32, 33, 34, 35 ]
+        },
+        "WREN": {
+          "direction": "input",
+          "bits": [ 36 ]
+        },
+        "CHIPSELECT": {
+          "direction": "input",
+          "bits": [ 37 ]
+        },
+        "CLOCK": {
+          "direction": "input",
+          "bits": [ 38 ]
+        },
+        "STANDBY": {
+          "direction": "input",
+          "bits": [ 39 ]
+        },
+        "SLEEP": {
+          "direction": "input",
+          "bits": [ 40 ]
+        },
+        "POWEROFF": {
+          "direction": "input",
+          "bits": [ 41 ]
+        },
+        "DATAOUT": {
+          "direction": "output",
+          "bits": [ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57 ]
+        }
+      },
+      "cells": {
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+      "netnames": {
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+          "bits": [ 37 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+        "CLOCK": {
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+          "bits": [ 38 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
+          }
+        },
+        "DATAIN": {
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+        "DATAOUT": {
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+        "MASKWREN": {
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+          "bits": [ 32, 33, 34, 35 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:945"
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+        },
+        "POWEROFF": {
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+          "bits": [ 41 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
+          }
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+        "SLEEP": {
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+          "bits": [ 40 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
+          }
+        },
+        "STANDBY": {
+          "hide_name": 0,
+          "bits": [ 39 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+          "bits": [ 36 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:946"
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+        }
+      }
+    },
+    "SB_WARMBOOT": {
+      "attributes": {
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+        "blackbox": 1,
+        "cells_not_processed": 1,
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+      },
+      "ports": {
+        "BOOT": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "S1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "S0": {
+          "direction": "input",
+          "bits": [ 4 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
+        "BOOT": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
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+          "bits": [ 3 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:884"
+          }
+        }
+      }
+    },
+    "top": {
+      "attributes": {
+        "top": 1,
+        "src": "pll-test.v:4"
+      },
+      "ports": {
+        "clk12m_in": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "out1": {
+          "direction": "output",
+          "bits": [ 3 ]
+        },
+        "out2": {
+          "direction": "output",
+          "bits": [ 4 ]
+        }
+      },
+      "cells": {
+        "pll0.pll_inst": {
+          "hide_name": 0,
+          "type": "SB_PLL40_2_PAD",
+          "parameters": {
+            "DELAY_ADJUSTMENT_MODE_FEEDBACK": "FIXED",
+            "DIVF": 66,
+            "DIVQ": 5,
+            "DIVR": 0,
+            "ENABLE_ICEGATE_PORTA": 0,
+            "ENABLE_ICEGATE_PORTB": 0,
+            "FDA_FEEDBACK": 0,
+            "FEEDBACK_PATH": "SIMPLE",
+            "FILTER_RANGE": 1,
+            "PLLOUT_SELECT_PORTB": "GENCLK",
+            "SHIFTREG_DIV_MODE": 0
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "pll-test.v:13|pll-test.v:47"
+          },
+          "port_directions": {
+            "BYPASS": "input",
+            "DYNAMICDELAY": "input",
+            "EXTFEEDBACK": "input",
+            "LATCHINPUTVALUE": "input",
+            "LOCK": "output",
+            "PACKAGEPIN": "input",
+            "PLLOUTCOREA": "output",
+            "PLLOUTCOREB": "output",
+            "PLLOUTGLOBALA": "output",
+            "PLLOUTGLOBALB": "output",
+            "RESETB": "input",
+            "SCLK": "input",
+            "SDI": "input",
+            "SDO": "output"
+          },
+          "connections": {
+            "BYPASS": [ "0" ],
+            "DYNAMICDELAY": [ ],
+            "EXTFEEDBACK": [ ],
+            "LATCHINPUTVALUE": [ ],
+            "LOCK": [ 5 ],
+            "PACKAGEPIN": [ 2 ],
+            "PLLOUTCOREA": [ 6 ],
+            "PLLOUTCOREB": [ 7 ],
+            "PLLOUTGLOBALA": [ 4 ],
+            "PLLOUTGLOBALB": [ 3 ],
+            "RESETB": [ "1" ],
+            "SCLK": [ ],
+            "SDI": [ ],
+            "SDO": [ ]
+          }
+        }
+      },
+      "netnames": {
+        "clk12m": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "pll-test.v:11"
+          }
+        },
+        "clk12m_in": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "pll-test.v:5"
+          }
+        },
+        "clk25m": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "pll-test.v:10"
+          }
+        },
+        "out1": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "pll-test.v:6"
+          }
+        },
+        "out2": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "pll-test.v:7"
+          }
+        },
+        "pll0.LOCK": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "pll-test.v:13|pll-test.v:45",
+            "unused_bits": "0"
+          }
+        },
+        "pll0.PACKAGEPIN": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "pll-test.v:13|pll-test.v:39"
+          }
+        },
+        "pll0.PLLOUTCOREA": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "pll-test.v:13|pll-test.v:41",
+            "unused_bits": "0"
+          }
+        },
+        "pll0.PLLOUTCOREB": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "pll-test.v:13|pll-test.v:42",
+            "unused_bits": "0"
+          }
+        },
+        "pll0.PLLOUTGLOBALA": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "pll-test.v:13|pll-test.v:43"
+          }
+        },
+        "pll0.PLLOUTGLOBALB": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "pll-test.v:13|pll-test.v:44"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0126/pll-test.npnr b/ice40/regressions/issue0126/pll-test.npnr
new file mode 100644
index 0000000..7f0606f
--- /dev/null
+++ b/ice40/regressions/issue0126/pll-test.npnr
@@ -0,0 +1 @@
+--package sg48 --up5k
diff --git a/ice40/regressions/issue0126/pll-test.pcf b/ice40/regressions/issue0126/pll-test.pcf
new file mode 100644
index 0000000..3c38feb
--- /dev/null
+++ b/ice40/regressions/issue0126/pll-test.pcf
@@ -0,0 +1,4 @@
+set_io clk12m_in 35
+
+set_io out1 3
+set_io out2 4
diff --git a/ice40/regressions/issue0126/pll-test.v b/ice40/regressions/issue0126/pll-test.v
new file mode 100644
index 0000000..e5ea44b
--- /dev/null
+++ b/ice40/regressions/issue0126/pll-test.v
@@ -0,0 +1,75 @@
+// instantiate pll with both original and generated clocks available
+// pass clocks to test points out1, out2
+
+module top(
+	input clk12m_in,
+	output out1,
+	output out2
+	);
+
+wire clk25m;
+wire clk12m;
+
+pll pll0(
+	.PACKAGEPIN(clk12m_in),
+	.PLLOUTGLOBALA(clk12m),
+	.PLLOUTGLOBALB(clk25m),
+	.PLLOUTCOREA(),
+	.PLLOUTCOREB(),
+	.LOCK(),
+	.RESET(1'b1)
+	);
+
+assign out1 = clk25m;
+assign out2 = clk12m;
+
+endmodule
+
+
+// below generated by lattice icecube2
+
+module pll(PACKAGEPIN,
+           PLLOUTCOREA,
+           PLLOUTCOREB,
+           PLLOUTGLOBALA,
+           PLLOUTGLOBALB,
+           RESET,
+           LOCK);
+
+inout PACKAGEPIN;
+input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ 
+output PLLOUTCOREA;
+output PLLOUTCOREB;
+output PLLOUTGLOBALA;
+output PLLOUTGLOBALB;
+output LOCK;
+
+SB_PLL40_2_PAD pll_inst(.PACKAGEPIN(PACKAGEPIN),
+                        .PLLOUTCOREA(PLLOUTCOREA),
+                        .PLLOUTCOREB(PLLOUTCOREB),
+                        .PLLOUTGLOBALA(PLLOUTGLOBALA),
+                        .PLLOUTGLOBALB(PLLOUTGLOBALB),
+                        .EXTFEEDBACK(),
+                        .DYNAMICDELAY(),
+                        .RESETB(RESET),
+                        .BYPASS(1'b0),
+                        .LATCHINPUTVALUE(),
+                        .LOCK(LOCK),
+                        .SDI(),
+                        .SDO(),
+                        .SCLK());
+
+//\\ Fin=12, Fout=25;
+defparam pll_inst.DIVR = 4'b0000;
+defparam pll_inst.DIVF = 7'b1000010;
+defparam pll_inst.DIVQ = 3'b101;
+defparam pll_inst.FILTER_RANGE = 3'b001;
+defparam pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam pll_inst.PLLOUT_SELECT_PORTB = "GENCLK";
+defparam pll_inst.ENABLE_ICEGATE_PORTA = 1'b0;
+defparam pll_inst.ENABLE_ICEGATE_PORTB = 1'b0;
+
+endmodule
diff --git a/ice40/regressions/issue0126/pll-test.ys b/ice40/regressions/issue0126/pll-test.ys
new file mode 100644
index 0000000..5a0d84c
--- /dev/null
+++ b/ice40/regressions/issue0126/pll-test.ys
@@ -0,0 +1,2 @@
+read_verilog pll-test.v
+synth_ice40 -top top -json pll-test.json
diff --git a/ice40/regressions/issue0151/top.json b/ice40/regressions/issue0151/top.json
new file mode 100644
index 0000000..c9f84e3
--- /dev/null
+++ b/ice40/regressions/issue0151/top.json
@@ -0,0 +1,5376 @@
+{
+  "creator": "Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)",
+  "modules": {
+    "ICESTORM_LC": {
+      "attributes": {
+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:667"
+      },
+      "ports": {
+        "I0": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "I1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I2": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "I3": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "CIN": {
+          "direction": "input",
+          "bits": [ 6 ]
+        },
+        "CLK": {
+          "direction": "input",
+          "bits": [ 7 ]
+        },
+        "CEN": {
+          "direction": "input",
+          "bits": [ 8 ]
+        },
+        "SR": {
+          "direction": "input",
+          "bits": [ 9 ]
+        },
+        "LO": {
+          "direction": "output",
+          "bits": [ 10 ]
+        },
+        "O": {
+          "direction": "output",
+          "bits": [ 11 ]
+        },
+        "COUT": {
+          "direction": "output",
+          "bits": [ 12 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
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+          "hide_name": 0,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
+          }
+        },
+        "CIN": {
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+          "bits": [ 6 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
+          }
+        },
+        "CLK": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
+          }
+        },
+        "COUT": {
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+          "bits": [ 12 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:669"
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+        "I0": {
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+          "bits": [ 2 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
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+        },
+        "I3": {
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+          "bits": [ 5 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
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+        },
+        "LO": {
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+          "bits": [ 10 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:669"
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+        },
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+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:669"
+          }
+        },
+        "SR": {
+          "hide_name": 0,
+          "bits": [ 9 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
+          }
+        }
+      }
+    },
+    "SB_CARRY": {
+      "attributes": {
+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:129"
+      },
+      "ports": {
+        "CO": {
+          "direction": "output",
+          "bits": [ 2 ]
+        },
+        "I0": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I1": {
+          "direction": "input",
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+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:942"
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+          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ]
+        },
+        "DATAIN": {
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+        },
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+          "direction": "input",
+          "bits": [ 36 ]
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+        "CHIPSELECT": {
+          "direction": "input",
+          "bits": [ 37 ]
+        },
+        "CLOCK": {
+          "direction": "input",
+          "bits": [ 38 ]
+        },
+        "STANDBY": {
+          "direction": "input",
+          "bits": [ 39 ]
+        },
+        "SLEEP": {
+          "direction": "input",
+          "bits": [ 40 ]
+        },
+        "POWEROFF": {
+          "direction": "input",
+          "bits": [ 41 ]
+        },
+        "DATAOUT": {
+          "direction": "output",
+          "bits": [ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57 ]
+        }
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+          "attributes": {
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+          "bits": [ 38 ],
+          "attributes": {
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+        "cells_not_processed": 1,
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+      },
+      "ports": {
+        "BOOT": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "S1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "S0": {
+          "direction": "input",
+          "bits": [ 4 ]
+        }
+      },
+      "cells": {
+      },
+      "netnames": {
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+          "bits": [ 2 ],
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+          "attributes": {
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+        }
+      }
+    },
+    "top": {
+      "attributes": {
+        "top": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "in_n": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 3 ]
+        }
+      },
+      "cells": {
+        "$abc$71$auto$blifparse.cc:492:parse_blif$72": {
+          "hide_name": 1,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": 1
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
+          },
+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
+          },
+          "connections": {
+            "I0": [ 3 ],
+            "I1": [ "0" ],
+            "I2": [ "0" ],
+            "I3": [ "0" ],
+            "O": [ 4 ]
+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$56": {
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+          "type": "SB_DFF",
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+          },
+          "attributes": {
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+            "src": "top.v:19|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "C": [ 5 ],
+            "D": [ 4 ],
+            "Q": [ 3 ]
+          }
+        },
+        "differential_clock_input": {
+          "hide_name": 0,
+          "type": "SB_GB_IO",
+          "parameters": {
+            "IO_STANDARD": "SB_LVDS_INPUT",
+            "PIN_TYPE": 0
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "top.v:8"
+          },
+          "port_directions": {
+            "GLOBAL_BUFFER_OUTPUT": "output",
+            "PACKAGE_PIN": "inout"
+          },
+          "connections": {
+            "GLOBAL_BUFFER_OUTPUT": [ 5 ],
+            "PACKAGE_PIN": [ 2 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\cntr[0:0]": {
+          "hide_name": 1,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:19"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "top.v:6"
+          }
+        },
+        "cntr": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "in_n": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:2"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0151/top.npnr b/ice40/regressions/issue0151/top.npnr
new file mode 100644
index 0000000..6c0ab4d
--- /dev/null
+++ b/ice40/regressions/issue0151/top.npnr
@@ -0,0 +1 @@
+--hx8k --package tq144:4k
diff --git a/ice40/regressions/issue0151/top.pcf b/ice40/regressions/issue0151/top.pcf
new file mode 100644
index 0000000..d5bb551
--- /dev/null
+++ b/ice40/regressions/issue0151/top.pcf
@@ -0,0 +1,2 @@
+set_io in_n 20
+set_io out 1
diff --git a/ice40/regressions/issue0151/top.v b/ice40/regressions/issue0151/top.v
new file mode 100644
index 0000000..7e987f2
--- /dev/null
+++ b/ice40/regressions/issue0151/top.v
@@ -0,0 +1,23 @@
+module top (
+  input wire in_n,
+  output wire out
+);
+
+wire clk;
+
+SB_GB_IO #(
+  .PIN_TYPE(6'b000000),
+  .IO_STANDARD("SB_LVDS_INPUT")
+) differential_clock_input (
+  .PACKAGE_PIN(in_n),
+  .GLOBAL_BUFFER_OUTPUT(clk)
+);
+
+assign out = cntr;
+reg cntr = 1'd0;
+
+always @(posedge clk) begin
+  cntr <= !cntr;
+end
+
+endmodule
diff --git a/ice40/regressions/issue0151/top.ys b/ice40/regressions/issue0151/top.ys
new file mode 100644
index 0000000..0efb9f9
--- /dev/null
+++ b/ice40/regressions/issue0151/top.ys
@@ -0,0 +1,2 @@
+read_verilog top.v
+synth_ice40 -json top.json
diff --git a/ice40/regressions/issue0170/hx8kbb.json b/ice40/regressions/issue0170/hx8kbb.json
new file mode 100644
index 0000000..4e752e3
--- /dev/null
+++ b/ice40/regressions/issue0170/hx8kbb.json
@@ -0,0 +1,49585 @@
+{
+  "creator": "Yosys 0.8+64 (git sha1 1bb728e, clang 3.8.0-2ubuntu4 -fPIC -Os)",
+  "modules": {
+    "ICESTORM_LC": {
+      "attributes": {
+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:648"
+      },
+      "ports": {
+        "I0": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "I1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I2": {
+          "direction": "input",
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+}
diff --git a/ice40/regressions/issue0170/hx8kbb.npnr b/ice40/regressions/issue0170/hx8kbb.npnr
new file mode 100644
index 0000000..86f99ee
--- /dev/null
+++ b/ice40/regressions/issue0170/hx8kbb.npnr
@@ -0,0 +1 @@
+--hx8k --package ct256 --freq 80 --pcf-allow-unconstrained
diff --git a/ice40/regressions/issue0170/hx8kbb.pcf b/ice40/regressions/issue0170/hx8kbb.pcf
new file mode 100644
index 0000000..acb958b
--- /dev/null
+++ b/ice40/regressions/issue0170/hx8kbb.pcf
@@ -0,0 +1,15 @@
+set_io BCLK G1 # only gbin pin on connector J4, expects 80MHz, others change on negative edge.
+set_io LRCLK J1 # expects 2.5MHz, low signifies new frame, msb of first channel; high is second channel
+# LRCLK should idle high
+set_io SDIN M1
+# above should use closely-mounted, terminated LVDS receiver modules.
+# 80MHz single-ended is a Bad Idea over wires between boards.
+
+# SPI Master output
+# on connector J3
+set_io SCLKp R3
+set_io SCLKn T5
+set_io DOp T7
+set_io DOn T9
+set_io CSp T10
+set_io CSn T11
diff --git a/ice40/regressions/issue0176/test1.json b/ice40/regressions/issue0176/test1.json
new file mode 100644
index 0000000..9c57961
--- /dev/null
+++ b/ice40/regressions/issue0176/test1.json
@@ -0,0 +1,5365 @@
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+        "PROBE": {
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+          "bits": [ "x" ]
+        }
+      },
+      "cells": {
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+          "hide_name": 1,
+          "type": "SB_LUT4",
+          "parameters": {
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+          "attributes": {
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+          "attributes": {
+            "src": "top.v:2"
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+          "hide_name": 0,
+          "bits": [ "1" ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "PROBE": {
+          "hide_name": 0,
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+            "src": "top.v:6"
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+}
diff --git a/ice40/regressions/issue0176/test1.ys b/ice40/regressions/issue0176/test1.ys
new file mode 100644
index 0000000..d5b2e6b
--- /dev/null
+++ b/ice40/regressions/issue0176/test1.ys
@@ -0,0 +1,2 @@
+read_verilog -DCONST_INOUT top.v
+synth_ice40 -json test1.json
diff --git a/ice40/regressions/issue0176/test2.json b/ice40/regressions/issue0176/test2.json
new file mode 100644
index 0000000..e06a4fb
--- /dev/null
+++ b/ice40/regressions/issue0176/test2.json
@@ -0,0 +1,5365 @@
+{
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diff --git a/ice40/regressions/issue0176/test2.ys b/ice40/regressions/issue0176/test2.ys
new file mode 100644
index 0000000..438a050
--- /dev/null
+++ b/ice40/regressions/issue0176/test2.ys
@@ -0,0 +1,2 @@
+read_verilog -DCONST_CLK_ASSIGN top.v
+synth_ice40 -json test2.json
diff --git a/ice40/regressions/issue0176/test3.json b/ice40/regressions/issue0176/test3.json
new file mode 100644
index 0000000..a86d2b6
--- /dev/null
+++ b/ice40/regressions/issue0176/test3.json
@@ -0,0 +1,5365 @@
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diff --git a/ice40/regressions/issue0176/test3.ys b/ice40/regressions/issue0176/test3.ys
new file mode 100644
index 0000000..5d4dfc3
--- /dev/null
+++ b/ice40/regressions/issue0176/test3.ys
@@ -0,0 +1,2 @@
+read_verilog -DCONST_ASSIGN top.v
+synth_ice40 -json test3.json
diff --git a/ice40/regressions/issue0176/test4.json b/ice40/regressions/issue0176/test4.json
new file mode 100644
index 0000000..b075dba
--- /dev/null
+++ b/ice40/regressions/issue0176/test4.json
@@ -0,0 +1,5415 @@
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diff --git a/ice40/regressions/issue0176/test4.ys b/ice40/regressions/issue0176/test4.ys
new file mode 100644
index 0000000..4ceef80
--- /dev/null
+++ b/ice40/regressions/issue0176/test4.ys
@@ -0,0 +1,2 @@
+read_verilog -DDYN_INOUT top.v
+synth_ice40 -json test4.json
diff --git a/ice40/regressions/issue0176/test5.json b/ice40/regressions/issue0176/test5.json
new file mode 100644
index 0000000..897d6b6
--- /dev/null
+++ b/ice40/regressions/issue0176/test5.json
@@ -0,0 +1,5435 @@
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+}
diff --git a/ice40/regressions/issue0176/test5.ys b/ice40/regressions/issue0176/test5.ys
new file mode 100644
index 0000000..417646f
--- /dev/null
+++ b/ice40/regressions/issue0176/test5.ys
@@ -0,0 +1,2 @@
+read_verilog -DDYN_CLK_ASSIGN top.v
+synth_ice40 -json test5.json
diff --git a/ice40/regressions/issue0176/test6.json b/ice40/regressions/issue0176/test6.json
new file mode 100644
index 0000000..b0e9f0f
--- /dev/null
+++ b/ice40/regressions/issue0176/test6.json
@@ -0,0 +1,5415 @@
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+}
diff --git a/ice40/regressions/issue0176/test6.ys b/ice40/regressions/issue0176/test6.ys
new file mode 100644
index 0000000..d72c47a
--- /dev/null
+++ b/ice40/regressions/issue0176/test6.ys
@@ -0,0 +1,2 @@
+read_verilog -DDYN_ASSIGN top.v
+synth_ice40 -json test6.json
diff --git a/ice40/regressions/issue0176/test7.json b/ice40/regressions/issue0176/test7.json
new file mode 100644
index 0000000..1d58255
--- /dev/null
+++ b/ice40/regressions/issue0176/test7.json
@@ -0,0 +1,5415 @@
+{
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+        "I3": {
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diff --git a/ice40/regressions/issue0176/test7.ys b/ice40/regressions/issue0176/test7.ys
new file mode 100644
index 0000000..512171d
--- /dev/null
+++ b/ice40/regressions/issue0176/test7.ys
@@ -0,0 +1,2 @@
+read_verilog -DCIRCULAR_INOUT top.v
+synth_ice40 -json test7.json
diff --git a/ice40/regressions/issue0176/test8.json b/ice40/regressions/issue0176/test8.json
new file mode 100644
index 0000000..b7ff93f
--- /dev/null
+++ b/ice40/regressions/issue0176/test8.json
@@ -0,0 +1,5415 @@
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+            "I2": [ "0" ],
+            "I3": [ "0" ],
+            "O": [ 6 ]
+          }
+        },
+        "$auto$simplemap.cc:293:simplemap_tribuf$59": {
+          "hide_name": 1,
+          "type": "$_TBUF_",
+          "parameters": {
+          },
+          "attributes": {
+            "src": "top.v:38"
+          },
+          "port_directions": {
+            "A": "input",
+            "E": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ "0" ],
+            "E": [ 5 ],
+            "Y": [ 4 ]
+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$91": {
+          "hide_name": 1,
+          "type": "SB_DFF",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "top.v:9|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "C": [ 2 ],
+            "D": [ 6 ],
+            "Q": [ 3 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\IGNORE_ME[0:0]": {
+          "hide_name": 1,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "top.v:9"
+          }
+        },
+        "$abc$106$n1": {
+          "hide_name": 1,
+          "bits": [ 5 ],
+          "attributes": {
+          }
+        },
+        "CLK": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:2"
+          }
+        },
+        "IGNORE_ME": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "INOUT": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "PROBE": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:6"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0176/test8.ys b/ice40/regressions/issue0176/test8.ys
new file mode 100644
index 0000000..350139d
--- /dev/null
+++ b/ice40/regressions/issue0176/test8.ys
@@ -0,0 +1,2 @@
+read_verilog -DCIRCULAR_ASSIGN top.v
+synth_ice40 -json test8.json
diff --git a/ice40/regressions/issue0176/top.v b/ice40/regressions/issue0176/top.v
new file mode 100644
index 0000000..f8ad851
--- /dev/null
+++ b/ice40/regressions/issue0176/top.v
@@ -0,0 +1,43 @@
+module top(
+    input CLK,
+    output reg IGNORE_ME,
+
+    inout INOUT,
+    output reg PROBE
+);
+
+always @(posedge CLK)
+    IGNORE_ME <= ~IGNORE_ME; // Pretend to do work (silence warning).
+
+// <<< Variations go here! >>>
+`ifdef CONST_INOUT
+assign INOUT= 'b1;
+`elsif CONST_CLK_ASSIGN
+assign INOUT = 'b1;
+
+always @(posedge CLK)
+    PROBE <= INOUT;
+`elsif CONST_ASSIGN
+assign INOUT = 'b1;
+
+assign PROBE = INOUT;
+`elsif DYN_INOUT
+assign INOUT = CLK ? 'bz : 'b0;
+`elsif DYN_CLK_ASSIGN
+assign INOUT = CLK ? 'bz : 'b0;
+
+always @(posedge CLK)
+    PROBE <= INOUT;
+`elsif DYN_ASSIGN
+assign INOUT = CLK ? 'bz : 'b0;
+
+assign PROBE = INOUT;
+`elsif CIRCULAR_INOUT
+assign INOUT = INOUT ? 'bz : 'b0;
+`elsif CIRCULAR_ASSIGN
+assign INOUT = INOUT ? 'bz : 'b0;
+
+assign PROBE = INOUT;
+`endif
+
+endmodule
diff --git a/ice40/regressions/issue0186/pll.v b/ice40/regressions/issue0186/pll.v
new file mode 100644
index 0000000..48ca3cc
--- /dev/null
+++ b/ice40/regressions/issue0186/pll.v
@@ -0,0 +1,33 @@
+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:       100.000 MHz
+ * Requested output frequency:  120.000 MHz
+ * Achieved output frequency:   120.000 MHz
+ */
+
+module pll(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0100),		// DIVR =  4
+		.DIVF(7'b0101111),	// DIVF = 47
+		.DIVQ(3'b011),		// DIVQ =  3
+		.FILTER_RANGE(3'b010)	// FILTER_RANGE = 2
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule
diff --git a/ice40/regressions/issue0186/test.json b/ice40/regressions/issue0186/test.json
new file mode 100644
index 0000000..5010b0a
--- /dev/null
+++ b/ice40/regressions/issue0186/test.json
@@ -0,0 +1,6838 @@
+{
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+          "direction": "input",
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+        },
+        "CIN": {
+          "direction": "input",
+          "bits": [ 6 ]
+        },
+        "CLK": {
+          "direction": "input",
+          "bits": [ 7 ]
+        },
+        "CEN": {
+          "direction": "input",
+          "bits": [ 8 ]
+        },
+        "SR": {
+          "direction": "input",
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+        },
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+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 66 ],
+            "D": [ 62 ],
+            "Q": [ 61 ],
+            "R": [ 7 ]
+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$94": {
+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
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+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 66 ],
+            "D": [ 65 ],
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+            "R": [ 7 ]
+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$95": {
+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 66 ],
+            "D": [ 14 ],
+            "Q": [ 12 ],
+            "R": [ 7 ]
+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$96": {
+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
+          },
+          "attributes": {
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+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 66 ],
+            "D": [ 17 ],
+            "Q": [ 16 ],
+            "R": [ 7 ]
+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$97": {
+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
+          },
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+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
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+            "Q": [ 19 ],
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+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$98": {
+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
+          },
+          "attributes": {
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+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
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+          }
+        },
+        "$auto$simplemap.cc:420:simplemap_dff$99": {
+          "hide_name": 1,
+          "type": "SB_DFFSR",
+          "parameters": {
+          },
+          "attributes": {
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+            "src": "test.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+          },
+          "port_directions": {
+            "C": "input",
+            "D": "input",
+            "Q": "output",
+            "R": "input"
+          },
+          "connections": {
+            "C": [ 66 ],
+            "D": [ 26 ],
+            "Q": [ 25 ],
+            "R": [ 7 ]
+          }
+        },
+        "mypll.uut": {
+          "hide_name": 0,
+          "type": "SB_PLL40_CORE",
+          "parameters": {
+            "DIVF": 47,
+            "DIVQ": 3,
+            "DIVR": 4,
+            "FEEDBACK_PATH": "SIMPLE",
+            "FILTER_RANGE": 2
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "test.v:14|pll.v:19"
+          },
+          "port_directions": {
+            "BYPASS": "input",
+            "LOCK": "output",
+            "PLLOUTCORE": "output",
+            "REFERENCECLK": "input",
+            "RESETB": "input"
+          },
+          "connections": {
+            "BYPASS": [ "0" ],
+            "LOCK": [ 7 ],
+            "PLLOUTCORE": [ 66 ],
+            "REFERENCECLK": [ 2 ],
+            "RESETB": [ "1" ]
+          }
+        }
+      },
+      "netnames": {
+        "$abc$231$n2": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+          }
+        },
+        "$abc$231$n4": {
+          "hide_name": 1,
+          "bits": [ 10 ],
+          "attributes": {
+          }
+        },
+        "$add$test.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 11, 67, 44, 47, 50, 53, 56, 59, 62, 65, 14, 17, 20, 23, 26, 29, 32, 35, 37, 39, 42 ],
+          "attributes": {
+          }
+        },
+        "$auto$alumacc.cc:474:replace_alu$8.C": {
+          "hide_name": 1,
+          "bits": [ 68, 69, 41, 45, 48, 51, 54, 57, 60, 63, 13, 15, 18, 21, 24, 27, 30, 33, 36, 38, 40 ],
+          "attributes": {
+            "src": "test.v:18|/usr/local/bin/../share/yosys/ice40/arith_map.v:43"
+          }
+        },
+        "cntr": {
+          "hide_name": 0,
+          "bits": [ 6, 9, 43, 46, 49, 52, 55, 58, 61, 64, 12, 16, 19, 22, 25, 28, 31, 34, 3, 4, 5 ],
+          "attributes": {
+            "src": "test.v:10"
+          }
+        },
+        "fclock": {
+          "hide_name": 0,
+          "bits": [ 66 ],
+          "attributes": {
+            "src": "test.v:12"
+          }
+        },
+        "led1": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "test.v:5"
+          }
+        },
+        "led2": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "test.v:6"
+          }
+        },
+        "led3": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "test.v:7"
+          }
+        },
+        "lock": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "test.v:11"
+          }
+        },
+        "mypll.clock_in": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "test.v:14|pll.v:14"
+          }
+        },
+        "mypll.clock_out": {
+          "hide_name": 0,
+          "bits": [ 66 ],
+          "attributes": {
+            "src": "test.v:14|pll.v:15"
+          }
+        },
+        "mypll.locked": {
+          "hide_name": 0,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "test.v:14|pll.v:16"
+          }
+        },
+        "pclk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "test.v:4"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0186/test.npnr b/ice40/regressions/issue0186/test.npnr
new file mode 100644
index 0000000..584e21b
--- /dev/null
+++ b/ice40/regressions/issue0186/test.npnr
@@ -0,0 +1 @@
+--hx8k
diff --git a/ice40/regressions/issue0186/test.pcf b/ice40/regressions/issue0186/test.pcf
new file mode 100644
index 0000000..5ff7847
--- /dev/null
+++ b/ice40/regressions/issue0186/test.pcf
@@ -0,0 +1,10 @@
+#
+# I/O pins for HX8K
+#
+set_io --warn-no-port led1 C8
+set_io --warn-no-port led2 F7
+set_io --warn-no-port led3 K9
+
+set_io pclk R9
+
+
diff --git a/ice40/regressions/issue0186/test.v b/ice40/regressions/issue0186/test.v
new file mode 100644
index 0000000..577f216
--- /dev/null
+++ b/ice40/regressions/issue0186/test.v
@@ -0,0 +1,26 @@
+`include "pll.v"
+
+module top (
+	input pclk,              // 100MHz clock
+	output led1,
+	output led2,
+	output led3
+);
+
+	reg [20:0] cntr;
+	wire lock;
+	wire fclock;
+	
+	pll mypll(pclk,fclock,lock);
+	
+	always@(posedge fclock) begin
+		if (lock) cntr <= 21'h00000000;
+		else cntr<= cntr+1;
+	end
+	
+	assign led1 = cntr[18];
+	assign led2 = cntr[19];
+	assign led3 = cntr[20];
+	
+	endmodule
+	
diff --git a/ice40/regressions/issue0186/test.ys b/ice40/regressions/issue0186/test.ys
new file mode 100644
index 0000000..76f616f
--- /dev/null
+++ b/ice40/regressions/issue0186/test.ys
@@ -0,0 +1,2 @@
+read_verilog test.v
+synth_ice40 -json test.json
diff --git a/ice40/regressions/issue0188/pll.v b/ice40/regressions/issue0188/pll.v
new file mode 100644
index 0000000..7b1ce33
--- /dev/null
+++ b/ice40/regressions/issue0188/pll.v
@@ -0,0 +1,33 @@
+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:       100.000 MHz
+ * Requested output frequency:   16.000 MHz
+ * Achieved output frequency:    16.016 MHz
+ */
+
+module pll(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0011),		// DIVR =  3
+		.DIVF(7'b0101000),	// DIVF = 40
+		.DIVQ(3'b110),		// DIVQ =  6
+		.FILTER_RANGE(3'b010)	// FILTER_RANGE = 2
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule
diff --git a/ice40/regressions/issue0188/test.json b/ice40/regressions/issue0188/test.json
new file mode 100644
index 0000000..0be2a02
--- /dev/null
+++ b/ice40/regressions/issue0188/test.json
@@ -0,0 +1,6906 @@
+{
+  "creator": "Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)",
+  "modules": {
+    "ICESTORM_LC": {
+      "attributes": {
+        "blackbox": 1,
+        "cells_not_processed": 1,
+        "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:667"
+      },
+      "ports": {
+        "I0": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "I1": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "I2": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "I3": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "CIN": {
+          "direction": "input",
+          "bits": [ 6 ]
+        },
+        "CLK": {
+          "direction": "input",
+          "bits": [ 7 ]
+        },
+        "CEN": {
+          "direction": "input",
+          "bits": [ 8 ]
+        },
+        "SR": {
+          "direction": "input",
+          "bits": [ 9 ]
+        },
+        "LO": {
+          "direction": "output",
+          "bits": [ 10 ]
+        },
+        "O": {
+          "direction": "output",
+          "bits": [ 11 ]
+        },
+        "COUT": {
+          "direction": "output",
+          "bits": [ 12 ]
+        }
+      },
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+      },
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+          "bits": [ 6 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
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+        "CLK": {
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+          "bits": [ 3 ]
+        },
+        "I1": {
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+        },
+        "CI": {
+          "direction": "input",
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+        }
+      },
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+        },
+        "R": {
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+        },
+        "D": {
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+        }
+      },
+      "cells": {
+      },
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+        },
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+        },
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+          }
+        },
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+          },
+          "connections": {
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+            "Q": [ 18 ],
+            "R": [ 10 ]
+          }
+        },
+        "mypll.uut": {
+          "hide_name": 0,
+          "type": "SB_PLL40_CORE",
+          "parameters": {
+            "DIVF": 40,
+            "DIVQ": 6,
+            "DIVR": 3,
+            "FEEDBACK_PATH": "SIMPLE",
+            "FILTER_RANGE": 2
+          },
+          "attributes": {
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+            "src": "test.v:16|pll.v:19"
+          },
+          "port_directions": {
+            "BYPASS": "input",
+            "LOCK": "output",
+            "PLLOUTCORE": "output",
+            "REFERENCECLK": "input",
+            "RESETB": "input"
+          },
+          "connections": {
+            "BYPASS": [ "0" ],
+            "LOCK": [ 8 ],
+            "PLLOUTCORE": [ 69 ],
+            "REFERENCECLK": [ 2 ],
+            "RESETB": [ "1" ]
+          }
+        }
+      },
+      "netnames": {
+        "$abc$277$n1": {
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+          "bits": [ 10 ],
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+          }
+        },
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+        },
+        "$abc$277$n6": {
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+          "attributes": {
+          }
+        },
+        "$add$test.v:20$3_Y": {
+          "hide_name": 1,
+          "bits": [ 13, 70, 47, 50, 53, 56, 59, 62, 65, 68, 16, 19, 22, 25, 28, 31, 34, 37, 40, 42, 45 ],
+          "attributes": {
+          }
+        },
+        "$auto$alumacc.cc:474:replace_alu$10.C": {
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+          "attributes": {
+            "src": "test.v:20|/usr/local/bin/../share/yosys/ice40/arith_map.v:43"
+          }
+        },
+        "button": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "test.v:7"
+          }
+        },
+        "button_read": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "test.v:11"
+          }
+        },
+        "cntr": {
+          "hide_name": 0,
+          "bits": [ 7, 11, 46, 49, 52, 55, 58, 61, 64, 67, 14, 18, 21, 24, 27, 30, 33, 36, 39, 4, 6 ],
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+          }
+        },
+        "fclock": {
+          "hide_name": 0,
+          "bits": [ 69 ],
+          "attributes": {
+            "src": "test.v:14"
+          }
+        },
+        "led1": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "test.v:5"
+          }
+        },
+        "led2": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "test.v:6"
+          }
+        },
+        "led3": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "test.v:8"
+          }
+        },
+        "lock": {
+          "hide_name": 0,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "test.v:13"
+          }
+        },
+        "mypll.clock_in": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "test.v:16|pll.v:14"
+          }
+        },
+        "mypll.clock_out": {
+          "hide_name": 0,
+          "bits": [ 69 ],
+          "attributes": {
+            "src": "test.v:16|pll.v:15"
+          }
+        },
+        "mypll.locked": {
+          "hide_name": 0,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "test.v:16|pll.v:16"
+          }
+        },
+        "pclk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "test.v:4"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0188/test.npnr b/ice40/regressions/issue0188/test.npnr
new file mode 100644
index 0000000..584e21b
--- /dev/null
+++ b/ice40/regressions/issue0188/test.npnr
@@ -0,0 +1 @@
+--hx8k
diff --git a/ice40/regressions/issue0188/test.pcf b/ice40/regressions/issue0188/test.pcf
new file mode 100644
index 0000000..ef20571
--- /dev/null
+++ b/ice40/regressions/issue0188/test.pcf
@@ -0,0 +1,12 @@
+#
+# I/O pins for HX8K
+#
+set_io --warn-no-port led1 C8
+set_io --warn-no-port led2 F7
+set_io --warn-no-port led3 K9
+
+set_io pclk R9
+
+set_io --warn-no-port -pullup yes button F9
+
+
diff --git a/ice40/regressions/issue0188/test.v b/ice40/regressions/issue0188/test.v
new file mode 100644
index 0000000..199c07f
--- /dev/null
+++ b/ice40/regressions/issue0188/test.v
@@ -0,0 +1,29 @@
+`include "pll.v"
+
+module top (
+	input pclk,              // 100MHz clock
+	output led1,
+	output led2,
+	input  button,
+	output led3
+);
+	
+	reg button_read;
+	reg [20:0] cntr;
+	wire lock;
+	wire fclock;
+	
+	pll mypll(pclk,fclock,lock);
+	
+	always@(posedge fclock) begin
+		if (~lock) cntr <= 21'h00000000;
+		else cntr<= cntr+1;
+		button_read <= button;
+	end
+	
+	assign led1 = button_read;
+	assign led2 = cntr[19];
+	assign led3 = cntr[20];
+	
+	endmodule
+	
diff --git a/ice40/regressions/issue0188/test.ys b/ice40/regressions/issue0188/test.ys
new file mode 100644
index 0000000..76f616f
--- /dev/null
+++ b/ice40/regressions/issue0188/test.ys
@@ -0,0 +1,2 @@
+read_verilog test.v
+synth_ice40 -json test.json
diff --git a/ice40/regressions/issue0203/ringosc.json b/ice40/regressions/issue0203/ringosc.json
new file mode 100644
index 0000000..81164ca
--- /dev/null
+++ b/ice40/regressions/issue0203/ringosc.json
@@ -0,0 +1,5377 @@
+{
+  "creator": "Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)",
+  "modules": {
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+        },
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+        },
+        "I3": {
+          "direction": "input",
+          "bits": [ 5 ]
+        },
+        "CIN": {
+          "direction": "input",
+          "bits": [ 6 ]
+        },
+        "CLK": {
+          "direction": "input",
+          "bits": [ 7 ]
+        },
+        "CEN": {
+          "direction": "input",
+          "bits": [ 8 ]
+        },
+        "SR": {
+          "direction": "input",
+          "bits": [ 9 ]
+        },
+        "LO": {
+          "direction": "output",
+          "bits": [ 10 ]
+        },
+        "O": {
+          "direction": "output",
+          "bits": [ 11 ]
+        },
+        "COUT": {
+          "direction": "output",
+          "bits": [ 12 ]
+        }
+      },
+      "cells": {
+      },
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+          "attributes": {
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+          "bits": [ 6 ],
+          "attributes": {
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:668"
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+        "CLK": {
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+        "random": {
+          "hide_name": 0,
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+    }
+  }
+}
diff --git a/ice40/regressions/issue0203/ringosc.npnr b/ice40/regressions/issue0203/ringosc.npnr
new file mode 100644
index 0000000..b936322
--- /dev/null
+++ b/ice40/regressions/issue0203/ringosc.npnr
@@ -0,0 +1 @@
+--force
diff --git a/ice40/regressions/issue0203/ringosc.pcf b/ice40/regressions/issue0203/ringosc.pcf
new file mode 100644
index 0000000..189426c
--- /dev/null
+++ b/ice40/regressions/issue0203/ringosc.pcf
@@ -0,0 +1 @@
+set_io D1 99
diff --git a/ice40/regressions/issue0203/ringosc.v b/ice40/regressions/issue0203/ringosc.v
new file mode 100644
index 0000000..6df8b0a
--- /dev/null
+++ b/ice40/regressions/issue0203/ringosc.v
@@ -0,0 +1,23 @@
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module top(output D1);
+
+  wire [1:0] buffers_in, buffers_out;
+  assign buffers_in = {buffers_out[0:0], ~buffers_out[1]};
+  SB_LUT4 #(
+          .LUT_INIT(16'd2)
+  ) buffers [1:0] (
+          .O(buffers_out),
+          .I0(buffers_in),
+          .I1(1'b0),
+          .I2(1'b0),
+          .I3(1'b0)
+  );
+
+  wire random = ~buffers_out[1];
+
+  assign D1 = random;
+
+endmodule // top
diff --git a/ice40/regressions/issue0203/ringosc.ys b/ice40/regressions/issue0203/ringosc.ys
new file mode 100644
index 0000000..0ebec93
--- /dev/null
+++ b/ice40/regressions/issue0203/ringosc.ys
@@ -0,0 +1,2 @@
+read_verilog ringosc.v
+synth_ice40 -top top -json ringosc.json -blif ringosc.blif -abc2
diff --git a/ice40/regressions/issue0209/test.json b/ice40/regressions/issue0209/test.json
new file mode 100644
index 0000000..5435715
--- /dev/null
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+      "netnames": {
+        "PIN_18": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "test.v:2"
+          }
+        },
+        "PIN_5": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "test.v:2"
+          }
+        },
+        "in.pin": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "test.v:3|test.v:6",
+            "unused_bits": "0"
+          }
+        },
+        "in.rd": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "test.v:3|test.v:6"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/ice40/regressions/issue0209/test.npnr b/ice40/regressions/issue0209/test.npnr
new file mode 100644
index 0000000..32da58f
--- /dev/null
+++ b/ice40/regressions/issue0209/test.npnr
@@ -0,0 +1 @@
+--lp8k --package cm81
diff --git a/ice40/regressions/issue0209/test.pcf b/ice40/regressions/issue0209/test.pcf
new file mode 100644
index 0000000..3542b71
--- /dev/null
+++ b/ice40/regressions/issue0209/test.pcf
@@ -0,0 +1,2 @@
+set_io --warn-no-port PIN_5 C1
+set_io --warn-no-port PIN_18 A9
diff --git a/ice40/regressions/issue0209/test.sh b/ice40/regressions/issue0209/test.sh
new file mode 100644
index 0000000..27bc2ca
--- /dev/null
+++ b/ice40/regressions/issue0209/test.sh
@@ -0,0 +1,3 @@
+:> test.log
+${NPNR} --json test.json --pcf test.pcf `cat test.npnr` > test.log 2>&1 || true
+grep "^ERROR: BEL 'X0/Y28/io0' has no global buffer connection available$" test.log
diff --git a/ice40/regressions/issue0209/test.v b/ice40/regressions/issue0209/test.v
new file mode 100644
index 0000000..5ca7d72
--- /dev/null
+++ b/ice40/regressions/issue0209/test.v
@@ -0,0 +1,10 @@
+// test.v
+module test (input  PIN_5, output wire PIN_18);
+   lvds_clock_input in (PIN_5, PIN_18);
+endmodule
+
+module lvds_clock_input ( input pin, output wire rd );
+   SB_GB_IO #(.PIN_TYPE(6'b0000_00),
+           .IO_STANDARD("SB_LVDS_INPUT")) lvds_in
+     (.PACKAGE_PIN(pin), .GLOBAL_BUFFER_OUTPUT(rd));
+endmodule
diff --git a/ice40/regressions/issue0209/test.ys b/ice40/regressions/issue0209/test.ys
new file mode 100644
index 0000000..76f616f
--- /dev/null
+++ b/ice40/regressions/issue0209/test.ys
@@ -0,0 +1,2 @@
+read_verilog test.v
+synth_ice40 -json test.json