4 files changed, 90 insertions, 0 deletions
diff --git a/fpga_interchange/site_router_tests/lut/CMakeLists.txt b/fpga_interchange/site_router_tests/lut/CMakeLists.txt
new file mode 100644
index 0000000..1441b38
--- /dev/null
+++ b/fpga_interchange/site_router_tests/lut/CMakeLists.txt
@@ -0,0 +1,6 @@
+add_site_router_test(
+    name lut
+    board arty35t
+    test_script test.yaml
+    sources lut.v
+)
diff --git a/fpga_interchange/site_router_tests/lut/lut.v b/fpga_interchange/site_router_tests/lut/lut.v
new file mode 100644
index 0000000..141d7b1
--- /dev/null
+++ b/fpga_interchange/site_router_tests/lut/lut.v
@@ -0,0 +1,24 @@
+module top(input [5:0] lut_1_in, input [4:0] lut_2_in, output lut_1_out, output lut_2_out);
+
+(* keep *)
+LUT6 #(.INIT(64'hFFFFFFFFFFFFFFFF)) lut_1 (
+ .I0(lut_1_in[0]),
+ .I1(lut_1_in[1]),
+ .I2(lut_1_in[2]),
+ .I3(lut_1_in[3]),
+ .I4(lut_1_in[4]),
+ .I5(lut_1_in[5]),
+ .O(lut_1_out)
+);
+
+(* keep *)
+LUT5 #(.INIT(32'h0)) lut_2 (
+ .I0(lut_1_in[0]),
+ .I1(lut_2_in[1]),
+ .I2(lut_2_in[2]),
+ .I3(lut_2_in[3]),
+ .I4(lut_2_in[4]),
+ .O(lut_2_out)
+);
+
+endmodule
diff --git a/fpga_interchange/site_router_tests/lut/lut.xdc b/fpga_interchange/site_router_tests/lut/lut.xdc
new file mode 100644
index 0000000..426b3a9
--- /dev/null
+++ b/fpga_interchange/site_router_tests/lut/lut.xdc
@@ -0,0 +1,32 @@
+## arty-35t board
+set_property PACKAGE_PIN G13  [get_ports lut_1_in[0]]
+set_property PACKAGE_PIN B11  [get_ports lut_1_in[1]]
+set_property PACKAGE_PIN A11  [get_ports lut_1_in[2]]
+set_property PACKAGE_PIN D12  [get_ports lut_1_in[3]]
+set_property PACKAGE_PIN D13  [get_ports lut_1_in[4]]
+set_property PACKAGE_PIN B18  [get_ports lut_1_in[5]]
+
+set_property PACKAGE_PIN E15  [get_ports lut_2_in[0]]
+set_property PACKAGE_PIN E16  [get_ports lut_2_in[1]]
+set_property PACKAGE_PIN D15  [get_ports lut_2_in[2]]
+set_property PACKAGE_PIN C15  [get_ports lut_2_in[3]]
+set_property PACKAGE_PIN J17  [get_ports lut_2_in[4]]
+
+set_property PACKAGE_PIN H5  [get_ports lut_1_out]
+set_property PACKAGE_PIN J5  [get_ports lut_2_out]
+
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[5]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[4]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports lut_1_out]
+set_property IOSTANDARD LVCMOS33 [get_ports lut_2_out]
diff --git a/fpga_interchange/site_router_tests/lut/test.yaml b/fpga_interchange/site_router_tests/lut/test.yaml
new file mode 100644
index 0000000..e299d81
--- /dev/null
+++ b/fpga_interchange/site_router_tests/lut/test.yaml
@@ -0,0 +1,28 @@
+test_case:
+  - place:
+    # Place cell `lut_2` at BEL `SLICE_X1Y8.SLICEL/A6LUT`
+      lut_1: SLICE_X1Y8.SLICEL/A6LUT
+  - test:
+    # Make sure this placement is accept
+      SLICE_X1Y8.SLICEL/A6LUT: true
+  - unplace:
+      SLICE_X1Y8.SLICEL/A6LUT
+   # - place:
+   #    lut_1: SLICE_X1Y8.SLICEL/B6LUT
+   # - test:
+   #   # Make sure this placement is accept
+   #   SLICE_X1Y8.SLICEL/A6LUT: true
+   #   SLICE_X1Y8.SLICEL/B6LUT: true
+   # - place:
+   #    lut_1: SLICE_X1Y8.SLICEL/A6LUT
+   #    lut_2: SLICE_X1Y8.SLICEL/A5LUT
+   # - test:
+   #   # The site is now invalid because too many signals into the A6/A5LUT
+   #   SLICE_X1Y8.SLICEL/A6LUT: false
+   #   SLICE_X1Y8.SLICEL/A5LUT: false
+   # - unplace:
+   #    - lut_2
+   # - test:
+   #   # By removing lut_2, the site is valid again
+   #   SLICE_X1Y8.SLICEL/A6LUT: true
+   #   SLICE_X1Y8.SLICEL/A5LUT: true