blob: 117d8fe2eaff83909381fcc50795f6f83ae49306 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
|
`timescale 1ns / 1ps
module top(input clock,
output led);
reg [23:0] count = 0;
always @ (posedge clock)
begin
count <= count + 1'b1;
end
assign led = count[23];
endmodule
|