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/**
* PLL configuration
*
* This Verilog module was generated automatically
* using the icepll tool from the IceStorm project.
* Use at your own risk.
*
* Given input frequency: 100.000 MHz
* Requested output frequency: 16.000 MHz
* Achieved output frequency: 16.016 MHz
*/
module pll(
input clock_in,
output clock_out,
output locked
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0011), // DIVR = 3
.DIVF(7'b0101000), // DIVF = 40
.DIVQ(3'b110), // DIVQ = 6
.FILTER_RANGE(3'b010) // FILTER_RANGE = 2
) uut (
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clock_in),
.PLLOUTCORE(clock_out)
);
endmodule
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