blob: 199c07f150c345ba43c702a212e4120d513eed9b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
`include "pll.v"
module top (
input pclk, // 100MHz clock
output led1,
output led2,
input button,
output led3
);
reg button_read;
reg [20:0] cntr;
wire lock;
wire fclock;
pll mypll(pclk,fclock,lock);
always@(posedge fclock) begin
if (~lock) cntr <= 21'h00000000;
else cntr<= cntr+1;
button_read <= button;
end
assign led1 = button_read;
assign led2 = cntr[19];
assign led3 = cntr[20];
endmodule
|
