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authorgatecat <gatecat@ds0.me>2021-04-20 11:33:51 +0100
committerGitHub <noreply@github.com>2021-04-20 11:33:51 +0100
commit95698827b876c5afa368ed8746d155d68a8b6bbf (patch)
tree2af311119f6ff54222020691248d0509ccd9ad69 /.github/workflows/interchange_ci.yml
parent6fbefb8f1388dbb2bfe059624f7cb76ee9a81c5e (diff)
parent0e6955a08dabf744cb57e6c440ff3ab62fd2a507 (diff)
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Merge pull request #682 from YosysHQ/gatecat/default-cellpins
interchange: Handle missing/disconnected cell pins
Diffstat (limited to '.github/workflows/interchange_ci.yml')
-rw-r--r--.github/workflows/interchange_ci.yml2
1 files changed, 1 insertions, 1 deletions
diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml
index 31036465..e8f1c153 100644
--- a/.github/workflows/interchange_ci.yml
+++ b/.github/workflows/interchange_ci.yml
@@ -108,7 +108,7 @@ jobs:
env:
RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
- PYTHON_INTERCHANGE_TAG: v0.0.9
+ PYTHON_INTERCHANGE_TAG: v0.0.10
PRJOXIDE_REVISION: a85135648c3ef2f7b3fd53ae2187ef6460e34b16
DEVICE: ${{ matrix.device }}
run: |