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| author | gatecat <gatecat@ds0.me> | 2021-04-20 11:33:51 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-20 11:33:51 +0100 |
| commit | 95698827b876c5afa368ed8746d155d68a8b6bbf (patch) | |
| tree | 2af311119f6ff54222020691248d0509ccd9ad69 /3rdparty/fpga-interchange-schema | |
| parent | 6fbefb8f1388dbb2bfe059624f7cb76ee9a81c5e (diff) | |
| parent | 0e6955a08dabf744cb57e6c440ff3ab62fd2a507 (diff) | |
| download | nextpnr-95698827b876c5afa368ed8746d155d68a8b6bbf.tar.gz nextpnr-95698827b876c5afa368ed8746d155d68a8b6bbf.tar.bz2 nextpnr-95698827b876c5afa368ed8746d155d68a8b6bbf.zip | |
Merge pull request #682 from YosysHQ/gatecat/default-cellpins
interchange: Handle missing/disconnected cell pins
Diffstat (limited to '3rdparty/fpga-interchange-schema')
| m--------- | 3rdparty/fpga-interchange-schema | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/3rdparty/fpga-interchange-schema b/3rdparty/fpga-interchange-schema -Subproject 8ec5b1739d7b91b84df3e92ccc70c7a7ee64408 +Subproject 5208d794d318e9151b93120d7e5ba75d8aef45e |