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| author | Sylvain Munaut <tnt@246tNt.com> | 2020-06-02 11:02:48 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-06-02 11:03:04 +0200 |
| commit | 5e2b6bcef945a89daa215d01e15120162f81da7b (patch) | |
| tree | 3e81b142d49c8cfde7e331f88de71043259e8c86 /3rdparty/python-console/ParseHelper.BracketParseState.cpp | |
| parent | f44498a5301f9f516488fb748c684926be514346 (diff) | |
| download | nextpnr-5e2b6bcef945a89daa215d01e15120162f81da7b.tar.gz nextpnr-5e2b6bcef945a89daa215d01e15120162f81da7b.tar.bz2 nextpnr-5e2b6bcef945a89daa215d01e15120162f81da7b.zip | |
ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE
This requires the matching chipdb update from icestorm project !
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to '3rdparty/python-console/ParseHelper.BracketParseState.cpp')
0 files changed, 0 insertions, 0 deletions