Merge pull request #690 from YosysHQ/gatecat/interchange-wire-types

interchange: Add wire types

5 files changed, 39 insertions, 4 deletions

diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml
index e8f1c153..4e94076d 100644
--- a/.github/workflows/interchange_ci.yml
+++ b/.github/workflows/interchange_ci.yml
@@ -108,8 +108,8 @@ jobs:
       env:
         RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
         PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
-        PYTHON_INTERCHANGE_TAG: v0.0.10
-        PRJOXIDE_REVISION: a85135648c3ef2f7b3fd53ae2187ef6460e34b16
+        PYTHON_INTERCHANGE_TAG: v0.0.11
+        PRJOXIDE_REVISION: b5d88c3491770559c3c10cccb1651db65ab061b1
         DEVICE: ${{ matrix.device }}
       run: |
         export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
diff --git a/3rdparty/fpga-interchange-schema b/3rdparty/fpga-interchange-schema
-Subproject 5208d794d318e9151b93120d7e5ba75d8aef45e
+Subproject b3ab09776c8dc31a71ca2c7fbcb4575219232d1
diff --git a/common/arch_pybindings_shared.h b/common/arch_pybindings_shared.h
index 69d7025f..c2fe3e24 100644
--- a/common/arch_pybindings_shared.h
+++ b/common/arch_pybindings_shared.h
@@ -67,6 +67,8 @@ fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelP
 
 fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
               conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
+fn_wrapper_1a<Context, decltype(&Context::getWireType), &Context::getWireType, conv_to_str<IdString>,
+              conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireType");
 fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
                 addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
 fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 441c2e1f..c49a172b 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -461,7 +461,24 @@ WireId Arch::getWireByName(IdStringList name) const
     return ret;
 }
 
-IdString Arch::getWireType(WireId wire) const { return id(""); }
+IdString Arch::getWireType(WireId wire) const
+{
+    int tile = wire.tile, index = wire.index;
+    if (tile == -1) {
+        // Nodal wire
+        const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
+        tile = wr.tile;
+        index = wr.index;
+    }
+    auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
+    if (index >= w2t.ssize())
+        return IdString();
+    int wire_type = w2t[index];
+    if (wire_type == -1)
+        return IdString();
+    return IdString(chip_info->wire_types[wire_type].name);
+}
+
 std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
 
 // -----------------------------------------------------------------------
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h
index b66640e3..e9cac84e 100644
--- a/fpga_interchange/chipdb.h
+++ b/fpga_interchange/chipdb.h
@@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
  * kExpectedChipInfoVersion
  */
 
-static constexpr int32_t kExpectedChipInfoVersion = 7;
+static constexpr int32_t kExpectedChipInfoVersion = 8;
 
 // Flattened site indexing.
 //
@@ -182,6 +182,9 @@ NPNR_PACKED_STRUCT(struct TileInstInfoPOD {
     // as they will never be nodal
     // -1 if a tile-local wire; node index if nodal wire
     RelSlice<int32_t> tile_wire_to_node;
+
+    // Index into wire_types
+    RelSlice<int16_t> tile_wire_to_type;
 });
 
 NPNR_PACKED_STRUCT(struct TileWireRefPOD {
@@ -305,6 +308,18 @@ NPNR_PACKED_STRUCT(struct ConstantsPOD {
     RelSlice<DefaultCellConnsPOD> default_conns;
 });
 
+enum WireCategory
+{
+    WIRE_CAT_GENERAL = 0,
+    WIRE_CAT_SPECIAL = 1,
+    WIRE_CAT_GLOBAL = 2,
+};
+
+NPNR_PACKED_STRUCT(struct WireTypePOD {
+    int32_t name;     // constid
+    int32_t category; // WireCategory
+});
+
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<char> name;
     RelPtr<char> generator;
@@ -317,6 +332,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelSlice<TileInstInfoPOD> tiles;
     RelSlice<NodeInfoPOD> nodes;
     RelSlice<PackagePOD> packages;
+    RelSlice<WireTypePOD> wire_types;
 
     // BEL bucket constids.
     RelSlice<int32_t> bel_buckets;