Merge pull request #790 from acomodi/place-only-same-cluster-in-site

interchange: place only cells belonging to the same clusters in the same site

4 files changed, 24 insertions, 11 deletions

diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml
index 4dec38b2..05220abd 100644
--- a/.github/workflows/interchange_ci.yml
+++ b/.github/workflows/interchange_ci.yml
@@ -114,7 +114,7 @@ jobs:
       env:
         RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
         PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
-        PYTHON_INTERCHANGE_TAG: v0.0.17
+        PYTHON_INTERCHANGE_TAG: v0.0.18
         PRJOXIDE_REVISION: 1bf30dee9c023c4c66cfc44fd0bc28addd229c89
         DEVICE: ${{ matrix.device }}
       run: |
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 0fb4f462..7873a8ec 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -859,6 +859,9 @@ struct Arch : ArchAPI<ArchRanges>
         const TileStatus &tile_status = iter->second;
         const CellInfo *cell = tile_status.boundcells[bel.index];
 
+        auto &bel_data = bel_info(chip_info, bel);
+        auto &site_status = get_site_status(tile_status, bel_data);
+
         if (cell != nullptr) {
             if (!dedicated_interconnect.isBelLocationValid(bel, cell))
                 return false;
@@ -873,14 +876,23 @@ struct Arch : ArchAPI<ArchRanges>
             if (!is_cell_valid_constraints(cell, tile_status, explain_constraints)) {
                 return false;
             }
+
+            for (auto ci : site_status.cells_in_site) {
+                if (ci->cluster != ClusterId() && ci->cluster != cell->cluster &&
+                    cluster_info(chip_info, clusters.at(ci->cluster).index).disallow_other_cells)
+                    return false;
+
+                if (cell->cluster != ClusterId() && ci->cluster != cell->cluster &&
+                    cluster_info(chip_info, clusters.at(cell->cluster).index).disallow_other_cells)
+                    return false;
+            }
         }
 
         // Still check site status if cell is nullptr; as other bels in the site could be illegal (for example when
         // dedicated paths can no longer be used after ripping up a cell)
-        auto &bel_data = bel_info(chip_info, bel);
-        bool site_status = get_site_status(tile_status, bel_data).checkSiteRouting(getCtx(), tile_status);
+        bool routing_status = site_status.checkSiteRouting(getCtx(), tile_status);
 
-        return site_status;
+        return routing_status;
     }
 
     CellInfo *getClusterRootCell(ClusterId cluster) const override;
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h
index 9ebbc1f3..85dc7f25 100644
--- a/fpga_interchange/chipdb.h
+++ b/fpga_interchange/chipdb.h
@@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
  * kExpectedChipInfoVersion
  */
 
-static constexpr int32_t kExpectedChipInfoVersion = 13;
+static constexpr int32_t kExpectedChipInfoVersion = 14;
 
 // Flattened site indexing.
 //
@@ -422,6 +422,7 @@ NPNR_PACKED_STRUCT(struct ClusterPOD {
     RelSlice<ChainablePortPOD> chainable_ports;
     RelSlice<ClusterCellPortPOD> cluster_cells_map;
     uint32_t out_of_site_clusters;
+    uint32_t disallow_other_cells;
 });
 
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index 947081f4..a4781ed3 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -192,7 +192,7 @@ struct SiteExpansionLoop
     }
 
     // Expand from wire specified, always downhill.
-    bool expand_net(const SiteArch *ctx, SiteRoutingCache *site_routing_cache, const SiteNetInfo *net)
+    bool expand_net(const SiteArch *ctx, SiteRoutingCache *site_routing_cache, const SiteNetInfo *net, bool cache_disabled = false)
     {
         if (net->driver == net_driver && net->users == net_users) {
             return expand_result;
@@ -203,7 +203,7 @@ struct SiteExpansionLoop
         net_driver = net->driver;
         net_users = net->users;
 
-        if (site_routing_cache->get_solution(ctx, *net, &solution)) {
+        if (!cache_disabled && site_routing_cache->get_solution(ctx, *net, &solution)) {
             expand_result = true;
             return expand_result;
         }
@@ -316,7 +316,7 @@ struct SiteExpansionLoop
             targets.erase(wire);
         }
 
-        if (targets.empty()) {
+        if (!cache_disabled && targets.empty()) {
             site_routing_cache->add_solutions(ctx, *net, solution);
         }
 
@@ -699,7 +699,7 @@ static bool find_solution_via_backtrack(SiteArch *ctx, std::vector<PossibleSolut
 }
 
 static bool route_site(SiteArch *ctx, SiteRoutingCache *site_routing_cache, RouteNodeStorage *node_storage,
-                       bool explain)
+                       bool explain, bool cache_disabled = false)
 {
     // Overview:
     // - Starting from each site net source, expand the site routing graph
@@ -723,7 +723,7 @@ static bool route_site(SiteArch *ctx, SiteRoutingCache *site_routing_cache, Rout
         expansions.push_back(net->net->loop);
 
         SiteExpansionLoop *router = expansions.back();
-        if (!router->expand_net(ctx, site_routing_cache, net)) {
+        if (!router->expand_net(ctx, site_routing_cache, net, cache_disabled)) {
             if (verbose_site_router(ctx) || explain) {
                 log_info("Net %s expansion failed to reach all users, site is unroutable!\n", ctx->nameOfNet(net));
             }
@@ -1415,7 +1415,7 @@ void SiteRouter::bindSiteRouting(Context *ctx)
     block_lut_outputs(&site_arch, blocked_wires);
     block_cluster_wires(&site_arch);
     reserve_site_ports(&site_arch);
-    NPNR_ASSERT(route_site(&site_arch, &ctx->site_routing_cache, &ctx->node_storage, /*explain=*/false));
+    NPNR_ASSERT(route_site(&site_arch, &ctx->site_routing_cache, &ctx->node_storage, /*explain=*/false, /*cache_disabled=*/true));
 
     check_routing(site_arch);
     apply_routing(ctx, site_arch, lut_thrus);