Merge pull request #101 from daveshah1/ecp5_pll

WIP: ecp5: Add PLL support and improve global promotion/routint

7 files changed, 257 insertions, 40 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index ab3e15c0..4a0b31b5 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -651,6 +651,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
         return TMG_IGNORE; // FIXME
     } else if (cell->type == id_ALU54B) {
         return TMG_IGNORE; // FIXME
+    } else if (cell->type == id_EHXPLLL) {
+        return TMG_IGNORE;
     } else {
         NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
     }
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 0a5de822..583d539f 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -491,7 +491,7 @@ struct Arch : BaseCtx
     BelId getBelByLocation(Loc loc) const;
     BelRange getBelsByTile(int x, int y) const;
 
-    bool getBelGlobalBuf(BelId bel) const { return false; }
+    bool getBelGlobalBuf(BelId bel) const { return getBelType(bel) == id_DCCA; }
 
     bool checkBelAvail(BelId bel) const
     {
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index c7b5d562..95256732 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -378,6 +378,32 @@ std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel)
     }
     return tiles;
 }
+
+// Get the list of tiles corresponding to a PLL
+std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel)
+{
+    std::string name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+    std::vector<std::string> tiles;
+    Loc loc = ctx->getBelLocation(bel);
+
+    if (name == "EHXPLL_UL") {
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UL"));
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UL"));
+    } else if (name == "EHXPLL_LL") {
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LL"));
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x + 1, "BANKREF8"));
+    } else if (name == "EHXPLL_LR") {
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LR"));
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_LR"));
+    } else if (name == "EHXPLL_UR") {
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UR"));
+        tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UR"));
+    } else {
+        NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
+    }
+    return tiles;
+}
+
 void fix_tile_names(Context *ctx, ChipConfig &cc)
 {
     // Remove the V prefix/suffix on certain tiles if device is a SERDES variant
@@ -390,7 +416,7 @@ void fix_tile_names(Context *ctx, ChipConfig &cc)
             auto vcib = tile.first.find("VCIB");
             if (vcib != std::string::npos) {
                 // Remove the V
-                newname.erase(vcib);
+                newname.erase(vcib, 1);
                 tiletype_xform[tile.first] = newname;
             } else if (tile.first.back() == 'V') {
                 // BMID_0V or BMID_2V
@@ -429,6 +455,14 @@ void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
     }
 }
 
+static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
+{
+    std::string tile = ctx->getPipTilename(pip);
+    std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
+    std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
+    cc.tiles[tile].add_arc(sink, source);
+}
+
 void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
 {
     ChipConfig cc;
@@ -450,10 +484,16 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
     for (auto pip : ctx->getPips()) {
         if (ctx->getBoundPipNet(pip) != nullptr) {
             if (ctx->getPipClass(pip) == 0) { // ignore fixed pips
-                std::string tile = ctx->getPipTilename(pip);
                 std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
-                std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
-                cc.tiles[tile].add_arc(sink, source);
+                if (source.find("CLKI_PLL") != std::string::npos) {
+                    // Special case - must set pip in all relevant tiles
+                    for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
+                        if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
+                            set_pip(ctx, cc, equiv_pip);
+                    }
+                } else {
+                    set_pip(ctx, cc, pip);
+                }
             }
         }
     }
@@ -624,6 +664,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
                 cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
             }
+            if (ci->attrs.count(ctx->id("SLEWRATE")))
+                cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
         } else if (ci->type == ctx->id("DCCA")) {
             // Nothing to do
         } else if (ci->type == ctx->id("DP16KD")) {
@@ -867,7 +909,96 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             }
             tieoff_dsp_ports(ctx, cc, ci);
             cc.tilegroups.push_back(tg);
+        } else if (ci->type == id_EHXPLLL) {
+            TileGroup tg;
+            tg.tiles = get_pll_tiles(ctx, ci->bel);
+
+            tg.config.add_enum("MODE", "EHXPLLL");
+
+            tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, ctx->id("CLKI_DIV"), 1) - 1, 7));
+            tg.config.add_word("CLKFB_DIV",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1) - 1, 7));
+
+            tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, ctx->id("CLKOP_ENABLE"), "ENABLED"));
+            tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, ctx->id("CLKOS_ENABLE"), "ENABLED"));
+            tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, ctx->id("CLKOS2_ENABLE"), "ENABLED"));
+            tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, ctx->id("CLKOS3_ENABLE"), "ENABLED"));
+
+            for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
+                tg.config.add_word(out + "_DIV",
+                                   int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
+                tg.config.add_word(out + "_CPHASE",
+                                   int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
+                tg.config.add_word(out + "_FPHASE",
+                                   int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
+            }
 
+            tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"));
+            tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOP_TRIM_POL"), "RISING"));
+            tg.config.add_enum("CLKOP_TRIM_DELAY", str_or_default(ci->params, ctx->id("CLKOP_TRIM_DELAY"), "0"));
+            tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOS_TRIM_POL"), "RISING"));
+            tg.config.add_enum("CLKOS_TRIM_DELAY", str_or_default(ci->params, ctx->id("CLKOS_TRIM_DELAY"), "0"));
+
+            tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXA"),
+                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
+            tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXB"),
+                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
+            tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXC"),
+                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
+            tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXD"),
+                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
+
+            tg.config.add_word("PLL_LOCK_MODE",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id("PLL_LOCK_MODE"), 0), 3));
+
+            tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, ctx->id("STDBY_ENABLE"), "DISABLED"));
+            tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, ctx->id("REFIN_RESET"), "DISABLED"));
+            tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, ctx->id("SYNC_ENABLE"), "DISABLED"));
+            tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, ctx->id("INT_LOCK_STICKY"), "ENABLED"));
+            tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, ctx->id("DPHASE_SOURCE"), "DISABLED"));
+            tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, ctx->id("PLLRST_ENA"), "DISABLED"));
+            tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, ctx->id("INTFB_WAKE"), "DISABLED"));
+
+            tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, ctx->id("KVCO"), 0), 3));
+            tg.config.add_word("LPF_CAPACITOR",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_CAPACITOR"), 0), 2));
+            tg.config.add_word("LPF_RESISTOR",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_RESISTOR"), 0), 7));
+            tg.config.add_word("ICP_CURRENT",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("ICP_CURRENT"), 0), 5));
+            tg.config.add_word("FREQ_LOCK_ACCURACY",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("FREQ_LOCK_ACCURACY"), 0), 2));
+
+            tg.config.add_word("MFG_GMC_GAIN",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_GAIN"), 0), 3));
+            tg.config.add_word("MFG_GMC_TEST",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_TEST"), 14), 4));
+            tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG1_TEST"), 0), 3));
+            tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG2_TEST"), 0), 3));
+
+            tg.config.add_word("MFG_FORCE_VFILTER",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FORCE_VFILTER"), 0), 1));
+            tg.config.add_word("MFG_ICP_TEST",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ICP_TEST"), 0), 1));
+            tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_EN_UP"), 0), 1));
+            tg.config.add_word("MFG_FLOAT_ICP",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FLOAT_ICP"), 0), 1));
+            tg.config.add_word("MFG_GMC_PRESET",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_PRESET"), 0), 1));
+            tg.config.add_word("MFG_LF_PRESET",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_PRESET"), 0), 1));
+            tg.config.add_word("MFG_GMC_RESET",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_RESET"), 0), 1));
+            tg.config.add_word("MFG_LF_RESET",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESET"), 0), 1));
+            tg.config.add_word("MFG_LF_RESGRND",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESGRND"), 0), 1));
+            tg.config.add_word("MFG_GMCREF_SEL",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMCREF_SEL"), 0), 2));
+            tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
+                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1));
+
+            cc.tilegroups.push_back(tg);
         } else {
             NPNR_ASSERT_FALSE("unsupported cell type");
         }
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index e3bfec6e..bdcbc1ea 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -787,3 +787,26 @@ X(OVER)
 X(UNDER)
 X(OVERUNDER)
 X(SIGNEDR)
+
+X(EHXPLLL)
+X(CLKFB)
+X(PHASESEL1)
+X(PHASESEL0)
+X(PHASEDIR)
+X(PHASESTEP)
+X(PHASELOADREG)
+X(STDBY)
+X(PLLWAKESYNC)
+X(RST)
+X(ENCLKOP)
+X(ENCLKOS)
+X(ENCLKOS2)
+X(ENCLKOS3)
+X(CLKOP)
+X(CLKOS)
+X(CLKOS2)
+X(CLKOS3)
+X(LOCK)
+X(INTLOCK)
+X(REFCLK)
+X(CLKINTFB)
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 5e5a2a01..06412fef 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -25,6 +25,7 @@
 #include "log.h"
 #include "nextpnr.h"
 #include "place_common.h"
+#include "util.h"
 #define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -257,6 +258,45 @@ class Ecp5GlobalRouter
         return true;
     }
 
+    // Get DCC wirelength based on source
+    wirelen_t get_dcc_wirelen(CellInfo *dcc)
+    {
+        NetInfo *clki = dcc->ports.at(id_CLKI).net;
+        BelId drv_bel;
+        const PortRef &drv = clki->driver;
+        if (drv.cell == nullptr) {
+            return 0;
+        } else if (drv.cell->attrs.count(ctx->id("BEL"))) {
+            drv_bel = ctx->getBelByName(ctx->id(drv.cell->attrs.at(ctx->id("BEL"))));
+        } else {
+            // Check if driver is a singleton
+            BelId last_bel;
+            bool singleton = true;
+            for (auto bel : ctx->getBels()) {
+                if (ctx->getBelType(bel) == drv.cell->type) {
+                    if (last_bel != BelId()) {
+                        singleton = false;
+                        break;
+                    }
+                    last_bel = bel;
+                }
+            }
+            if (singleton && last_bel != BelId()) {
+                drv_bel = last_bel;
+            }
+        }
+        if (drv_bel == BelId()) {
+            // Driver is not locked. Use standard metric
+            float tns;
+            return get_net_metric(ctx, clki, MetricType::WIRELENGTH, tns);
+        } else {
+            // Driver is locked
+            Loc dcc_loc = ctx->getBelLocation(dcc->bel);
+            Loc drv_loc = ctx->getBelLocation(drv_bel);
+            return std::abs(dcc_loc.x - drv_loc.x) + std::abs(dcc_loc.y - drv_loc.y);
+        }
+    }
+
     // Attempt to place a DCC
     void place_dcc(CellInfo *dcc)
     {
@@ -266,8 +306,7 @@ class Ecp5GlobalRouter
             if (ctx->getBelType(bel) == id_DCCA && ctx->checkBelAvail(bel)) {
                 if (ctx->isValidBelForCell(dcc, bel)) {
                     ctx->bindBel(bel, dcc, STRENGTH_LOCKED);
-                    float tns;
-                    wirelen_t wirelen = get_net_metric(ctx, dcc->ports.at(id_CLKI).net, MetricType::WIRELENGTH, tns);
+                    wirelen_t wirelen = get_dcc_wirelen(dcc);
                     if (wirelen < best_wirelen) {
                         best_bel = bel;
                         best_wirelen = wirelen;
@@ -292,11 +331,16 @@ class Ecp5GlobalRouter
         glbnet->is_global = true;
         dcc->ports[id_CLKO].net = glbnet.get();
 
-        glbnet->users = net->users;
+        std::vector<PortRef> keep_users;
         for (auto user : net->users) {
-            user.cell->ports.at(user.port).net = glbnet.get();
+            if (user.port == id_CLKFB) {
+                keep_users.push_back(user);
+            } else {
+                glbnet->users.push_back(user);
+                user.cell->ports.at(user.port).net = glbnet.get();
+            }
         }
-        net->users.clear();
+        net->users = keep_users;
 
         dcc->ports[id_CLKI].net = net;
         PortRef clki_pr;
@@ -322,47 +366,61 @@ class Ecp5GlobalRouter
     Context *ctx;
 
   public:
-    void promote_and_route_globals()
+    void promote_globals()
     {
-        log_info("Promoting and routing globals...\n");
+        log_info("Promoting globals...\n");
         auto clocks = get_clocks();
+        for (auto clock : clocks) {
+            log_info("    promoting clock net %s to global network\n", clock->name.c_str(ctx));
+            insert_dcc(clock);
+        }
+    }
+
+    void route_globals()
+    {
+        log_info("Routing globals...\n");
         std::set<int> all_globals, fab_globals;
         for (int i = 0; i < 16; i++) {
             all_globals.insert(i);
             if (i < 8)
                 fab_globals.insert(i);
         }
-        for (auto clock : clocks) {
-            bool drives_fabric = std::any_of(clock->users.begin(), clock->users.end(),
-                                             [this](const PortRef &port) { return !is_clock_port(port); });
-            int glbid;
-            if (drives_fabric) {
-                if (fab_globals.empty())
-                    continue;
-                glbid = *(fab_globals.begin());
-            } else {
-                glbid = *(all_globals.begin());
-            }
-            all_globals.erase(glbid);
-            fab_globals.erase(glbid);
-            log_info("    promoting clock net %s to global %d\n", clock->name.c_str(ctx), glbid);
-            auto old_users = clock->users;
-            NetInfo *global = insert_dcc(clock);
-            bool routed = route_onto_global(global, glbid);
-            NPNR_ASSERT(routed);
-
-            // WCK must have routing priority
-            auto sorted_users = global->users;
-            std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
-                return global_route_priority(a) < global_route_priority(b);
-            });
-            for (const auto &user : sorted_users) {
-                route_logic_tile_global(global, glbid, user);
+        for (auto cell : sorted(ctx->cells)) {
+            CellInfo *ci = cell.second;
+            if (ci->type == id_DCCA) {
+                NetInfo *clock = ci->ports.at(id_CLKO).net;
+                NPNR_ASSERT(clock != nullptr);
+                bool drives_fabric = std::any_of(clock->users.begin(), clock->users.end(),
+                                                 [this](const PortRef &port) { return !is_clock_port(port); });
+
+                int glbid;
+                if (drives_fabric) {
+                    if (fab_globals.empty())
+                        continue;
+                    glbid = *(fab_globals.begin());
+                } else {
+                    glbid = *(all_globals.begin());
+                }
+                all_globals.erase(glbid);
+                fab_globals.erase(glbid);
+
+                log_info("    routing clock net %s using global %d\n", clock->name.c_str(ctx), glbid);
+                bool routed = route_onto_global(clock, glbid);
+                NPNR_ASSERT(routed);
+
+                // WCK must have routing priority
+                auto sorted_users = clock->users;
+                std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
+                    return global_route_priority(a) < global_route_priority(b);
+                });
+                for (const auto &user : sorted_users) {
+                    route_logic_tile_global(clock, glbid, user);
+                }
             }
         }
     }
 };
-
-void route_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_and_route_globals(); }
+void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); }
+void route_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).route_globals(); }
 
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/globals.h b/ecp5/globals.h
index 23e25c8d..cc7cf98e 100644
--- a/ecp5/globals.h
+++ b/ecp5/globals.h
@@ -21,6 +21,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+void promote_ecp5_globals(Context *ctx);
 void route_ecp5_globals(Context *ctx);
 
 NEXTPNR_NAMESPACE_END
\ No newline at end of file
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index cb111fc6..73e15609 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -24,6 +24,7 @@
 #include "cells.h"
 #include "chain_utils.h"
 #include "design_utils.h"
+#include "globals.h"
 #include "log.h"
 #include "util.h"
 NEXTPNR_NAMESPACE_BEGIN
@@ -1047,6 +1048,7 @@ class Ecp5Packer
         pack_lut_pairs();
         pack_remaining_luts();
         pack_remaining_ffs();
+        promote_ecp5_globals(ctx);
         ctx->check();
     }