ecp5: clangformat timing changes

Signed-off-by: David Shah <dave@ds0.me>

4 files changed, 18 insertions, 19 deletions

diff --git a/common/timing.cc b/common/timing.cc
index 4012c374..7ab24c25 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -659,7 +659,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                     }
                 }
                 last_port = sink->port;
-
             }
             int clockCount = 0;
             auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
@@ -670,7 +669,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                 log_info("%4.1f %4.1f  Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total),
                          crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx));
             }
-
         };
 
         for (auto &clock : clock_reports) {
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 0ae063a2..fc3c97bf 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -740,7 +740,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             info.clockToQ = getDelayFromNS(0.7);
         } else {
             info.setup = getDelayFromNS(1);
-            info.hold  = getDelayFromNS(0);
+            info.hold = getDelayFromNS(0);
         }
     }
     return info;
diff --git a/ecp5/arch.h b/ecp5/arch.h
index cf30876b..a68673f4 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -828,10 +828,12 @@ struct Arch : BaseCtx
         if (fnd_fanout != wire_fanout.end())
             fanout = fnd_fanout->second;
         NPNR_ASSERT(locInfo(pip)->pip_data[pip.index].timing_class < speed_grade->num_pip_classes);
-        delay.min_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay
-                + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
-        delay.max_delay = speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay
-                + fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
+        delay.min_delay =
+                speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_base_delay +
+                fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
+        delay.max_delay =
+                speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_base_delay +
+                fanout * speed_grade->pip_classes[locInfo(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
         return delay;
     }
 
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 8e1ee8d4..12afb09d 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -122,24 +122,23 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext()
         if (vm.count("speed")) {
             int speed = vm["speed"].as<int>();
             switch (speed) {
-                case 6:
-                    chipArgs.speed = ArchArgs::SPEED_6;
-                    break;
-                case 7:
-                    chipArgs.speed = ArchArgs::SPEED_7;
-                    break;
-                case 8:
-                    chipArgs.speed = ArchArgs::SPEED_8;
-                    break;
-                default:
-                    log_error("Unsupported speed grade '%d'\n", speed);
+            case 6:
+                chipArgs.speed = ArchArgs::SPEED_6;
+                break;
+            case 7:
+                chipArgs.speed = ArchArgs::SPEED_7;
+                break;
+            case 8:
+                chipArgs.speed = ArchArgs::SPEED_8;
+                break;
+            default:
+                log_error("Unsupported speed grade '%d'\n", speed);
             }
         } else {
             chipArgs.speed = ArchArgs::SPEED_6;
         }
     }
 
-
     return std::unique_ptr<Context>(new Context(chipArgs));
 }