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author | Maciej Kurc <mkurc@antmicro.com> | 2022-03-15 10:43:31 +0100 |
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committer | Maciej Kurc <mkurc@antmicro.com> | 2022-03-15 10:43:31 +0100 |
commit | 1cc71c7846463c401b63c15cf7da3c674b50269e (patch) | |
tree | 63d7fd61c9172710c1e129a72b4bc33864339678 | |
parent | 6ed625be8e4e4f6f1ec7d74d4180b4ed60c96f9d (diff) | |
download | nextpnr-1cc71c7846463c401b63c15cf7da3c674b50269e.tar.gz nextpnr-1cc71c7846463c401b63c15cf7da3c674b50269e.tar.bz2 nextpnr-1cc71c7846463c401b63c15cf7da3c674b50269e.zip |
nexus: Added FASM feature emission for DCC and port timing class info
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
-rw-r--r-- | nexus/arch.cc | 8 | ||||
-rw-r--r-- | nexus/fasm.cc | 12 |
2 files changed, 20 insertions, 0 deletions
diff --git a/nexus/arch.cc b/nexus/arch.cc index cb8cacf8..0241e832 100644 --- a/nexus/arch.cc +++ b/nexus/arch.cc @@ -546,6 +546,14 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in if (type == TMG_REGISTER_INPUT || type == TMG_REGISTER_OUTPUT) clockInfoCount = 1; return type; + } else if (cell->type == id_DCC) { + if (port == id_CLKI) + return TMG_CLOCK_INPUT; + else if (port == id_CLKO) + return TMG_GEN_CLOCK; + else if (port == id_CE) + return TMG_COMB_INPUT; + return TMG_IGNORE; } return TMG_IGNORE; } diff --git a/nexus/fasm.cc b/nexus/fasm.cc index c460e14b..c8404587 100644 --- a/nexus/fasm.cc +++ b/nexus/fasm.cc @@ -526,6 +526,16 @@ struct NexusFasmWriter write_cell_muxes(cell); pop(2); } + // Write config for DCC + void write_dcc(const CellInfo *cell) + { + BelId bel = cell->bel; + push_tile(bel.tile); + push_belname(bel); + write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer + write_cell_muxes(cell); + pop(2); + } // Write config for an OXIDE_EBR cell void write_bram(const CellInfo *cell) { @@ -927,6 +937,8 @@ struct NexusFasmWriter write_dphy(ci); else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) write_iol(ci); + else if (ci->type == id_DCC) + write_dcc(ci); blank(); } // Handle DCC route-throughs |