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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-13 18:10:09 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-13 18:10:09 +0200 |
| commit | 3d5954f9972a1962d76c4eb1f2eb13a13128f372 (patch) | |
| tree | edc65d2f28f5ac1662e447fd91da09d9437e0678 | |
| parent | 794fc6df607d76cd3763dea75f7c93ad48aa306f (diff) | |
| download | nextpnr-3d5954f9972a1962d76c4eb1f2eb13a13128f372.tar.gz nextpnr-3d5954f9972a1962d76c4eb1f2eb13a13128f372.tar.bz2 nextpnr-3d5954f9972a1962d76c4eb1f2eb13a13128f372.zip | |
Improve router error messages
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | common/route.cc | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/common/route.cc b/common/route.cc index 79bf13b0..02fbfe96 100644 --- a/common/route.cc +++ b/common/route.cc @@ -86,8 +86,11 @@ void route_design(Design *design, bool verbose) auto src_wire = chip.getWireBelPin(src_bel, portPinFromId(driver_port)); if (src_wire == WireId()) - log_error("No wire found for port %s on source bel.\n", - net_info->driver.port.c_str()); + log_error("No wire found for port %s (pin %s) on source cell %s " + "(bel %s).\n", + net_info->driver.port.c_str(), driver_port.c_str(), + net_info->driver.cell->name.c_str(), + chip.getBelName(src_bel).c_str()); if (verbose) log(" Source wire: %s\n", chip.getWireName(src_wire).c_str()); @@ -106,7 +109,9 @@ void route_design(Design *design, bool verbose) auto dst_pos = chip.getBelPosition(dst_bel); if (dst_bel == BelId()) - log_error("Destination cell is not mapped to a bel.\n"); + log_error("Destination cell %s (%s) is not mapped to a bel.\n", + user_it.cell->name.c_str(), + user_it.cell->type.c_str()); if (verbose) { log(" Destination bel: %s\n", @@ -126,8 +131,11 @@ void route_design(Design *design, bool verbose) chip.getWireBelPin(dst_bel, portPinFromId(user_port)); if (dst_wire == WireId()) - log_error("No wire found for port %s on destination bel.\n", - user_it.port.c_str()); + log_error("No wire found for port %s (pin %s) on destination " + "cell %s (bel %s).\n", + user_it.port.c_str(), user_port.c_str(), + user_it.cell->name.c_str(), + chip.getBelName(dst_bel).c_str()); if (verbose) log(" Destination wire: %s\n", |