basectx: Add a field to store timing results

Signed-off-by: gatecat <gatecat@ds0.me>

5 files changed, 31 insertions, 1 deletions

diff --git a/common/arch_pybindings_shared.h b/common/arch_pybindings_shared.h
index c2fe3e24..46f1f9be 100644
--- a/common/arch_pybindings_shared.h
+++ b/common/arch_pybindings_shared.h
@@ -9,6 +9,8 @@ readonly_wrapper<Context, decltype(&Context::hierarchy), &Context::hierarchy, wr
         ctx_cls, "hierarchy");
 readwrite_wrapper<Context, decltype(&Context::top_module), &Context::top_module, conv_to_str<IdString>,
                   conv_from_str<IdString>>::def_wrap(ctx_cls, "top_module");
+readonly_wrapper<Context, decltype(&Context::timing_result), &Context::timing_result,
+                 wrap_context<TimingResult &>>::def_wrap(ctx_cls, "timing_result");
 
 fn_wrapper_0a<Context, decltype(&Context::getNameDelimiter), &Context::getNameDelimiter, pass_through<char>>::def_wrap(
         ctx_cls, "getNameDelimiter");
diff --git a/common/basectx.h b/common/basectx.h
index dbfdf5ee..507f29cd 100644
--- a/common/basectx.h
+++ b/common/basectx.h
@@ -84,6 +84,9 @@ struct BaseCtx
     // Context meta data
     dict<IdString, Property> attrs;
 
+    // Fmax data post timing analysis
+    TimingResult timing_result;
+
     Context *as_ctx = nullptr;
 
     // Has the frontend loaded a design?
diff --git a/common/nextpnr_types.h b/common/nextpnr_types.h
index bbf61934..1cae3dbe 100644
--- a/common/nextpnr_types.h
+++ b/common/nextpnr_types.h
@@ -217,6 +217,18 @@ struct ClockConstraint
     DelayPair period;
 };
 
+struct ClockFmax
+{
+    float achieved;
+    float constraint;
+};
+
+struct TimingResult
+{
+    // Achieved and target Fmax for all clock domains
+    dict<IdString, ClockFmax> clock_fmax;
+};
+
 // Represents the contents of a non-leaf cell in a design
 // with hierarchy
 
diff --git a/common/pybindings.cc b/common/pybindings.cc
index bdd4f92a..2f672a41 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -285,8 +285,16 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
     WRAP_MAP(m, WireMap, wrap_context<PipMap &>, "WireMap");
     WRAP_MAP_UPTR(m, RegionMap, "RegionMap");
 
-    WRAP_VECTOR(m, PortRefVector, wrap_context<PortRef &>);
+    typedef dict<IdString, ClockFmax> ClockFmaxMap;
+    WRAP_MAP(m, ClockFmaxMap, pass_through<ClockFmax>, "ClockFmaxMap");
 
+    auto clk_fmax_cls = py::class_<ClockFmax>(m, "ClockFmax")
+                                .def_readonly("achieved", &ClockFmax::achieved)
+                                .def_readonly("constraint", &ClockFmax::constraint);
+
+    auto tmg_result_cls = py::class_<ContextualWrapper<TimingResult &>>(m, "TimingResult");
+    readonly_wrapper<TimingResult &, decltype(&TimingResult::clock_fmax), &TimingResult::clock_fmax,
+                     wrap_context<ClockFmaxMap &>>::def_wrap(tmg_result_cls, "clock_fmax");
     arch_wrap_python(m);
 }
 
diff --git a/common/timing.cc b/common/timing.cc
index d110498c..0cdb5be2 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -1315,6 +1315,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     if (print_fmax) {
         log_break();
         unsigned max_width = 0;
+        auto &result = ctx->timing_result;
+        result.clock_fmax.clear();
         for (auto &clock : clock_reports)
             max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
         for (auto &clock : clock_reports) {
@@ -1324,6 +1326,9 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             if (ctx->nets.at(clock.first)->clkconstr)
                 target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay());
 
+            result.clock_fmax[clock.first].achieved = clock_fmax[clock.first];
+            result.clock_fmax[clock.first].constraint = target;
+
             bool passed = target < clock_fmax[clock.first];
             if (!warn_on_failure || passed)
                 log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",