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| author | David Shah <dave@ds0.me> | 2019-09-03 11:53:43 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-09-03 11:53:43 +0100 |
| commit | 4d8fa130334376640432a7b5d371cd0bfae46cb5 (patch) | |
| tree | 2ab7cf989d9264f5b1c86b914978c52fbd5005b7 | |
| parent | c06d7390b61adebb6a6c368edf0cc92a9432374a (diff) | |
| download | nextpnr-4d8fa130334376640432a7b5d371cd0bfae46cb5.tar.gz nextpnr-4d8fa130334376640432a7b5d371cd0bfae46cb5.tar.bz2 nextpnr-4d8fa130334376640432a7b5d371cd0bfae46cb5.zip | |
ice40: Fix DSP cascade wires
Signed-off-by: David Shah <dave@ds0.me>
| -rw-r--r-- | ice40/chipdb.py | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index cc7be01f..195c08ae 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -969,10 +969,15 @@ def add_bel_ec(ec): last_dsp_y = 23 else: assert False, "unknown DSP y " + str(y) - wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout") - wire_signextout = add_wire(x, y, "dsp/signextout") - wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco") - wire_accumco = add_wire(x, y, "dsp/accumco") + def add_if_new(x, y, name): + if (x, y, name) in wire_names: + return wire_names[(x, y, name)] + else: + return add_wire(x, y, name) + wire_signextin = add_if_new(x, last_dsp_y, "dsp/signextout") + wire_signextout = add_if_new(x, y, "dsp/signextout") + wire_accumci = add_if_new(x, last_dsp_y, "dsp/accumco") + wire_accumco = add_if_new(x, y, "dsp/accumco") add_bel_input(bel, wire_signextin, "SIGNEXTIN") add_bel_output(bel, wire_signextout, "SIGNEXTOUT") add_bel_input(bel, wire_accumci, "ACCUMCI") |