timing: Add Fmax printing for debugging

Signed-off-by: gatecat <gatecat@ds0.me>

2 files changed, 23 insertions, 0 deletions

diff --git a/common/timing.cc b/common/timing.cc
index d39aced8..f46df189 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -39,6 +39,7 @@ void TimingAnalyser::setup()
     reset_times();
     walk_forward();
     walk_backward();
+    print_fmax();
 }
 
 void TimingAnalyser::init_ports()
@@ -386,6 +387,26 @@ void TimingAnalyser::walk_backward()
     }
 }
 
+void TimingAnalyser::print_fmax()
+{
+    // Temporary testing code for comparison only
+    std::unordered_map<int, double> domain_fmax;
+    for (auto p : topological_order) {
+        auto &pd = ports.at(p);
+        for (auto &req : pd.required) {
+            if (pd.arrival.count(req.first)) {
+                auto &arr = pd.arrival.at(req.first);
+                double fmax = 1000.0 / (arr.value.maxDelay() - req.second.value.minDelay());
+                if (!domain_fmax.count(req.first) || domain_fmax.at(req.first) > fmax)
+                    domain_fmax[req.first] = fmax;
+            }
+        }
+    }
+    for (auto &fm : domain_fmax) {
+        log_info("Domain %s Worst Fmax %.02f\n", ctx->nameOf(domains.at(fm.first).key.clock), fm.second);
+    }
+}
+
 domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockEdge edge)
 {
     return domain_id(ctx->cells.at(cell)->ports.at(clock_port).net, edge);
diff --git a/common/timing.h b/common/timing.h
index b050e671..de30ee61 100644
--- a/common/timing.h
+++ b/common/timing.h
@@ -140,6 +140,8 @@ struct TimingAnalyser
     void walk_forward();
     void walk_backward();
 
+    void print_fmax();
+
     const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
 
     // Set arrival/required times if more/less than the current value